Search results for "cmp"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
164	Norma Rodriguez, Li Song, Shishir Shroff, Kuang Han Chen, Taber Smith, Wilbur Luo	Hotspot Prevention Using CMP Model in Design Implementation Flow.	ISQED	2008	DBLP DOI BibTeX RDF	CMP modeling, CMP aware design, hotspot
122	Alberto Ros 0001, Manuel E. Acacio, José M. García 0001	DiCo-CMP: Efficient cache coherency in tiled CMP architectures.	IPDPS	2008	DBLP DOI BibTeX RDF
103	Andrew B. Kahng, Puneet Sharma, Alexander Zelikovsky	Fill for shallow trench isolation CMP.	ICCAD	2006	DBLP DOI BibTeX RDF
103	Ravi R. Iyer 0001, Mahesh Bhat, Li Zhao 0002, Ramesh Illikkal, Srihari Makineni, Michael Jones, Kumar Shiv, Donald Newell	Exploring Small-Scale and Large-Scale CMP Architectures for Commercial Java Servers.	IISWC	2006	DBLP DOI BibTeX RDF
100	Kypros Constantinides, Stephen Plaza, Jason A. Blome, Valeria Bertacco, Scott A. Mahlke, Todd M. Austin, Bin Zhang 0011, Michael Orshansky	Architecting a reliable CMP switch architecture.	ACM Trans. Archit. Code Optim.	2007	DBLP DOI BibTeX RDF	CMP switch, reliability, defect-tolerance
92	Ruchira Sasanka, Sarita V. Adve, Yen-Kuang Chen, Eric Debes	The energy efficiency of CMP vs. SMT for multimedia workloads.	ICS	2004	DBLP DOI BibTeX RDF	multimedia, energy efficiency, CMP, SMT
84	Yanming Jia, Yici Cai, Xianlong Hong	Full-chip routing system for reducing Cu CMP & ECP variation.	SBCCI	2008	DBLP DOI BibTeX RDF	electroplating, routing, chemical mechanical polishing
84	Minsik Cho, David Z. Pan, Hua Xiang 0001, Ruchir Puri	Wire density driven global routing for CMP variation and timing.	ICCAD	2006	DBLP DOI BibTeX RDF	performance, VLSI, manufacturability, global routing
84	Yingmin Li, David M. Brooks, Zhigang Hu, Kevin Skadron	Performance, Energy, and Thermal Considerations for SMT and CMP Architectures.	HPCA	2005	DBLP DOI BibTeX RDF
76	Dmitry G. Korzun, Andrei V. Gurtov	A local equilibrium model for P2P resource ranking.	SIGMETRICS Perform. Evaluation Rev.	2009	DBLP DOI BibTeX RDF
76	Bill Lin 0001, Jun (Jim) Xu, Nan Hua, Hao Wang 0006, Haiquan (Chuck) Zhao	A randomized interleaved DRAM architecture for the maintenance of exact statistics counters.	SIGMETRICS Perform. Evaluation Rev.	2009	DBLP DOI BibTeX RDF
76	Sipat Triukose, Zhihua Wen, Michael Rabinovich	Content delivery networks: how big is big enough?	SIGMETRICS Perform. Evaluation Rev.	2009	DBLP DOI BibTeX RDF
76	Alma Riska, Erik Riedel	Evaluation of disk-level workloads at different time scales.	SIGMETRICS Perform. Evaluation Rev.	2009	DBLP DOI BibTeX RDF
76	Alberto Ros 0001, Manuel E. Acacio, José M. García 0001	Dealing with Traffic-Area Trade-Off in Direct Coherence Protocols for Many-Core CMPs.	APPT	2009	DBLP DOI BibTeX RDF
76	Carmelo Acosta, Francisco J. Cazorla, Alex Ramírez, Mateo Valero	MFLUSH: Handling Long-Latency Loads in SMT On-Chip Multiprocessors.	ICPP	2008	DBLP DOI BibTeX RDF
75	Andrew B. Kahng, Kambiz Samadi	CMP Fill Synthesis: A Survey of Recent Studies.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
75	Sewook Wee, Jared Casper, Njuguna Njoroge, Yuriy Teslyar, Daxia Ge, Christos Kozyrakis, Kunle Olukotun	A practical FPGA-based framework for novel CMP research.	FPGA	2007	DBLP DOI BibTeX RDF	FPGA-based emulation, transactional memory, chip multi-processor
75	Yuxing Tang, Kun Deng, Xingming Zhou	The Design Space of CMP vs. SMT for High Performance Embedded Processor.	ICESS	2005	DBLP DOI BibTeX RDF
75	Jason Cong, Ashok Jagannathan, Glenn Reinman, Yuval Tamir	Understanding the energy efficiency of SMT and CMP with multiclustering.	ISLPED	2005	DBLP DOI BibTeX RDF	energy efficiency, simultaneous multithreading, chip multiprocessing
73	Min-Chun Tsai	A formula of STI cmp design rule.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	sti, topography, cmp, design rules, dfm
73	Yin Shen, Yici Cai, Qiang Zhou 0001, Xianlong Hong	DFM Based Detailed Routing Algorithm for ECP and CMP.	ISQED	2008	DBLP DOI BibTeX RDF	ECP, CMP, DFM, detailed routing
73	Linzhi Ning, Wenbin Yao, Jun Ni, Nianmin Yao	Fault-Tolerance CMP Architecture based on SMT Technology.	IMSCCS	2007	DBLP DOI BibTeX RDF	fault tolerance, CMP, thread, SMT
73	Mohamed A. Gomaa, Michael D. Powell, T. N. Vijaykumar	Heat-and-run: leveraging SMT and CMP to manage power density through the operating system.	ASPLOS	2004	DBLP DOI BibTeX RDF	CMP, migration, SMT, heat, power density
72	Lei He 0001, Andrew B. Kahng, King Ho Tam, Jinjun Xiong	Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random leff variation.	ISPD	2005	DBLP DOI BibTeX RDF	yield, buffering, design for manufacturing, wire sizing, chemical mechanical polishing (CMP)
65	Eddy Z. Zhang, Yunlian Jiang, Xipeng Shen	Does cache sharing on modern CMP matter to the performance of contemporary multithreaded programs?	PPoPP	2010	DBLP DOI BibTeX RDF	parallel program optimizations, chip multiprocessors, shared cache, thread scheduling
65	Jaideep Moses, Konstantinos Aisopos, Aamer Jaleel, Ravi R. Iyer 0001, Ramesh Illikkal, Donald Newell, Srihari Makineni	CMPSched$im: Evaluating OS/CMP interaction on shared cache management.	ISPASS	2009	DBLP DOI BibTeX RDF
65	Lih Wen-Chen, Satish T. S. Bukkapatnam, Prahalad K. Rao, Naga Chandrasekharan, Ranga Komanduri	Adaptive Neuro-Fuzzy Inference System Modeling of MRR and WIWNU in CMP Process With Sparse Experimental Data.	IEEE Trans Autom. Sci. Eng.	2008	DBLP DOI BibTeX RDF
65	Venkatesan Packirisamy, Yangchun Luo, Wei-Lung Hung, Antonia Zhai, Pen-Chung Yew, Tin-Fook Ngai	Efficiency of thread-level speculation in SMT and CMP architectures - performance, power and thermal perspective.	ICCD	2008	DBLP DOI BibTeX RDF
65	Vijaykumar Ramamurthi, Jason McCollum, Christopher Ostler, Karam S. Chatha	System Level Methodology for Programming CMP Based Multi-Threaded Network Processor Architectures.	ISVLSI	2005	DBLP DOI BibTeX RDF
65	Michael R. Marty, Jesse D. Bingham, Mark D. Hill, Alan J. Hu, Milo M. K. Martin, David A. Wood 0001	Improving Multiple-CMP Systems Using Token Coherence.	HPCA	2005	DBLP DOI BibTeX RDF
64	David K. Tam, Reza Azimi, Michael Stumm	Thread clustering: sharing-aware scheduling on SMP-CMP-SMT multiprocessors.	EuroSys	2007	DBLP DOI BibTeX RDF	cache behavior, detecting sharing, performance monitoring unit, single-chip multiprocessors, thread placement, resource allocation, CMP, multithreading, sharing, SMP, simultaneous multithreading, SMT, shared caches, cache locality, thread scheduling, thread migration, hardware performance monitors, hardware performance counters, affinity scheduling
57	Yadan Deng, Ning Jing, Wei Xiong 0010, Chen Luo, Hongsheng Chen	Hash Join Optimization Based on Shared Cache Chip Multi-processor.	DASFAA	2009	DBLP DOI BibTeX RDF	Radix-Join, Shared L2-Cache, Chip Multi-Processor, Cache Conflict
57	Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginosar, Avinoam Kolodny	The Power of Priority: NoC Based Distributed Cache Coherency.	NOCS	2007	DBLP DOI BibTeX RDF
57	Christof Pitter, Martin Schoeberl	Towards a Java multiprocessor.	JTRES	2007	DBLP DOI BibTeX RDF	Java, multiprocessor, shared memory
57	Masayuki Abe, Ronald Cramer, Serge Fehr	Non-interactive Distributed-Verifier Proofs and Proving Relations among Commitments.	ASIACRYPT	2002	DBLP DOI BibTeX RDF
56	Yuanming Zhang, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba	Clustered Decoupled Software Pipelining on Commodity CMP.	ICPADS	2008	DBLP DOI BibTeX RDF
56	Donald Newell	Workloads, Scalability, and QoS Considerations in CMP Platforms.	ISPASS	2007	DBLP DOI BibTeX RDF
56	Pengyong Ma, Shuming Chen	M2SI: An Improved Coherency Protocol in CMP.	IEEE NAS	2007	DBLP DOI BibTeX RDF
56	Kypros Constantinides, Stephen Plaza, Jason A. Blome, Bin Zhang 0011, Valeria Bertacco, Scott A. Mahlke, Todd M. Austin, Michael Orshansky	BulletProof: a defect-tolerant CMP switch architecture.	HPCA	2006	DBLP DOI BibTeX RDF
56	James Burns, Jean-Luc Gaudiot	Area and System Clock Effects on SMT/CMP Throughput.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	layout area estimation, microarchitecture trade off, processor architecture, SMT
56	Khaled Z. Ibrahim, Gregory T. Byrd, Eric Rotenberg	Slipstream Execution Mode for CMP-Based Multiprocessors.	HPCA	2003	DBLP DOI BibTeX RDF
56	James Burns, Jean-Luc Gaudiot	Area and System Clock Effects on SMT/CMP Processors.	IEEE PACT	2001	DBLP DOI BibTeX RDF
56	Stefanos Kaxiras, Girija J. Narlikar, Alan D. Berenbaum, Zhigang Hu	Comparing power consumption of an SMT and a CMP DSP for mobile phone workloads.	CASES	2001	DBLP DOI BibTeX RDF
56	Haixun Wang, Carlo Zaniolo	CMP: A Fast Decision Tree Classifier Using Multivariate Predictions.	ICDE	2000	DBLP DOI BibTeX RDF
54	Jiuzhen Jin, Jianmin Pang, Zheng Shan, Rongcai Zhao	Queuing Network Performance Model for Evaluation of CMP-Based VoIP SPS.	ACIS-ICIS	2008	DBLP DOI BibTeX RDF	GI/G/m-FCFS open Queuing Network, Performance Evaluation, CMP, SPS
54	Ravi R. Iyer 0001, Li Zhao 0002, Fei Guo, Ramesh Illikkal, Srihari Makineni, Donald Newell, Yan Solihin, Lisa R. Hsu, Steven K. Reinhardt	QoS policies and architecture for cache/memory in CMP platforms.	SIGMETRICS	2007	DBLP DOI BibTeX RDF	cache/memory, resource sharing priniciples, QoS, quality of service, performance, CMP, service level agreements
54	Ravi R. Iyer 0001	CQoS: a framework for enabling QoS in shared caches of CMP platforms.	ICS	2004	DBLP DOI BibTeX RDF	QoS, performance, cache, partitioning, CMP, sharing
53	Jisheng Zhao, Matthew Horsnell, Mikel Luján, Ian Rogers, Chris C. Kirkham, Ian Watson	Adaptive Loop Tiling for a Multi-cluster CMP.	ICA3PP	2008	DBLP DOI BibTeX RDF	Multi-Cluster CMP, Automatic Parallelization, Loop Tiling, Feedback-Directed Optimization
48	Wenlong Li, Eric Q. Li, Aamer Jaleel, Jiulong Shan, Yurong Chen 0001, Qigang Wang, Ravi R. Iyer 0001, Ramesh Illikkal, Yimin Zhang 0002, Dong Liu, Michael Liao, Wei Wei, Jinhua Du	Understanding the Memory Performance of Data-Mining Workloads on Small, Medium, and Large-Scale CMPs Using Hardware-Software Co-simulation.	ISPASS	2007	DBLP DOI BibTeX RDF	DRAM caches, small-scale CMP, medium-scale CMP, large-scale CMP, hardware-software co-simulation, terabyte-level workloads, multithreaded data mining applications, cache design, memory performance, multicore systems, memory system performance
47	Fei Guo, Yan Solihin, Li Zhao 0002, Ravishankar R. Iyer 0001	A Framework for Providing Quality of Service in Chip Multi-Processors.	MICRO	2007	DBLP DOI BibTeX RDF
47	David A. Penry, Daniel Fay, David Hodgdon, Ryan Wells, Graham Schelle, David I. August, Dan Connors	Exploiting parallelism and structure to accelerate the simulation of chip multi-processors.	HPCA	2006	DBLP DOI BibTeX RDF
47	Ruiqi Tian, Xiaoping Tang, Martin D. F. Wong	Dummy-feature placement for chemical-mechanical polishinguniformity in a shallow-trench isolation process.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
47	Ruiqi Tian, Martin D. F. Wong, Robert Boone	Model-based dummy feature placement for oxide chemical-mechanicalpolishing manufacturability.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
47	Ruiqi Tian, Xiaoping Tang, D. F. Wong 0001	Dummy feature placement for chemical-mechanical polishing uniformity in a shallow trench isolation process.	ISPD	2001	DBLP DOI BibTeX RDF
47	Ruiqi Tian, D. F. Wong 0001, Robert Boone	Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability.	DAC	2000	DBLP DOI BibTeX RDF
47	David Wai-Lok Cheung, Bo Zhou, Ben Kao, Hongjun Lu, Tak Wah Lam, Hing-Fung Ting	Requirement-Based Data Cube Schema Design.	CIKM	1999	DBLP DOI BibTeX RDF	data cube schema design, DSS, OLAP, data cubes
47	Hsiao-Feng Steven Chen, D. T. Lee	On crossing minimization problem.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
47	Andrew Herdrich, Ramesh Illikkal, Ravi R. Iyer 0001, Donald Newell, Vineet Chadha, Jaideep Moses	Rate-based QoS techniques for cache/memory in CMP platforms.	ICS	2009	DBLP DOI BibTeX RDF	p-states, performance differentiation, t-states, cache, memory, rate control, qos, clock gating, frequency scaling, dvfs
47	Brian M. Rogers, Anil Krishna, Gordon B. Bell, Ken V. Vu, Xiaowei Jiang, Yan Solihin	Scaling the bandwidth wall: challenges in and avenues for CMP scaling.	ISCA	2009	DBLP DOI BibTeX RDF	analytical model, memory bandwidth, chip multi-processor
47	Antonio Flores, Juan L. Aragón, Manuel E. Acacio	An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures.	J. Supercomput.	2008	DBLP DOI BibTeX RDF	Power dissipation model, Microarchitectural level simulator, Heterogeneus on-chip interconnection network, Chip-multiprocessor, Parallel scientific applications
47	Tung-Chieh Chen, Minsik Cho, David Z. Pan, Yao-Wen Chang	Metal-Density-Driven Placement for CMP Variation and Routability.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
47	Lei He 0001, Andrew B. Kahng, King Ho Tam, Jinjun Xiong	Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random Leff Variation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
47	Richard T. Saunders, Clinton L. Jeffery, Derek T. Jones	A Portable Framework for High-Speed Parallel Producer/Consumers on Real CMP, SMT and SMP Architectures.	IPDPS	2007	DBLP DOI BibTeX RDF
47	Antonio Flores, Juan L. Aragón, Manuel E. Acacio	Sim-PowerCMP: A Detailed Simulator for Energy Consumption Analysis in Future Embedded CMP Architectures.	AINA Workshops (1)	2007	DBLP DOI BibTeX RDF
47	Bratin Saha, Ali-Reza Adl-Tabatabai, Anwar M. Ghuloum, Mohan Rajagopalan, Richard L. Hudson, Leaf Petersen, Vijay Menon 0002, Brian R. Murphy, Tatiana Shpeisman, Eric Sprangle, Anwar Rohillah, Doug Carmean, Jesse Fang	Enabling scalability and performance in a large scale CMP environment.	EuroSys	2007	DBLP DOI BibTeX RDF	runtime design, scheduler design, sequestered mode, parallel programming, memory management, transactional memory, multi-core processors, synchronization primitives
47	Xuemei Zhao, Karl Sammut, Fangpo He	Performance Evaluation of a Novel CMP Cache Structure for Hybrid Workloads.	PDCAT	2007	DBLP DOI BibTeX RDF
47	Aamer Jaleel, Matthew Mattina, Bruce L. Jacob	Last level cache (LLC) performance of data mining workloads on a CMP - a case study of parallel bioinformatics workloads.	HPCA	2006	DBLP DOI BibTeX RDF
47	Kyriakos Stavrou, Paraskevas Evripidou, Pedro Trancoso	DDM-CMP: Data-Driven Multithreading on a Chip Multiprocessor.	SAMOS	2005	DBLP DOI BibTeX RDF
47	Gang Xu, Ruiqi Tian, David Z. Pan, Martin D. F. Wong	CMP aware shuttle mask floorplanning.	ASP-DAC	2005	DBLP DOI BibTeX RDF
47	Jose Renau, Karin Strauss, Luis Ceze, Wei Liu 0014, Smruti R. Sarangi, James Tuck 0001, Josep Torrellas	Thread-Level Speculation on a CMP can be energy efficient.	ICS	2005	DBLP DOI BibTeX RDF
45	Sanjeev Kumar, Christopher J. Hughes, Anthony D. Nguyen	Carbon: architectural support for fine-grained parallelism on chip multiprocessors.	ISCA	2007	DBLP DOI BibTeX RDF	loop and task parallelism, CMP, architectural support
45	Li Zhao 0002, Ravi R. Iyer 0001, Jaideep Moses, Ramesh Illikkal, Srihari Makineni, Donald Newell	Exploring Large-Scale CMP Architectures Using ManySim.	IEEE Micro	2007	DBLP DOI BibTeX RDF	performance evaluation, architecture, CMP, workload characterization, servers, simulation techniques
44	Hamid Shojaei, Amir Hossein Ghamarian, Twan Basten, Marc Geilen, Sander Stuijk, Rob Hoes	A parameterized compositional multi-dimensional multiple-choice knapsack heuristic for CMP run-time management.	DAC	2009	DBLP DOI BibTeX RDF	CMP run-time management, MMKP, Pareto algebra
44	Li Zhao 0002, Ravi R. Iyer 0001, Srihari Makineni, Ramesh Illikkal, Jaideep Moses, Donald Newell	Constraint-Aware Large-Scale CMP Cache Design.	HiPC	2007	DBLP DOI BibTeX RDF	Large Scale CMP, constraint-aware design, CAAM, LCMP, cache hierarchy
44	Shuichi Sakai	CMP on SoC: Architect's View.	ISSS	2002	DBLP DOI BibTeX RDF	CMP (Chip Multiprocessor), I/O centric, SoC (System on Chip), parallel processing, dependability
38	Yaoguang Wei, Sachin S. Sapatnekar	Dummy fill optimization for enhanced manufacturability.	ISPD	2010	DBLP DOI BibTeX RDF	routing, design for manufacturability, chemical-mechanical polishing, dummy fill
38	Takeshi Ogasawara	Scalability limitations when running a Java web server on a chip multiprocessor.	SYSTOR	2010	DBLP DOI BibTeX RDF	performance, multi-cores, JVMs, web servers
38	Jaejin Lee, Changhee Jung, Daeseob Lim, Yan Solihin	Prefetching with Helper Threads for Loosely Coupled Multiprocessor Systems.	IEEE Trans. Parallel Distributed Syst.	2009	DBLP DOI BibTeX RDF
38	Reetuparna Das, Soumya Eachempati, Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das	Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs.	HPCA	2009	DBLP DOI BibTeX RDF
38	Noriko Takagi, Hiroshi Sasaki 0001, Masaaki Kondo, Hiroshi Nakamura	Cooperative shared resource access control for low-power chip multiprocessors.	ISLPED	2009	DBLP DOI BibTeX RDF	low power, chip multiprocessors, cache partitioning, dvfs, resource conflict
38	Yefu Wang, Kai Ma, Xiaorui Wang	Temperature-constrained power control for chip multiprocessors with online model estimation.	ISCA	2009	DBLP DOI BibTeX RDF	power management, chip multiprocessor, feedback control
38	Rezaul Alam Chowdhury, Vijaya Ramachandran	Cache-efficient dynamic programming algorithms for multicores.	SPAA	2008	DBLP DOI BibTeX RDF	parallelism, multicore, shared cache, distributed cache, cache-efficiency
38	Jason Cong, Guoling Han, Ashok Jagannathan, Glenn Reinman, Krzysztof Rutkowski	Accelerating Sequential Applications on CMPs Using Core Spilling.	IEEE Trans. Parallel Distributed Syst.	2007	DBLP DOI BibTeX RDF
38	Salman Khan 0002, Polychronis Xekalakis, John Cavazos, Marcelo Cintra	Using PredictiveModeling for Cross-Program Design Space Exploration in Multicore Systems.	PACT	2007	DBLP DOI BibTeX RDF
38	Philip Machanick	Design principles for a virtual multiprocessor.	SAICSIT	2007	DBLP DOI BibTeX RDF	chip multiprocessor, instruction-level parallelism
38	James Tuck 0001, Wei Liu 0014, Josep Torrellas	CAP: Criticality analysis for power-efficient speculative multithreading.	ICCD	2007	DBLP DOI BibTeX RDF
38	Nan Wang, Xuhui Liu, Jin He, Jizhong Han, Lisheng Zhang, Zhiyong Xu 0003	Collaborative Memory Pool in Cluster System.	ICPP	2007	DBLP DOI BibTeX RDF
38	Pedro Trancoso, Paraskevas Evripidou, Kyriakos Stavrou, Costas Kyriacou	A Case for Chip Multiprocessors Based on the Data-Driven Multithreading Model.	Int. J. Parallel Program.	2006	DBLP DOI BibTeX RDF	data-driven execution, parallel processing, Chip multiprocessor, multithreading
38	Francisco J. Villa, Manuel E. Acacio, José M. García 0001	On the Evaluation of Dense Chip-Multiprocessor Architectures.	ICSAMOS	2006	DBLP DOI BibTeX RDF
38	Haixia Wang 0001, Dongsheng Wang 0002, Peng Li 0031	Acceleration Techniques for Chip-Multiprocessor Simulator Debug.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF
38	Kyriakos Stavrou, Pedro Trancoso, Paraskevas Evripidou	Hardware Budget and Runtime System for Data-Driven Multithreaded Chip Multiprocessor.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF
38	Jichuan Chang, Gurindar S. Sohi	Cooperative Caching for Chip Multiprocessors.	ISCA	2006	DBLP DOI BibTeX RDF
37	Huang-Yu Chen, Szu-Jui Chou, Yao-Wen Chang	Density gradient minimization with coupling-constrained dummy fill for CMP control.	ISPD	2010	DBLP DOI BibTeX RDF	density gradient, manufacturability, chemical-mechanical polishing, dummy fill
37	Huang-Yu Chen, Szu-Jui Chou, Sheng-Lung Wang, Yao-Wen Chang	A Novel Wire-Density-Driven Full-Chip Routing System for CMP Variation Control.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
37	Ricardo Fernández Pascual, José M. García 0001, Manuel E. Acacio, José Duato	Extending the TokenCMP Cache Coherence Protocol for Low Overhead Fault Tolerance in CMP Architectures.	IEEE Trans. Parallel Distributed Syst.	2008	DBLP DOI BibTeX RDF
37	Zhimin Gu, Ninghan Zheng, Jie Tang Yan Huang	An analysis and experimental approach to teaching data prefetching on CMP.	Summit on Computing Education in China	2008	DBLP DOI BibTeX RDF	data push, data prefetching
37	Song Hao, Zhihui Du, David A. Bader, Man Wang	A Prediction Based CMP Cache Migration Policy.	HPCC	2008	DBLP DOI BibTeX RDF
37	Tung-Chieh Chen, Minsik Cho, David Z. Pan, Yao-Wen Chang	Metal-density driven placement for cmp variation and routability.	ISPD	2008	DBLP DOI BibTeX RDF	VLSI, placement, physical design, manufacturability
37	Haixia Wang 0001, Dongsheng Wang 0002, Peng Li 0031, Jinglei Wang, XianPing Fu	Exploit Temporal Locality of Shared Data in SRC Enabled CMP.	NPC	2007	DBLP DOI BibTeX RDF
37	Jie Tao 0001, Kim D. Hoàng, Wolfgang Karl	CMP Cache Architecture and the OpenMP Performance.	IWOMP	2007	DBLP DOI BibTeX RDF