Search results for "co-timing"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
80	Liang-Chi Chen, Sandeep K. Gupta 0001, Melvin A. Breuer	A new framework for static timing analysis, incremental timing refinement, and timing simulation.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	incremental timing refinement, signal arrival, target fault, test generation efficiency, logic testing, delays, timing, test generation, integrated circuit testing, computation, automatic test pattern generation, ATPG, static timing analysis, delay model, timing simulation
77	Amit Chowdhary, Karthik Rajagopal, Satish Venkatesan, Tung Cao, Vladimir Tiourin, Yegna Parasuram, Bill Halpin	How accurately can we model timing in a placement engine?	DAC	2005	DBLP DOI BibTeX RDF	differential timing analysis, linear programming, static timing analysis, timing-driven placement
73	John V. A. Janeri, Daylan B. Darby, Daniel D. Schnackenberg	Building higher resolution synthetic clocks for signaling in covert timing channels.	CSFW	1995	DBLP DOI BibTeX RDF	higher resolution synthetic clocks, timing channel countermeasure, Boeing multilevel secure local area network, secure network server, internal timing channels, time reference clock granularity, fine-grained signaling clock, timing channel throughput, timing channel capacities, local area networks, security of data, worst-case analysis, covert timing channels
69	Natarajan Viswanathan, Gi-Joon Nam, Jarrod A. Roy, Zhuo Li 0001, Charles J. Alpert, Shyam Ramji, Chris Chu	ITOP: integrating timing optimization within placement.	ISPD	2010	DBLP DOI BibTeX RDF	placement, timing optimization, physical synthesis
67	Aloysius K. Mok, Guangtian Liu	Early detection of timing constraint violation at runtime.	RTSS	1997	DBLP DOI BibTeX RDF	timing constraint violation detection, timing constraint compliance, conditional guarantees, satisfiability checking algorithm, timing constraint monitoring, time terms, timing constraint specification, real-time systems, real time applications
65	Avi Efrati, Moshe Kleyner	Timing analysis challenges for high speed CPUs at 90nm and below.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF
64	Jeffrey J. P. Tsai, Steve Jennhwa Yang, Yao-Hsiung Chang	Timing Constraint Petri Nets and Their Application to Schedulability Analysis of Real-Time System Specifications.	IEEE Trans. Software Eng.	1995	DBLP DOI BibTeX RDF	real-time systems, Petri nets, synthesis, timing analysis, Timing constraints, time Petri nets, timed Petri nets, specification and verification
60	Ali Dasdan, Dinesh Ramanathan, Rajesh K. Gupta 0001	A timing-driven design and validation methodology for embedded real-time systems.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	period assignment, period derivation, rate assignment, rate derivation, timing-driven codesign, requirements analysis, timing analysis, system-level design, performance verification
58	Aseem Agarwal, David T. Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula	Statistical timing analysis using bounds and selective enumeration.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF
57	Duane S. Boning, Joseph Panganiban, Karen Gonzalez-Valentin, Sani R. Nassif, Chandler McDowell, Anne E. Gattiker, Frank Liu 0001	Test structures for delay variability.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF
57	Louis Scheffer	Explicit computation of performance as a function of process variation.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	static timing, process variation, yield, statistical timing
56	Leo Motus, R. Kinksaar, Tonu Naks, M. Pall	Enhancing object modelling technique with timing analysis capabilities.	ICECCS	1995	DBLP DOI BibTeX RDF	enhanced object modelling technique, timing analysis capabilities, timing correctness, software implementation problems, specification problems, time-constraint elicitation, Q-model, noncontradiction analysis, time modelling requirements, performance, software engineering, real-time systems, real-time systems, data integrity, timing, scheduling algorithms, timing constraints, object-oriented methods, consistency checking, application domain, integrity checking, design problems
55	Shuo Zhou, Yi Zhu 0002, Yuanfang Hu, Ronald L. Graham, Mike Hutton, Chung-Kuan Cheng	Timing model reduction for hierarchical timing analysis.	ICCAD	2006	DBLP DOI BibTeX RDF	biclique-star replacement, hierarchical timing analysis
54	Tai M. Chung, Henry G. Dietz	Static scheduling of hard real-time code with instruction-level timing accuracy.	RTCSA	1996	DBLP DOI BibTeX RDF	timing fault, instruction-level timing accuracy, high-level language code, instruction-level, compiler code scheduling, genetic search algorithm, real-time systems, timing analysis, processor scheduling, search space
54	Lo Ko, Christopher A. Healy, Emily Ratliff, Robert D. Arnold, David B. Whalley, Marion G. Harmon	Supporting the specification and analysis of timing constraints.	IEEE Real Time Technology and Applications Symposium	1996	DBLP DOI BibTeX RDF	timing constraints analysis, real-time programmers, user-friendly environment, user specification, real-time systems, user interface, formal specification, timing, synchronisation, timing constraints, computer aided software engineering, C language, C program, project support environments
53	Zhuo Feng, Peng Li 0001	A methodology for timing model characterization for statistical static timing analysis.	ICCAD	2007	DBLP DOI BibTeX RDF
53	Mukund Sivaraman, Andrzej J. Strojwas	Timing analysis based on primitive path delay fault identification.	ICCAD	1997	DBLP DOI BibTeX RDF	primitive path delay faults, correlated delay, floating mode, timing analysis, timing verification, false path, path delay fault testing
52	Ali Dasdan	Efficient algorithms for debugging timing constraint violations.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	over-constraint resolution, scheduling, high-level synthesis, constraint satisfaction, timing constraints, behavioral synthesis, rate analysis
52	Markus Lindgren, Hans Hansson, Henrik Thane	Using measurements to derive the worst-case execution time.	RTCSA	2000	DBLP DOI BibTeX RDF	execution time analysis, program flow analysis, low level timing information, low level timing analysis, program execution times, timing measurements, instrumented version, program fragments, non-exhaustive measurements, program paths, realistic processor model, scheduling, real-time systems, real time systems, embedded systems, worst-case execution time, pipeline processing, schedulability analysis, program diagnostics, architectural modeling, pipeline architectures, flow graphs, timing estimates, target architecture, system of linear equations
51	Steven Gianvecchio, Haining Wang	Detecting covert timing channels: an entropy-based approach.	CCS	2007	DBLP DOI BibTeX RDF	detection, covert timing channels
50	Kurt Keutzer, Michael Orshansky	From blind certainty to informed uncertainty.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF
49	Christopher J. Thompson, Andrew L. Goertzen	A Method for Determination of the Timing Stability of PET Scanners.	IEEE Trans. Medical Imaging	2005	DBLP DOI BibTeX RDF
49	Aloysius K. Mok, Guangtian Liu	Efficient Run-Time Monitoring of Timing Constraints.	IEEE Real Time Technology and Applications Symposium	1997	DBLP DOI BibTeX RDF
49	Vinod Narayanan, Barbara A. Chappell, Bruce M. Fleischer	Static timing analysis for self resetting circuits.	ICCAD	1996	DBLP DOI BibTeX RDF
49	Sung-Soo Lim, Young Hyun Bae, Gyu Tae Jang, Byung-Do Rhee, Sang Lyul Min, Chang Yun Park, Heonshik Shin, Kunsoo Park, Soo-Mook Moon, Chong-Sang Kim	An Accurate Worst Case Timing Analysis for RISC Processors.	IEEE Trans. Software Eng.	1995	DBLP DOI BibTeX RDF	pipelined execution, real-time system, Cache memory, worst case execution time, RISC processor
49	Amir Masoud Gharehbaghi, Bijan Alizadeh, Masahiro Fujita	Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	overclocking, timing error detection, timing error recovery, fpga
49	Ho Kyoung Lee, Woo Jin Lee, Heung Seok Chae, Yong Rae Kwon	Specification and analysis of timing requirements for real-time systems in the CBD approach.	Real Time Syst.	2007	DBLP DOI BibTeX RDF	Real-time system, Petri nets, Component, Timing analysis, Timing constraints, CBD, Compositional analysis
49	Liang-Chi Chen, Sandeep K. Gupta 0001, Melvin A. Breuer	TA-PSV - Timing Analysis for Partially Specified Vectors.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	timing analysis for partially specified vectors (TA-PSV), crosstalk test generation (ATPG), static timing analysis (STA), delay model
47	Uwe Fassnacht, Jürgen Schietke	Timing Analysis and Optimization of a High-Performance CMOS Processor Chipset.	DATE	1998	DBLP DOI BibTeX RDF	Timing, static timing analysis, timing optimization
46	Bhavana Thudi, David T. Blaauw	Efficient switching window computation for cross-talk noise.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF
46	Ed Grochowski, Murali Annavaram, Paul Reed	Implications of device timing variability on full chip timing.	ISPD	2008	DBLP DOI BibTeX RDF
46	Murali Annavaram, Ed Grochowski, Paul Reed	Implications of Device Timing Variability on Full Chip Timing.	HPCA	2007	DBLP DOI BibTeX RDF
46	Min Pan, Chris C. N. Chu, Hai Zhou 0001	Timing yield estimation using statistical static timing analysis.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
46	Tobias Thiel	Have I Really Met Timing? - Validating PrimeTime Timing Reports with Spice.	DATE	2004	DBLP DOI BibTeX RDF
45	Musab AlTurki, Dinakar Dhurjati, Dachuan Yu, Ajay Chander, Hiroshi Inamura	Formal Specification and Analysis of Timing Properties in Software Systems.	FASE	2009	DBLP DOI BibTeX RDF
45	Guilan Dai, Rujuan Liu, Chongchong Zhao, Changjun Hu	Timing Constraints Specification and Verification for Web Service Compositions.	APSCC	2008	DBLP DOI BibTeX RDF
45	Dipankar Das 0002, P. P. Chakrabarti 0001, Rajeev Kumar 0004	Scenario-based timing verification of multiprocessor embedded applications.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	execution scenarios, real time systems, static timing analysis, Timing verification
45	David A. Papa, Tao Luo 0002, Michael D. Moffitt, Chin Ngai Sze, Zhuo Li 0001, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov	RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm.	ISPD	2008	DBLP DOI BibTeX RDF	static timing analysis, timing-driven placement
45	Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Paula K. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, Nobuo Kojima, Ohsang Kwon, Kyung T. Lee, David Meltzer, Kevin J. Nowka, J. Park, J. Peter, Joel Silberman, Osamu Takahashi, Paul Villarrubia	"Timing closure by design, " a high frequency microprocessor design methodology.	DAC	2000	DBLP DOI BibTeX RDF	chip integration, dynamic circuits0, CAD, methodology, microprocessor, timing analysis, PLA, timing closure
43	Wei-Tek Tsai, Hessam S. Sarjoughian, Wu Li, Xin Sun 0003	Timing specification and analysis for service-oriented simulation.	SpringSim	2009	DBLP DOI BibTeX RDF	service-oriented simulation, timing specifications and analysis, DEVS
43	Shihheng Tsai, Chung-Yang Huang	A false-path aware formal static timing analyzer considering simultaneous input transitions.	DAC	2009	DBLP DOI BibTeX RDF	critical path selection, multiple input transitioning, formal method, static timing analysis, false path
43	Hanif Fatemi, Soroush Abbaspour, Massoud Pedram, Amir H. Ajami, Emre Tuncer	SACI: statistical static timing analysis of coupled interconnects.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	coupled interconnect, sources of variation, crosstalk noise, statistical timing analysis
43	Mike Hutton, David Karchmer, Bryan Archell, Jason Govig	Efficient static timing analysis and applications using edge masks.	FPGA	2005	DBLP DOI BibTeX RDF	cut-path, multicycle, thru-x, FPGA, placement, timing analysis
43	Chandramouli Visweswariah, K. Ravindran, Kerim Kalafala, Steven G. Walker, S. Narayan	First-order incremental block-based statistical timing analysis.	DAC	2004	DBLP DOI BibTeX RDF	variability, incremental, statistical timing
43	Yu Cao 0001, Xiaodong Yang, Xuejue Huang, Dennis Sylvester	Switch-Factor Based Loop RLC Modeling for Efficient Timing Analysis.	ICCAD	2003	DBLP DOI BibTeX RDF	RLC model, loop inductance, switch-factor, current return loop, data-bus and clock, static timing analysis, slew rate
43	Rajesh K. Gupta 0001	A framework for interactive analysis of timing constraints in embedded systems.	CODES	1996	DBLP DOI BibTeX RDF	constraint satisfiability, performance evaluation, real-time systems, embedded systems, timing, computability, logic design, satisfiability, timing constraints, interactive analysis, timing performance
43	Vinod Narayananan, David LaPotin, Rajesh Gupta 0003, Gopalakrishnan Vijayan	PEPPER - a timing driven early floorplanner.	ICCD	1995	DBLP DOI BibTeX RDF	PEPPER, timing driven early floorplanner, chip complexities, early analysis, performance critical CMOS chips, wireability, floorplan optimization process, performance, computational complexity, optimisation, timing, system design, circuit layout CAD, CMOS integrated circuits, static timing analysis, integrated circuit layout, area, interconnect delay
43	Anirudh Devgan	Accurate device modeling techniques for efficient timing simulation of integrated circuits.	ICCD	1995	DBLP DOI BibTeX RDF	device modeling techniques, Fast-to-evaluate and Accurate Simplified Transistor, aggressive MOS technologies, FAST models, timing, AGES, circuit analysis computing, integrated circuits, circuit simulators, transient analysis, transistors, transistor, transient simulator, timing simulation, timing simulator, electronic engineering computing, semiconductor device models
43	Hong-Yean Hsieh, Wentai Liu, Ralph K. Cavin III, C. Thomas Gray	Concurrent timing optimization of latch-based digital systems.	ICCD	1995	DBLP DOI BibTeX RDF	concurrent timing optimization, latch-based digital systems, digital system timing, intentional clock skew, latch-based designed systems, multi-phase clocking, resynchronization, latches insertion, optimisation, timing, logic design, flip-flops, retiming, mixed integer linear program, race conditions, integrated framework, wave pipelining, hazards and race conditions, clock period
43	Steve Brown, Germán Gutiérrez, Reed Nelson, Chris VanKrevelen	A gate-array based 500 MHz triple channel ATE controller with 40 pS timing verniers.	VTS	1995	DBLP DOI BibTeX RDF	emitter-coupled logic, triple channel ATE controller, timing verniers, precision edge timing, drive waveforms, returning signals, system clock frequency, ECL, 500 MHz, 40 ps, timing, clocks, automatic test equipment, logic arrays, programmable controllers, gate array, high speed testing
43	Hatice Kose-Bagci, Frank Broz, Qiming Shen, Kerstin Dautenhahn, Chrystopher L. Nehaniv	As Time Goes By: Representing and Reasoning About Timing in Human-Robot Interaction Studies.	AAAI Spring Symposium: It's All in the Timing	2010	DBLP BibTeX RDF
43	Aseem Agarwal, David T. Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula	Statistical timing analysis using bounds and selective enumeration.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF
42	Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye	Trade-off analysis between timing error rate and power dissipation for adaptive speed control with timing error prediction.	ASP-DAC	2009	DBLP DOI BibTeX RDF
42	Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen	Block based statistical timing analysis with extended canonical timing model.	ASP-DAC	2005	DBLP DOI BibTeX RDF
42	Cristinel Ababei, Kia Bazargan	Timing Minimization by Statistical Timing hMetis-based Partitioning.	VLSI Design	2003	DBLP DOI BibTeX RDF
42	Farid N. Najm, Noel Menezes	Statistical timing analysis based on a timing yield model.	DAC	2004	DBLP DOI BibTeX RDF	statistical timing analysis, principal components, timing yield
41	Parimala Viswanath, Pranav Murthy, Debajit Das, R. Venkatraman, Ajoy Mandal, Arvind Veeravalli, H. Udayakumar	Optimization strategies to improve statistical timing.	ISQED	2009	DBLP DOI BibTeX RDF
41	Euiseok Hwang, Rohit Negi, B. V. K. Vijaya Kumar	Extended Kalman Filter Based Acquisition Timing Recovery for Magnetic Recording Read Channels.	ICC	2008	DBLP DOI BibTeX RDF
41	Chan-Gun Lee, Aloysius K. Mok, Prabhudev Konana	Monitoring of Timing Constraints with Confidence Threshold Requirements.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	fault tolerance, Constraints, monitors, temporal logic, real-time and embedded systems
41	Chee Sing Lee 0002, Wei Ting Loke, Wenjuan Zhang, Yajun Ha	Fast and Accurate Interval-Based Timing Estimator for Variability-Aware FPGA Physical Synthesis Tools.	FPL	2007	DBLP DOI BibTeX RDF
41	Chandramouli Visweswariah, K. Ravindran, Kerim Kalafala, Steven G. Walker, S. Narayan, Daniel K. Beece, Jeff Piaget, Natesan Venkateswaran, Jeffrey G. Hemmett	First-Order Incremental Block-Based Statistical Timing Analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
41	Aravind R. Nayak, John R. Barry, German S. Feyh, Steven W. McLaughlin	Timing Recovery With Frequency Offset and Random Walk: Cramer-Rao Bound and a Phase-Locked Loop Postprocessor.	IEEE Trans. Commun.	2006	DBLP DOI BibTeX RDF
41	Aravind R. Nayak, John R. Barry, German S. Feyh, Steven W. McLaughlin	Timing Recovery With Frequency Offset and Random Walk: Cramér-Rao Bound and a Phase- Locked Loop Postprocessor.	IEEE Trans. Commun.	2006	DBLP DOI BibTeX RDF
41	Chan-Gun Lee, Aloysius K. Mok, Prabhudev Konana	Monitoring of Timing Constraints with Confidence Threshold Requirements.	RTSS	2003	DBLP DOI BibTeX RDF
41	Sibin Mohan, Frank Mueller 0001	Hybrid Timing Analysis of Modern Processor Pipelines via Hardware/Software Interactions.	IEEE Real-Time and Embedded Technology and Applications Symposium	2008	DBLP DOI BibTeX RDF	hybrid timing anlalysis, hardware/software interactions, real-time systems, embedded systems, computer architecture, timing analysis, worst-case execution time, out-of-order execution
41	Sreeja Raj, Sarma B. K. Vrudhula, Janet Meiling Wang	A methodology to improve timing yield in the presence of process variations.	DAC	2004	DBLP DOI BibTeX RDF	timing analysis, gate sizing, timing yield
41	Peter A. Beerel, Ken S. Stevens, Hoshik Kim	Relative Timing Based Verification of Timed Circuits and Systems.	ASYNC	2002	DBLP DOI BibTeX RDF	Relative Timing, Verification and Timed Circuits, Timing Constraints
41	Martin Foltin, Brian Foutz, Sean Tyler	Efficient stimulus independent timing abstraction model based on a new concept of circuit block transparency.	DAC	2002	DBLP DOI BibTeX RDF	timing analysis, VLSI design, timing model, circuit optimization
41	Karim Khordoc, Eduard Cerny	Semantics and verification of action diagrams with linear timing.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	compatibility of interfaces, hardware interfaces, causality, timing verification, timing diagrams
41	Sung-Kwan Kim, Sang Lyul Min, Rhan Ha	Efficient worst case timing analysis of data caching.	IEEE Real Time Technology and Applications Symposium	1996	DBLP DOI BibTeX RDF	efficient worst case timing analysis, accurate timing analysis, pipelined execution, multiple memory locations, pointer based references, dynamic load/store instructions, WCET overestimation, global data flow analysis, benchmark programs, real-time systems, computational complexity, data caching, cache storage, instruction sets, reduced instruction set computing, data dependence analysis, cache block
41	Shuichi Oikawa, Hideyuki Tokuda	Efficient timing management for user-level real-time threads.	IEEE Real Time Technology and Applications Symposium	1995	DBLP DOI BibTeX RDF	efficient timing management, user-level real-time threads, specified time, upcalled user-level scheduler, user-level scheduler overhead, shared user-level timers, shared kernel/user structure, upcall performance, scheduling, performance evaluations, software engineering, real-time systems, resource allocation, timing, shared memory systems, kernel, processor scheduling, software performance evaluation, operating system kernels, hints, virtual processor
40	Serge Egelman, Janice Y. Tsai, Lorrie Faith Cranor, Alessandro Acquisti	Timing is everything?: the effects of timing and placement of online privacy indicators.	CHI	2009	DBLP DOI BibTeX RDF	website indicators, privacy, timing, mental models, privacy policies, usable privacy and security
40	Lei Ju 0001, Bach Khoa Huynh, Abhik Roychoudhury, Samarjit Chakraborty	Timing analysis of esterel programs on general-purpose multiprocessors.	DAC	2010	DBLP DOI BibTeX RDF	multiprocessor, timing analysis, synchronous language, esterel
40	Wilsaan M. Joiner, Mark Shelhamer	A model of time estimation and error feedback in predictive timing behavior.	J. Comput. Neurosci.	2009	DBLP DOI BibTeX RDF	Error feedback, Prediction, Timing, Saccade
40	Steven Gianvecchio, Haining Wang, Duminda Wijesekera, Sushil Jajodia	Model-Based Covert Timing Channels: Automated Modeling and Evasion.	RAID	2008	DBLP DOI BibTeX RDF	traffic modeling, evasion, covert timing channels
40	Khaled R. Heloue, Farid N. Najm	Parameterized timing analysis with general delay models and arbitrary variation sources.	DAC	2008	DBLP DOI BibTeX RDF	nonlinear delay, parameterized timing analysis, variability
40	Stephan Thesing	Modeling a system controller for timing analysis.	EMSOFT	2006	DBLP DOI BibTeX RDF	aiT, verification, static analysis, VHDL, timing analysis, WCET, worst-case execution time, avionics, peripherals
40	Alan Wassyng, Mark Lawford, Xiayong Hu	Timing Tolerances in Safety-Critical Software.	FM	2005	DBLP DOI BibTeX RDF	timing tolerances, real-time, requirements, safety-critical
40	Alejandro Hevia, Marcos A. Kiwi	Strength of two data encryption standard implementations under timing attacks.	ACM Trans. Inf. Syst. Secur.	1999	DBLP DOI BibTeX RDF	cryptography, cryptanalysis, data encryption standard, timing attack
40	Savithri Sundareswaran, David T. Blaauw, Abhijit Dharchoudhury	A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing Analysis.	VLSI Design	1999	DBLP DOI BibTeX RDF	spice verification, primary-path, secondary-path, timing analysis, assertion, assertibility
40	S. Balajee, Ananta K. Majhi	Automated AC (Timing) Characterization for Digital Circuit Testing.	VLSI Design	1998	DBLP DOI BibTeX RDF	Timing Characterization, STIL, Setup and Hold Time
40	Supratik Chakraborty, David L. Dill, Kun-Yung Chang, Kenneth Y. Yun	Timing Analysis of Extended Burst-Mode Circuits.	ASYNC	1997	DBLP DOI BibTeX RDF	Extended burst-mode circuits, 3D design style, global timing constraints, uncertain component delays, thirteen-valued signal algebra, polynomial-time
39	Zhuo Li 0001, David A. Papa, Charles J. Alpert, Shiyan Hu, Weiping Shi, Cliff C. N. Sze, Nancy Ying Zhou	Ultra-fast interconnect driven cell cloning for minimizing critical path delay.	ISPD	2010	DBLP DOI BibTeX RDF	gate duplication, physical synthesis, timing-driven placement
39	Ratnakar Goyal, Harindranath Parameswaran, Sachin Shrivastava	Computation of Waveform Sensitivity Using Geometric Transforms for SSTA.	ISQED	2008	DBLP DOI BibTeX RDF	Timing Library, Accuracy, SSTA
39	Salim Chowdhury, John Lillis	Repeater insertion for concurrent setup and hold time violations with power-delay trade-off.	ISPD	2007	DBLP DOI BibTeX RDF	early-mode timing, hold violation, late-mode timing, setup violation, timing optimization, repeater insertion
39	Aloysius K. Mok, Duu-Chung Tsou, Ruud C. M. de Rooij	The MSP.RTL real-time scheduler synthesis tool.	RTSS	1996	DBLP DOI BibTeX RDF	MSP RTL real time scheduler synthesis tool, scheduler synthesis algorithm, real time scheduling problem, temporal constraint satisfaction problem, temporal constraint graph, input timing specification, incremental positive cycle detection algorithm, real time scheduling theory, Boeing 777 Integrated Airplane Information Management System, AIMS, constraint satisfaction, processor scheduling, timing constraints, resource constraints, application domains, search strategies, cyclic schedules, feasible schedule, timing semantics, real time logic
39	Tapan J. Chakraborty, Vishwani D. Agrawal	Simulation of at-speed tests for stuck-at faults.	VTS	1995	DBLP DOI BibTeX RDF	stuck-at fault detectability, at-speed test simulation, delayed signal transitions, timing hazards, fault simulation method, delay-hazard robust test coverage, timing considerations, high performance circuits, fault diagnosis, logic testing, delays, timing, integrated circuit testing, circuit analysis computing, hazards and race conditions, path delays, high speed test
39	Hai Zhou 0001	Clock schedule verification with crosstalk.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	verification, delay, coupling, clock schedule
39	Farhana Sheikh, Andreas Kuehlmann, Kurt Keutzer	Minimum-power retiming for dual-supply CMOS circuits.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	dual-supply, retiming theory, low-power, synthesis, low-power design
39	Kanak Agarwal, Dennis Sylvester, David T. Blaauw	A library compatible driving point model for on-chip RLC interconnects.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF
39	Baris Taskin, Ivan S. Kourtev	Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skew.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	optimization, linear programming, clock skew, cycle stealing
38	Bing Li 0005, Christoph Knoth, Walter Schneider 0001, Manuel Schmidt, Ulf Schlichtmann	Static Timing Model Extraction for Combinational Circuits.	PATMOS	2008	DBLP DOI BibTeX RDF
38	Lizheng Zhang, Weijen Chen, Yuhen Hu, John A. Gubner, Charlie Chung-Ping Chen	Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model.	DAC	2005	DBLP DOI BibTeX RDF
38	David E. Wallace, Carlo H. Séquin	Plug-in timing models for an abstract timing verifier.	DAC	1986	DBLP DOI BibTeX RDF
38	Liangjun Shao, Peng Song, Yufan Yan, Xintao Zhang, Mianjun Xiao, Fang Liu, Huajun Liu, Timing Qu	Numerical Analysis of Screening-Current Induced Strain in a 16 T REBCO Insert Within a 20 T Background Field.	IEEE Access	2023	DBLP DOI BibTeX RDF
38	Yimin Dou, Kewen Li, Hongjie Duan, Timing Li, Lin Dong, Zongchao Huang	MDA GAN: Adversarial-Learning-Based 3-D Seismic Data Interpolation and Reconstruction for Complex Missing.	IEEE Trans. Geosci. Remote. Sens.	2023	DBLP DOI BibTeX RDF
38	Zhihao Liu, Yuanyuan Shang, Timing Li, Guanlin Chen, Yu Wang 0106, Qinghua Hu, Pengfei Zhu 0001	Robust Multi-Drone Multi-Target Tracking to Resolve Target Occlusion: A Benchmark.	IEEE Trans. Multim.	2023	DBLP DOI BibTeX RDF
38	Yimin Dou, Timing Li, Kewen Li, Hongjie Duan, Zhifeng Xu	ContrasInver: Voxel-wise Contrastive Semi-supervised Learning for Seismic Inversion.	CoRR	2023	DBLP DOI BibTeX RDF
38	Yimin Dou, Kewen Li, Jianbing Zhu, Timing Li, Shaoquan Tan, Zongchao Huang	MD Loss: Efficient Training of 3-D Seismic Fault Segmentation Network Under Sparse Labels by Weakening Anomaly Annotation.	IEEE Trans. Geosci. Remote. Sens.	2022	DBLP DOI BibTeX RDF
38	Yimin Dou, Kewen Li, Hongjie Duan, Timing Li, Lin Dong, Zongchao Huang	MDA GAN: Adversarial-Learning-based 3-D Seismic Data Interpolation and Reconstruction for Complex Missing.	CoRR	2022	DBLP DOI BibTeX RDF