Search results for "coprocessors"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
79	Vijay K. Jain, L. Lin	High-speed double precision computation of nonlinear functions.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	high-speed double precision computation, interpolative approach, third degree polynomial, image processing, interpolation, interpolation, scientific computing, digital arithmetic, multiplications, coprocessors, coprocessors, real-time image processing, nonlinear functions, silicon area
69	Domingo Benitez	A Quantitative Understanding of the Performance of Reconfigurable Coprocessors.	FPL	2002	DBLP DOI BibTeX RDF
67	Bradly K. Fawcett, J. Watson	Reconfigurable Processing With Field Programmable Gate Arrays.	ASAP	1996	DBLP DOI BibTeX RDF	reconfigurable processing, internal architecture, computationally-intensive tasks, programmable solution, XC6200 FPGA architecture, SRAM control store, on-chip memory capability, field programmable gate arrays, interconnections, reconfigurable architectures, processors, coprocessors, coprocessors, SRAM chips, SRAM-based field programmable gate arrays
66	Chen Huang 0005, Frank Vahid	Transmuting coprocessors: dynamic loading of FPGA coprocessors.	DAC	2009	DBLP DOI BibTeX RDF	coprocessing, FPGAs, online algorithms, dynamic optimization, acceleration, runtime configuration
60	Fei Sun, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor Generation for Extensible Processors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
57	Miljan Vuletic, Laura Pozzi, Paolo Ienne	Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors.	FPL	2004	DBLP DOI BibTeX RDF
48	Chen Huang 0005, Frank Vahid	Server-side coprocessor updating for mobile devices with FPGAs.	FPGA	2010	DBLP DOI BibTeX RDF	coprocessing, fpgas, dynamic optimization, acceleration
48	David W. Kravitz, Kim-Ee Yeoh, Nicol So	Secure Open Systems for Protecting Privacy and Digital Services.	Digital Rights Management Workshop	2001	DBLP DOI BibTeX RDF
46	Klaus E. Schauser, Chris J. Scheiman, J. Mitchell Ferguson, Paul Z. Kolano	Exploiting the Capabilities of Communications Co-Processors.	IPPS	1996	DBLP DOI BibTeX RDF	inter-computer links, communications coprocessor architecture, dedicated hardware support, user-level message handlers, Split-C, message handling code, Meiko CS-2 platform, synchronization, parallel architectures, local area networks, synchronisation, flexibility, coprocessors, computational power, massively parallel processors, workstation networks, active messages, electronic messaging
45	Bishwaranjan Bhattacharjee, Naoki Abe, Kenneth A. Goldman, Bianca Zadrozny, Vamsavardhana R. Chillakuru, Marysabel del Carpio, Chidanand Apté	Using secure coprocessors for privacy preserving collaborative data mining and analysis.	DaMoN	2006	DBLP DOI BibTeX RDF	data mining, privacy, collaboration, federation
45	Miljan Vuletic, Ludovic Righetti, Laura Pozzi, Paolo Ienne	Operating System Support for Interface Virtualisation of Reconfigurable Coprocessors.	DATE	2004	DBLP DOI BibTeX RDF
45	Domingo Benitez	Performance of Remote FPGA-Based Coprocessors for Image-Processing Applications.	DSD	2002	DBLP DOI BibTeX RDF
42	Sean W. Smith	Outbound authentication for programmable secure coprocessors.	Int. J. Inf. Sec.	2004	DBLP DOI BibTeX RDF	Secure coprocessors, Authentication, Trust, Attestation
42	Miljan Vuletic, Laura Pozzi, Paolo Ienne	Virtual memory window for application-specific reconfigurable coprocessors.	DAC	2004	DBLP DOI BibTeX RDF	reconfigurable computing, codesign, coprocessors, OS
42	Naren Narasimhan, Vinoo Srinivasan, Madhavi Vootukuru, Jeffrey Walrath, Sriram Govindarajan, Ranga Vemuri	Rapid Prototyping of Reconfigurable Coprocessors.	ASAP	1996	DBLP DOI BibTeX RDF	Prototyping, High-level Synthesis, JPEG, Coprocessors, Hardware-Software Co-design, Software Profiling
36	Yi-Neng Lin, Ying-Dar Lin, Kuo-Kun Tseng, Yuan-Cheng Lai	Modeling and analysis of core-centric network processors.	ACM Trans. Embed. Comput. Syst.	2009	DBLP DOI BibTeX RDF	core-centric, simulation, modeling, embedded system, Network processor
36	Yi-Neng Lin, Ying-Dar Lin, Yuan-Cheng Lai, Kuo-Kun Tseng	Modeling and analysis of core-centric network processors.	ACM Trans. Embed. Comput. Syst.	2008	DBLP DOI BibTeX RDF	core-centric, simulation, modeling, embedded system, Network processor
36	Lance Saldanha, Roman L. Lysecky	Hardware/software partitioning of floating point software applications to fixed-pointed coprocessor circuits.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	floating point to fixed conversion, floating point, fixed point, hardware/software partitioning
36	Jason Cong, Karthik Gururaj, Guoling Han, Adam Kaplan, Mishali Naik, Glenn Reinman	MC-Sim: an efficient simulation tool for MPSoC designs.	ICCAD	2008	DBLP DOI BibTeX RDF
36	Pranav Vaidya, Jaehwan John Lee	Simulation of hybrid computer architectures: simulators, methodologies and recommendations.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
36	Martijn J. Rutten, Jos T. J. van Eijndhoven, Evert-Jan D. Pol	Design of multi-tasking coprocessor control for Eclipse.	CODES	2002	DBLP DOI BibTeX RDF
33	Frédéric Amiel, Benoit Feix, Karine Villegas	Power Analysis for Secret Recovering and Reverse Engineering of Public Key Algorithms.	Selected Areas in Cryptography	2007	DBLP DOI BibTeX RDF	arithmetic coprocessors, reverse engineering, Public key cryptography, side-channel analysis, exponentiation
33	Richard S. Wallace, Michael D. Howard	HBA Vision Architecture: Built and Benchmarked.	IEEE Trans. Pattern Anal. Mach. Intell.	1989	DBLP DOI BibTeX RDF	vision architecture, hierarchical bus architecture, algorithmic benchmarks, local neighborhood operations, Apply, image-to-image transformations, floating-point coprocessors, computer vision, computer vision, parallel processing, parallel architectures, software tools, programming environment, programming environments, computerised picture processing, programming model, looping, boundary conditions
33	Xu Guo 0001, Zhimin Chen 0002, Patrick Schaumont	Energy and Performance Evaluation of an FPGA-Based SoC Platform with AES and PRESENT Coprocessors.	SAMOS	2008	DBLP DOI BibTeX RDF
33	Jin Ho Ha, Jin Soo Kim, Myung Hoon Sunwoo	AN ASIP Approach for H.264/AVC Implementation Having Novel Coprocessors.	SiPS	2007	DBLP DOI BibTeX RDF
33	Miljan Vuletic, Laura Pozzi, Paolo Ienne	Virtual memory window for application-specific reconfigurable coprocessors.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
33	Patrick Schaumont, Doris Ching, Ingrid Verbauwhede	An interactive codesign environment for domain-specific coprocessors.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	hardware description language, hardware-software codesign, Cosimulation
33	Carsten Albrecht, Andreas C. Döring, Frank Penczek, Torben Schneider, Hannes Schulz	Impact of Coprocessors on a Multithreaded Processor Design Using Prioritized Threads.	PDP	2006	DBLP DOI BibTeX RDF
33	Björn Griese, Boris Kettelhoit, Mario Porrmann	Evaluation of On-Chip Interfaces for Dynamically Reconfigurable Coprocessors.	PARELEC	2006	DBLP DOI BibTeX RDF
33	Thomas J. Wollinger, Guido Bertoni, Luca Breveglieri, Christof Paar	Performance of HECC Coprocessors Using Inversion-Free Formulae.	ICCSA (3)	2006	DBLP DOI BibTeX RDF
33	Haidong Xia, Jayashree Kanchana, José Carlos Brustoloni	Using Secure Coprocessors to Protect Access to Enterprise Networks.	NETWORKING	2005	DBLP DOI BibTeX RDF
33	MinYong Jeon, Hyunil Byun, JooHo Ha, KiTaek Lee, JooHyoung Kim, JiYoung Seo, KyungWoo Lee, SeungHo Lee	A system-on-chip featuring variable bus architecture and enhanced video coprocessors for MPEG-4 multimedia applications.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
33	Martijn J. Rutten, Jos T. J. van Eijndhoven, Evert-Jan D. Pol	Robust Media Processing in a Flexible and Cost-Effective Network of Multi-Tasking Coprocessors.	ECRTS	2002	DBLP DOI BibTeX RDF
33	Stephen Charlwood, Jonathan Mangnall, Steven F. Quigley	System-Level Modelling for Performance Estimation of Reconfigurable Coprocessors.	FPL	2002	DBLP DOI BibTeX RDF
33	Juan Carlos López 0001, Fernando Rincón, Francisco Moya, José Manuel Moya	Improving Embedded System Design by Means of HW-SW Compilation on Reconfigurable Coprocessors.	ISSS	2002	DBLP DOI BibTeX RDF	reconfigurable datapaths, hardware-software codesign
33	Takashi Miyamori, Kunle Olukotun	A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications.	FCCM	1998	DBLP DOI BibTeX RDF
33	Martin C. Herbordt, Owais Kidwai, Charles C. Weems	Preprototyping SIMD Coprocessors Using Virtual Machine Emulation and Trace Compilation.	SIGMETRICS	1997	DBLP DOI BibTeX RDF
24	John H. Kelm, Isaac Gelado, Mark J. Murphy, Nacho Navarro, Steven S. Lumetta, Wen-mei W. Hwu	CIGAR: Application Partitioning for a CPU/Coprocessor Architecture.	PACT	2007	DBLP DOI BibTeX RDF
24	Christopher Claus, Johannes Zeppenfeld, Florian Helmut Müller, Walter Stechele	Using partial-run-time reconfigurable hardware to accelerate video processing in driver assistance system.	DATE	2007	DBLP DOI BibTeX RDF
24	Giovanni Agosta, Luca Breveglieri, Gerardo Pelosi, Martino Sykora	Programming Highly Parallel Reconfigurable Architectures for Public-Key Cryptographic Applications.	ITNG	2007	DBLP DOI BibTeX RDF
24	Henrik Svensson, Thomas Lenart, Viktor Öwall	Accelerating Vector Operations by Utilizing Reconfigurable Coprocessor Architectures.	ISCAS	2007	DBLP DOI BibTeX RDF
24	Dong-Ho Lee, Jong-Soo Oh	Multi-segment GF(2m) multiplication and its application to elliptic curve cryptography.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	elliptic curve scalar multiplication, FPGA, elliptic curve cryptography (ECC), coprocessor, finite field multiplication
24	David Sheldon, Rakesh Kumar 0002, Frank Vahid, Dean M. Tullsen, Roman L. Lysecky	Conjoining soft-core FPGA processors.	ICCAD	2006	DBLP DOI BibTeX RDF	conjoined processors, parameterized platforms, soft-core processors, FPGAs, customization, tuning
24	Ivan Augé, Frédéric Pétrot, François Donnet, Pascal Gomez	Platform-based design from parallel C specifications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
24	Seng Lin Shee, Sri Parameswaran, Newton Cheung	Novel architecture for loop acceleration: a case study.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	tightly coupled, architecture, ASIP, hardware/software partitioning, coprocessor, loop optimization, latency hiding, loop pipelining, loop acceleration
24	Martin Seysen	Using an RSA Accelerator for Modular Inversion.	CHES	2005	DBLP DOI BibTeX RDF	Smart card coprocessor, Euclidean algorithm, modular inversion
24	Howon Kim 0001, Mun-Kyu Lee, Dong Kyue Kim, Sang-Kyoon Chung, Kyoil Chung	Design and Implementation of Crypto Co-processor and Its Application to Security Systems.	CIS (2)	2005	DBLP DOI BibTeX RDF	Crypto Algorithm, Power Consumption, Crypto Coprocessor
24	Andrew Morton, Wayne M. Loucks	A hardware/software kernel for system on chip designs.	SAC	2004	DBLP DOI BibTeX RDF	operating systems, SoC, hardware/software codesign
24	Leandro Möller, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Eduardo Wenzel Brião, Ewerson Carvalho, Daniel Camozzato	FiPRe: An Implementation Model to Enable Self-Reconfigurable Applications.	FPL	2004	DBLP DOI BibTeX RDF
24	Miljan Vuletic, Laura Pozzi, Paolo Ienne	Virtual Memory Window for a Portable Reconfigurable Cryptography Coprocessor.	FCCM	2004	DBLP DOI BibTeX RDF
24	Newton Cheung, Jörg Henkel, Sri Parameswaran	Rapid Configuration and Instruction Selection for an ASIP: A Case Study.	DATE	2003	DBLP DOI BibTeX RDF
24	Matthias Dyer, Christian Plessl, Marco Platzner	Partially Reconfigurable Cores for Xilinx Virtex.	FPL	2002	DBLP DOI BibTeX RDF
24	Anatoly E. Voevudko	Steps Toward Next Generation Computer Based Systems.	ECBS	1999	DBLP DOI BibTeX RDF	Processor based architecture, unified linguistic and access support, scripting and programming languages, distributed systems, integration, operating systems, software, hardware, portability, Web-based systems
24	Rolf Ernst, Kees A. Vissers, Pieter van der Wolf, Gert-Jan van Rootselaar	System level design and debug of high-performance embedded media systems (tutorial).	ICCAD	1999	DBLP BibTeX RDF
24	Timothy J. Callahan, John Wawrzynek	Instruction-Level Parallelism for Reconfigurable Computing.	FPL	1998	DBLP DOI BibTeX RDF
24	Peter Steenkiste	Analyzing Communication Latency Using the Nectar Communication Processor.	SIGCOMM	1992	DBLP DOI BibTeX RDF	SPARC
21	Tony M. Brewer	Instruction Set Innovations for the Convey HC-1 Computer.	IEEE Micro	2010	DBLP DOI BibTeX RDF	hybrid-core computing, FPGAs, reconfigurable computing, heterogeneous computing, accelerators, coprocessors, instruction set design
21	Liang Ma, Caijun Zhen, Bin Zhao, Jingwei Ma, Gang Wang 0001, Xiaoguang Liu 0001	Towards Fast De-duplication Using Low Energy Coprocessor.	NAS	2010	DBLP DOI BibTeX RDF	De-duplication, Commodity coprocessors, Computing complexity, Low energy
21	Atabak Mahram, Martin C. Herbordt	Fast and accurate NCBI BLASTP: acceleration with multiphase FPGA-based prefiltering.	ICS	2010	DBLP DOI BibTeX RDF	FPGA-based coprocessors, high performance reconfigurable computing, bioinformatics, biological sequence alignment
21	Paul E. Marks, Cameron D. Patterson	Data streaming and simd support for the microblaze architecture.	FPGA	2009	DBLP DOI BibTeX RDF	streaming coprocessors, vector units, reconfigurability
21	Masayuki Yoshino, Katsuyuki Okeya, Camille Vuillaume	Recursive Double-Size Modular Multiplications without Extra Cost for Their Quotients.	CT-RSA	2009	DBLP DOI BibTeX RDF	low-end device, double-size technique, RSA, modular multiplication, efficient implementation, crypto-coprocessors, arithmetic unit
21	Partha Biswas, Nikil D. Dutt	Code Size Reduction in Heterogeneous-Connectivity-Based DSPs Using Instruction Set Extensions.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	DSP, VLIW, ASIP, Coprocessors, instruction set extensions, code size reduction
21	Partha Biswas, Vinay Choudhary, Kubilay Atasu, Laura Pozzi, Paolo Ienne, Nikil D. Dutt	Introduction of local memory elements in instruction set extensions.	DAC	2004	DBLP DOI BibTeX RDF	ad-hoc functional units, genetic algorithm, ASIPs, coprocessors, instruction set extensions, customizable processors
21	S. Ramanathan, S. K. Nandy 0001, V. Visvanathan	Reconfigurable Filter Coprocessor Architecture for DSP Applications.	J. VLSI Signal Process.	2000	DBLP DOI BibTeX RDF	reconfigurable coprocessors, filter coprocessor architecture, systolic architectures and digital signal processing, pipelined architectures, low-power architectures
21	Nalini K. Ratha, Anil K. Jain 0001, Diane T. Rover	FPGA-Based Coprocessor for Text String Extraction.	CAMP	2000	DBLP DOI BibTeX RDF	FPGA-based coprocessor, text string extraction, image morphology based algorithms, high-performance coprocessor, Splash 2, Sun hosts, VHDL behavioral modeling, SPARC station 20, design patterns, coprocessors, document understanding, visual effects
21	Chi-Min Lin, Tien-Fu Chen	Dynamic memory management for real-time embedded Java chips.	RTCSA	2000	DBLP DOI BibTeX RDF	storage management chips, dynamic runtime memory management, real-time embedded Java chips, CPU design, hardware-assisted scheme, dynamic garbage collection mechanism, predictable memory allocation time, data transition events, circular heap, simulation, Java, embedded systems, response time, memory architecture, memory architecture, storage allocation, coprocessors, resource constraints, real-time constraints, co-processor
21	Jean-Luis Dufour	Safety computations in integrated circuits.	VTS	1996	DBLP DOI BibTeX RDF	safety computations, software-based railway control systems, MATRA TRANSPORT, signature checking, coded processor, reliability, fault tolerant computing, logic testing, redundancy, integrated circuit testing, error correction codes, automatic testing, application specific integrated circuits, ASICs, integrated circuits, coprocessors, arithmetic coding, integrated circuit reliability
21	Michael S. Allen, W. Kurt Lewchuk, J. D. Coddington	A high performance bus and cache controller for PowerPC multiprocessing systems.	ICCD	1995	DBLP DOI BibTeX RDF	high performance bus, cache controller, PowerPC 620 microprocessor, system bus interface, ECC protected, server-class systems, physical address bus, data bus, address transfer rates, address snoop response, direct cache-to-cache data transfers, 2 GByte/s, 133 MHz, 128 MB, performance evaluation, pipelining, multiprocessing systems, multiprocessing systems, pipeline processing, cache storage, microprocessor chips, coprocessors, cache coherency protocol, data transfer, PowerPC, system buses, co-processor
21	Michael J. Schulte, Earl E. Swartzlander Jr.	A coprocessor for accurate and reliable numerical computations.	ICCD	1995	DBLP DOI BibTeX RDF	reliable numerical computations, direct hardware support, logic design, digital arithmetic, interval arithmetic, hardware design, coprocessors, coprocessor, numerical computations
21	Ali Skaf, Alain Guyot	SAGA: the first general-purpose on-line arithmetic co-processor.	VLSI Design	1995	DBLP DOI BibTeX RDF	general-purpose co-processor, online arithmetic coprocessor, VLSI realisation, BKM algorithm, complex logarithm function, complex exponential function, VLSI, arithmetic, coprocessors, CMOS digital integrated circuits, redundant number systems, CMOS IC, SAGA
21	Leonardo Campanale, Mario De Blasi, Anna Gentile, F. Greco	Topologies for the parallel backtracking Prolog engine.	MICRO	1990	DBLP BibTeX RDF	Prolog machines, backup or-parallelism, distributed systems, topologies, coprocessors, transputers, Occam, multicomputer networks
21	CMS Collaboration	Portable acceleration of CMS computing workflows with coprocessors as a service.	CoRR	2024	DBLP DOI BibTeX RDF
21	Dhiman Chakraborty 0001, Michael Schwarz 0001, Sven Bugiel	TALUS: Reinforcing TEE Confidentiality with Cryptographic Coprocessors (Technical Report).	CoRR	2023	DBLP DOI BibTeX RDF
21	Dhiman Chakraborty 0001, Michael Schwarz 0001, Sven Bugiel	TALUS: Reinforcing TEE Confidentiality with Cryptographic Coprocessors.	FC (1)	2023	DBLP DOI BibTeX RDF
21	Balazs Udvarhelyi, François-Xavier Standaert	Leveraging Coprocessors as Noise Engines in Off-the-Shelf Microcontrollers.	CARDIS	2023	DBLP DOI BibTeX RDF
21	Jong-Yeon Park, Yong-Hyuk Moon, Won-Il Lee, Sung-Hyun Kim, Kouichi Sakurai	A Survey of Polynomial Multiplication With RSA-ECC Coprocessors and Implementations of NIST PQC Round3 KEM Algorithms in Exynos2100.	IEEE Access	2022	DBLP DOI BibTeX RDF
21	Ferruccio Damiani, Luca Paolini, Luca Roversi	Programming the Interaction with Quantum Coprocessors.	ERCIM News	2022	DBLP BibTeX RDF
21	Jorge Reis, Jarbas Silveira, César A. M. Marcon	Impact of failures in a MPSoC with shared coprocessors to extend the RISC-V ISA.	LADC	2022	DBLP DOI BibTeX RDF
21	Yaroslav Nykolaychuk, Volodymyr Hryha, Natalia Vozna, Artur Voronych, Andriy Segin, Petro Humennyi	High-performance Coprocessors for Arithmetic and Logic Operations of Multi-Bit Cores for Vector and Scalar Supercomputers.	ACIT	2022	DBLP DOI BibTeX RDF
21	Tim Fritzmann	Towards Secure Coprocessors and Instruction Set Extensions for Acceleration of Post-Quantum Cryptography.		2022	RDF
21	Abdallah Cheikh, Stefano Sordillo, Antonio Mastrandrea, Francesco Menichelli, Giuseppe Scotti, Mauro Olivieri	Klessydra-T: Designing Vector Coprocessors for Multithreaded Edge-Computing Cores.	IEEE Micro	2021	DBLP DOI BibTeX RDF
21	Anirban Sengupta, Rahul Chaurasia, Tarun Reddy	Contact-Less Palmprint Biometric for Securing DSP Coprocessors Used in CE Systems.	IEEE Trans. Consumer Electron.	2021	DBLP DOI BibTeX RDF
21	Olivier Bronchain, Charles Momin, Thomas Peters, François-Xavier Standaert	Improved Leakage-Resistant Authenticated Encryption based on Hardware AES Coprocessors.	IACR Trans. Cryptogr. Hardw. Embed. Syst.	2021	DBLP DOI BibTeX RDF
21	Jeffrey D. Krupa, Kelvin Lin, Maria Acosta Flechas, Jack Dinsmore, Javier M. Duarte, Philip C. Harris, Scott Hauck, Burt Holzman, Shih-Chieh Hsu, Thomas Klijnsma, Mia Liu, Kevin Pedro, Dylan S. Rankin, Natchanon Suaysom, Matt Trahms, Nhan Tran	GPU coprocessors as a service for deep learning inference in high energy physics.	Mach. Learn. Sci. Technol.	2021	DBLP DOI BibTeX RDF
21	Alexander Antonov	Inferring Custom Synthesizable Kernel for Generation of Coprocessors with Out-of-Order Execution.	MECO	2021	DBLP DOI BibTeX RDF
21	Jeffrey D. Krupa, Kelvin Lin, Maria Acosta Flechas, Jack Dinsmore, Javier M. Duarte, Philip C. Harris, Scott Hauck, Burt Holzman, Shih-Chieh Hsu, Thomas Klijnsma, Mia Liu, Kevin Pedro, Natchanon Suaysom, Matt Trahms, Nhan Tran	GPU coprocessors as a service for deep learning inference in high energy physics.	CoRR	2020	DBLP BibTeX RDF
21	Abdallah Cheikh, Stefano Sordillo, Antonio Mastrandrea, Francesco Menichelli, Giuseppe Scotti, Mauro Olivieri	Klessydra-T: Designing Vector Coprocessors for Multi-Threaded Edge-Computing Cores.	CoRR	2020	DBLP BibTeX RDF
21	Sebastian Baunsgaard, Sebastian Benjamin Wrede, Pinar Tözün	Training for Speech Recognition on Coprocessors.	CoRR	2020	DBLP BibTeX RDF
21	Nouredine Melab, Jan Gmys, Mohand Mezmaz, Daniel Tuyttens	Many-Core Branch-and-Bound for GPU Accelerators and MIC Coprocessors.	High-Performance Simulation-Based Optimization	2020	DBLP DOI BibTeX RDF
21	Sebastian Baunsgaard, Sebastian Benjamin Wrede, Pinar Tözün	Training for Speech Recognition on Coprocessors.	ADMS@VLDB	2020	DBLP BibTeX RDF
21	Bryan Pearson, Cliff C. Zou, Yue Zhang 0025, Zhen Ling, Xinwen Fu	SIC2: Securing Microcontroller Based IoT Devices with Low-cost Crypto Coprocessors.	ICPADS	2020	DBLP DOI BibTeX RDF
21	Pedro Lima, Caio Vieira, Jorge Reis, Alexandre Almeida, Jarbas Silveira, Roger C. Goerl, César A. M. Marcon	Optimizing RISC-V ISA Usage by Sharing Coprocessors on MPSoC.	LATS	2020	DBLP DOI BibTeX RDF
21	Valerii Hlukhov	Comparison of Homogeneous and Heterogeneous Digital Quantum Coprocessors.	CSIT (2)	2020	DBLP DOI BibTeX RDF
21	Putt Sakdhnagool, Amit Sabne, Rudolf Eigenmann	Comparative analysis of coprocessors.	Concurr. Comput. Pract. Exp.	2019	DBLP DOI BibTeX RDF
21	J. L. Campon, Luis Landesa	Fast solution of electromagnetic scattering problems using Xeon Phi coprocessors.	J. Supercomput.	2019	DBLP DOI BibTeX RDF
21	Niels Pirotte, Jo Vliegen, Lejla Batina, Nele Mentens	Balancing elliptic curve coprocessors from bottom to top.	Microprocess. Microsystems	2019	DBLP DOI BibTeX RDF
21	Daniel Etiemble	Coprocessors: failures and successes.	CoRR	2019	DBLP BibTeX RDF
21	Wenpeng Ma, Wu Yuan 0002, Xiaodong Hu	Implementation and Optimization of a CFD Solver Using Overlapped Meshes on Multiple MIC Coprocessors.	Sci. Program.	2019	DBLP DOI BibTeX RDF
21	Jason Staggs, Sujeet Shenoi	Securing Wireless Coprocessors from Attacks in the Internet of Things.	Critical Infrastructure Protection	2019	DBLP DOI BibTeX RDF
21	Christopher P. Stone, Andrew T. Alferman, Kyle E. Niemeyer	Accelerating finite-rate chemical kinetics with coprocessors: Comparing vectorization methods on GPUs, MICs, and CPUs.	Comput. Phys. Commun.	2018	DBLP DOI BibTeX RDF