Search results for "cores"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
80	Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante	A genetic algorithm-based system for generating test programs for microprocessor IP cores.	ICTAI	2000	DBLP DOI BibTeX RDF	industrial property, genetic algorithm based system, test program generation, microprocessor IP cores, digital systems design trend, design-and-reuse paradigm, intellectual property cores, encrypted gate-level netlist, testability problems, automatic approach, processor cores, fault coverage figures, random approach, genetic algorithms, genetic algorithms, microprocessor chips, automatic test software, test program, electronic engineering computing
68	Pierre Salverda, Craig B. Zilles	Fundamental performance constraints in horizontal fusion of in-order cores.	HPCA	2008	DBLP DOI BibTeX RDF
68	Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty	IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores.	ITC	2004	DBLP DOI BibTeX RDF
63	Sandeep Kumar Goel, Erik Jan Marinissen, Anuja Sehgal, Krishnendu Chakrabarty	Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
62	Jaime H. Moreno	Chip-level integration: the new frontier for microprocessor architecture.	SPAA	2006	DBLP DOI BibTeX RDF	chip-level integration, microprocessor architecture
57	Srinivasan Murali, Giovanni De Micheli	Bandwidth-Constrained Mapping of Cores onto NoC Architectures.	DATE	2004	DBLP DOI BibTeX RDF	routing, Systems on Chips, mapping, Networks on Chips, bandwidth, cores
57	Noha Kafafi, Kimberly A. Bozman, Steven J. E. Wilton	Architectures and algorithms for synthesizable embedded programmable logic cores.	FPGA	2003	DBLP DOI BibTeX RDF	programmable logic cores, FPGA, standard cells, system-on-chip design
57	Peter Hallschmid, Steven J. E. Wilton	Detailed routing architectures for embedded programmable logic IP cores.	FPGA	2001	DBLP DOI BibTeX RDF	FPGA, programmable logic, detailed routing, SoC design, embedded cores
57	Ganesh Venkatesh, Jack Sampson, Nathan Goulding, Saturnino Garcia, Vladyslav Bryksin, Jose Lugo-Martinez, Steven Swanson, Michael Bedford Taylor	Conservation cores: reducing the energy of mature computations.	ASPLOS	2010	DBLP DOI BibTeX RDF	conservation core, heterogeneous many-core, utilization wall, patching
56	Kuen-Jong Lee, Cheng-I Huang	A hierarchical test control architecture for core based design.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	hierarchical test control architecture, SOC design, IEEE P1500 Working Group, test standard, IEEE 1149.1 cores, parallel testing capabilities, hierarchical test control mechanism, deeply embedded cores, hierarchical test access, integrated circuit testing, design for testability, automatic testing, application specific integrated circuits, IEEE standards, test architecture, core based design
53	Avi Mendelson	Current trends in computer architectures: multi-cores, many-cores and special-cores.	ICS	2007	DBLP DOI BibTeX RDF
52	Nur A. Touba, Bahram Pouya	Testing Embedded Cores Using Partial Isolation Rings.	VTS	1997	DBLP DOI BibTeX RDF	Intellectual Property Cores, Isolation Rings, Boundary Scan, Hill Climbing, Partial Scan, Embedded Cores, Digital Testing
51	Vijay Janapa Reddi, Benjamin C. Lee, Trishul M. Chilimbi, Kushagra Vaid	Web search using mobile cores: quantifying and mitigating the price of efficiency.	ISCA	2010	DBLP DOI BibTeX RDF	bing, mobile cores, energy efficiency, web search
51	Daniel Ziener, Jürgen Teich	Power Signature Watermarking of IP Cores for FPGAs.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	IPP, FPGA, watermarking, signature, power analysis, IP cores
51	Ulya R. Karpuzcu, Brian Greskamp, Josep Torrellas	The BubbleWrap many-core: popping cores for sequential acceleration.	MICRO	2009	DBLP DOI BibTeX RDF	power wall, process scaling, processor aging, voltage scaling
51	Irith Pomeranz, Sudhakar M. Reddy, Yervant Zorian	A Test Interface for Built-In Test of Non-Isolated Scanned Cores.	VTS	2003	DBLP DOI BibTeX RDF
51	Juan Carlos Saez, Manuel Prieto 0001, Alexandra Fedorova, Sergey Blagodurov	A comprehensive scheduler for asymmetric multicore systems.	EuroSys	2010	DBLP DOI BibTeX RDF	asymmetric multicore, scheduling, operating systems
51	Vahid Kazempour, Ali Kamali, Alexandra Fedorova	AASH: an asymmetry-aware scheduler for hypervisors.	VEE	2010	DBLP DOI BibTeX RDF	heterogeneous, scheduling algorithms, multicore processors, virtual machine monitor, hypervisor, asymmetric
51	Enric Musoll	Trading off higher execution latency for increased reliability in tile-based massive multi-core architectures.	ISQED	2009	DBLP DOI BibTeX RDF
51	Xiongfei Liao, Wu Jigang, Thambipillai Srikanthan	A temperature-aware virtual submesh allocation scheme for noc-based manycore chips.	SPAA	2008	DBLP DOI BibTeX RDF	manycore chips, submesh allocation, algorithm, noc, temperature
51	Ondrej Novák, Zdenek Plíva, Jiri Jenícek, Zbynek Mader, Michal Jarkovský	Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead.	DFT	2006	DBLP DOI BibTeX RDF
51	Qiang Xu 0001, Nicola Nicolici	Modular SOC testing with reduced wrapper count.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
46	A. Schubert, Walter Anheier	On Random Pattern Testability of Cryptographic VLSI Cores.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	testing of cores, test-ready intellectual property, built-in self-test, pseudorandom testing
46	Tony Givargis, Frank Vahid, Jörg Henkel	Instruction-based System-level Power Evaluation of System-On-A-Chip Peripheral Cores.	ISSS	2000	DBLP DOI BibTeX RDF	silicon platforms, caches, low-power design, estimation, System-on-a-chip, intellectual property, cores, system parameters
46	Andy Yan, Steven J. E. Wilton	Product-Term-Based Synthesizable Embedded Programmable Logic Cores.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
46	John D. Davis, James Laudon, Kunle Olukotun	Maximizing CMP Throughput with Mediocre Cores.	IEEE PACT	2005	DBLP DOI BibTeX RDF
46	Alex K. Jones, Prithviraj Banerjee	An automated and power-aware framework for utilization of IP cores in hardware generated from C descriptions targeting FPGAs.	FPGA	2003	DBLP DOI BibTeX RDF
46	Lukás Sekanina	Towards Evolvable IP Cores for FPGAs.	Evolvable Hardware	2003	DBLP DOI BibTeX RDF
46	Chih-Wea Wang, Jing-Reng Huang, Yen-Fu Lin, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin	Test Scheduling of BISTed Memory Cores for SOC.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
46	Daniel Zappala, Aaron Fabbri	An Evaluation of Shared Multicast Trees with Multiple Active Cores.	ICN (1)	2001	DBLP DOI BibTeX RDF
45	Hans G. Kerkhoff, Jarkko J. M. Huijts	Testing of a Highly Reconfigurable Processor Core for Dependable Data Streaming Applications.	DELTA	2008	DBLP DOI BibTeX RDF	reconfigurable multi-processor-cores SoC, embedded system test, dependable SoCs, ATPG, Design-for-Test, self-repair
45	Henry Wong, Anne Bracy, Ethan Schuchman, Tor M. Aamodt, Jamison D. Collins, Perry H. Wang, Gautham N. Chinya, Ankur Khandelwal Groen, Hong Jiang, Hong Wang 0003	Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor.	PACT	2008	DBLP DOI BibTeX RDF	ia32, on-chip integration, chip multiprocessor, heterogeneous
40	Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian	Instruction-Based Self-Testing of Processor Cores.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	processor cores, built-in self-test, instruction set, at-speed testing, software-based self test
40	Tony Givargis, Frank Vahid, Jörg Henkel	Trace-driven system-level power evaluation of system-on-a-chip peripheral cores.	ASP-DAC	2001	DBLP DOI BibTeX RDF	low power system design, parameterized architectures, system-on-a-chip, intellectual property, cores, system-level modeling
40	Ilker Hamzaoglu, Janak H. Patel	Reducing Test Application Time for Full Scan Embedded Cores.	FTCS	1999	DBLP DOI BibTeX RDF	test generation, design-for-testability, fault simulation, embedded cores, full scan
40	Kaushik De	Test methodology for embedded cores which protects intellectual property.	VTS	1997	DBLP DOI BibTeX RDF	core I/Os, ASIC I/O inaccessibility, partial netlist generation, ASIC level test generation, gate testing, core scan chain, selective boundary scan, coreware design paradigm, logic testing, heuristic algorithm, structural analysis, intellectual property protection, embedded cores, test methodology
40	Wei Zhao, Christos A. Papachristou	Synthesis of reusable DSP cores based on multiple behaviors.	ICCAD	1996	DBLP DOI BibTeX RDF	RTL components, RTL structure, design process complexity, design time, multiple behaviors, reusable DSP cores synthesis, digital signal processing chips
40	Tameesh Suri, Aneesh Aggarwal	Improving Scalability and Per-Core Performance in Multi-Cores through Resource Sharing and Reconfiguration.	VLSI Design	2009	DBLP DOI BibTeX RDF
40	Ronald Scrofano, Ling Zhuo, Viktor K. Prasanna	Area-Efficient Arithmetic Expression Evaluation Using Deeply Pipelined Floating-Point Cores.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
40	David de Andrés, Juan-Carlos Ruiz-Garcia, Daniel Gil, Pedro J. Gil	Dependability Assessment for the Selection of Embedded Cores.	EDCC	2008	DBLP DOI BibTeX RDF
40	David Tarjan, Michael Boyer, Kevin Skadron	Federation: repurposing scalar cores for out-of-order instruction issue.	DAC	2008	DBLP DOI BibTeX RDF	CMP, multicore, federation, out-of-order
40	Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty	Test infrastructure design for mixed-signal SOCs with wrapped analog cores.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
40	Simin Dai, Elaheh Bozorgzadeh	CAD Tool for FPGAs with Embedded Hard Cores for Design Space Exploration of Future Architectures.	FCCM	2006	DBLP DOI BibTeX RDF
40	Mario Donato Marino	32-core CMP with multi-sliced L2: 2 and 4 cores sharing a L2 slice.	SBAC-PAD	2006	DBLP DOI BibTeX RDF
40	Anuja Sehgal, Fang Liu 0029, Sule Ozev, Krishnendu Chakrabarty	Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores.	DATE	2005	DBLP DOI BibTeX RDF
40	Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-Bin Kim, Vincenzo Piuri	Optimal Spare Utilization in Repairable and Reliable Memory Cores.	MTDT	2003	DBLP DOI BibTeX RDF	Embedded Memory Repair and Reliability, Fault-Tolerant Memory Core, System-on-chip, Yield, Built-In-Self-Repair
40	Magnus Ekman, Per Stenström	Performance and Power Impact of Issue-width in Chip-Multiprocessor Cores.	ICPP	2003	DBLP DOI BibTeX RDF
40	Anoop Iyer, Diana Marculescu	Power efficiency of voltage scaling in multiple clock, multiple voltage cores.	ICCAD	2002	DBLP DOI BibTeX RDF
40	Jing-Reng Huang, Madhu K. Iyer, Kwang-Ting Cheng	A Self-Test Methodology for IP Cores in Bus-Based Programmable SoCs.	VTS	2001	DBLP DOI BibTeX RDF
40	Philip James-Roxby, Steven A. Guccione	Automated Extraction of Run-Time Parameterizable Cores from Programmable Device Configurations.	FCCM	2000	DBLP DOI BibTeX RDF
39	Perry H. Wang, Jamison D. Collins, Gautham N. Chinya, Hong Jiang, Xinmin Tian, Milind Girkar, Nick Y. Yang, Guei-Yuan Lueh, Hong Wang 0003	EXOCHI: architecture and programming environment for a heterogeneous multi-core multithreaded system.	PLDI	2007	DBLP DOI BibTeX RDF	GPU, openMP, heterogeneous multi-cores
39	Pierre Michaud, Yiannakis Sazeides, André Seznec	Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cache misses.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	activity migration, sequential performance, power, multicore, temperature, cache misses, manycore
39	Mario Donato Marino	L2-Cache Hierarchical Organizations for Multi-core Architectures.	ISPA Workshops	2006	DBLP DOI BibTeX RDF
39	Theofanis Constantinou, Yiannakis Sazeides, Pierre Michaud, Damien Fetis, André Seznec	Performance implications of single thread migration on a chip multi-core.	SIGARCH Comput. Archit. News	2005	DBLP DOI BibTeX RDF
36	Francesco Menichelli, Mauro Olivieri, Simone Smorfa	Performance evaluation of Jpeg2000 implementation on VLIW cores, SIMD cores and multi-cores.	ISCAS	2011	DBLP DOI BibTeX RDF
35	Swann Perarnau, Guillaume Huard	KRASH: reproducible CPU load generation on many cores machines.	PPoPP	2010	DBLP DOI BibTeX RDF	cpu load generation, many cores, experimentation testbed
35	Roman L. Lysecky, Frank Vahid	Prefetching for improved bus wrapper performance in cores.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	Bus wrapper, PVCI, VSIA, interfacing, system-on-a-chip, intellectual property, cores, design reuse, on-chip bus
35	T. Vinod Kumar Gupta, Roberto E. Ko, Rajeev Barua	Compiler-directed customization of ASIP cores.	CODES	2002	DBLP DOI BibTeX RDF	soft cores, embedded, customization, ASIP
35	Yulu Ma, Shiduan Cheng	Multi-Cores Uni-Directional Shared Trees Multicast Routing Protocol.	LCN	2000	DBLP DOI BibTeX RDF	multi-cores uni-directional shared trees, CBT, PIM-SM, intradomain multicast routing protocols, efficient member management mechanism, authentication, protocols, admission control, trees (mathematics), telecommunication network routing, multicast communication, multicast group, packet transmission
35	Marinés Puig-Medina, Gülbin Ezer, Pavlos Konas	Verification of configurable processor cores.	DAC	2000	DBLP DOI BibTeX RDF	configurable processor cores, system-on-chip, test generation, design verification, co-simulation, coverage analysis
35	Omer Khan, Sandip Kundu	A self-adaptive scheduler for asymmetric multi-cores.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	scheduling, modeling, power
35	Tameesh Suri, Aneesh Aggarwal	Improving performance of simple cores by exploiting loop-level parallelism through value prediction and reconfiguration.	Conf. Computing Frontiers	2009	DBLP DOI BibTeX RDF	data value prediction, dynamic reconfiguration, loop level parallelism
35	Takanori Ueda, Yu Hirate, Hayato Yamana	Exploiting idle CPU cores to improve file access performance.	ICUIMC	2009	DBLP DOI BibTeX RDF	access pattern mining, many core, access pattern, replacement algorithm, buffer caching
35	Albert Meixner, Daniel J. Sorin	Detouring: Translating software to circumvent hard faults in simple cores.	DSN	2008	DBLP DOI BibTeX RDF
35	Qiang Xu 0001, Nicola Nicolici, Krishnendu Chakrabarty	Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
35	Andreas Apostolakis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis	A Functional Self-Test Approach for Peripheral Cores in Processor-Based SoCs.	IOLTS	2007	DBLP DOI BibTeX RDF
35	Xiaoding Chen, Michael S. Hsiao	Testing Embedded Sequential Cores in Parallel Using Spectrum-Based BIST.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	built-in-self-test, System-on-a-chip, spectral analysis
35	Daniel Ziener, Stefan Assmus, Jürgen Teich	Identifying FPGA IP-Cores Based on Lookup Table Content Analysis.	FPL	2006	DBLP DOI BibTeX RDF
35	Umar Farooq 0009, Muhammad Saleem, Habibullah Jamal	Parameterized FIR Filtering IP Cores for Reusable SoC Design.	ITNG	2006	DBLP DOI BibTeX RDF	Finite Impulse Response (FIR) filter, Unfolded Direct Form (UDF), Folded Direct Form (FDF), Parameterized, SoC design, IP Core, Synthesis tools
35	Haihua Shen, Yunji Chen, Jing Huang	EmGen: An Automatic Test-Program Generation Tool for Embedded IP Cores.	ICESS	2004	DBLP DOI BibTeX RDF
35	George Lykakis, N. Mouratidis, Kyriakos Vlachos, Nikos A. Nikolaou, Stylianos Perissakis, G. Sourdis, George E. Konstantoulakis, Dionisios N. Pnevmatikatos, Dionisios I. Reisis	Efficient Field Processing Cores in an Innovative Protocol Processor System-on-Chip.	DATE	2003	DBLP DOI BibTeX RDF
35	Huaguo Liang, Cuiyun Jiang	Sharing BIST with Multiple Cores for System-on-a-Chip.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
35	Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian	Effective Software Self-Test Methodology for Processor Cores.	DATE	2002	DBLP DOI BibTeX RDF
35	K. Y. Ko, Mike W. T. Wong, Yim-Shu Lee	Testing System-On-Chip by Summations of Cores? Test Output Voltages.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
35	Satnam Singh, Carl Johan Lillieroth	Formal Verification of Reconfigurable Cores.	FCCM	1999	DBLP DOI BibTeX RDF
35	Janusz Rajski, Jerzy Tyszer	Modular logic built-in self-test for IP cores.	ITC	1998	DBLP DOI BibTeX RDF
34	Angela C. Sodan, Jacob Machina, Arash Deshmeh, Kevin Macnaughton, Bryan Esbaugh	Parallelism via Multithreaded and Multicore CPUs.	Computer	2010	DBLP DOI BibTeX RDF	Multithreaded cores, Heterogeneous cores, Application-level parallelism, Chip interconnects, GPUs, Multicore processors, Power efficiency
34	Roman L. Lysecky, Frank Vahid	Design and implementation of a MicroBlaze-based warp processor.	ACM Trans. Embed. Comput. Syst.	2009	DBLP DOI BibTeX RDF	soft processor cores, FPGA, dynamic optimization, hardware/software partitioning, configurable logic, Warp processors, just-in-time (JIT) compilation
34	Divya Gulati, Changkyu Kim, Simha Sethumadhavan, Stephen W. Keckler, Doug Burger	Multitasking workload scheduling on flexible-core chip multiprocessors.	PACT	2008	DBLP DOI BibTeX RDF	flexible cores, multitask scheduling, multicore architectures
34	Erik Jan Marinissen, Rohit Kapur, Maurice Lousberg, Teresa L. McLaurin, Mike Ricchetti, Yervant Zorian	On IEEE P1500's Standard for Embedded Core Test.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	core test wrapper, core test language, compliance levels, standardization, embedded cores
34	Roman L. Lysecky, Frank Vahid, Tony Givargis	Techniques for Reducing Read Latency of Core Bus Wrappers.	DATE	2000	DBLP DOI BibTeX RDF	bus wrapper, interfacing, system-on-a-chip, intellectual property, Cores, design reuse, on-chip bus
34	Major Bhadauria, Vincent M. Weaver, Sally A. McKee	Accomodating Diversity in CMPs with Heterogeneous Frequencies.	HiPEAC	2009	DBLP DOI BibTeX RDF
34	Seung Woo Son 0001, Mahmut T. Kandemir, Mustafa Karaköy, Dhruva R. Chakrabarti	A compiler-directed data prefetching scheme for chip multiprocessors.	PPoPP	2009	DBLP DOI BibTeX RDF	compiler, chip multiprocessors, prefetching, helper thread
34	Gerard J. M. Smit, André B. J. Kokkeler, Pascal T. Wolkotte, Marcel D. van de Burgwal	Multi-core architectures and streaming applications.	SLIP	2008	DBLP DOI BibTeX RDF	NoC design, multi-core SoC design, system design, streaming applications
34	Mijeom Kim, Mohan Kumar, Behrooz A. Shirazi	An Integrated Scheme for Address Assignment and Service Location in Pervasive Environments.	EUC	2005	DBLP DOI BibTeX RDF
34	Indradeep Ghosh, Niraj K. Jha, Sujit Dey	A low overhead design for testability and test generation technique for core-based systems-on-a-chip.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
30	Brais Bosquet, Daniel Cores, Lorenzo Seidenari, Víctor M. Brea 0001, Manuel Mucientes, Alberto Del Bimbo	A full data augmentation pipeline for small object detection based on generative adversarial networks.	Pattern Recognit.	2023	DBLP DOI BibTeX RDF
30	Daniel Cores, Víctor M. Brea 0001, Manuel Mucientes	Spatiotemporal tubelet feature aggregation and object linking for small object detection in videos.	Appl. Intell.	2023	DBLP DOI BibTeX RDF
30	Daniel Cores, Nicolás Vila Blanco, Manuel Mucientes, María J. Carreira	Few-Shot Image Classification for Automatic COVID-19 Diagnosis.	IbPRIA	2023	DBLP DOI BibTeX RDF
30	Daniel Cores, Lorenzo Seidenari, Alberto Del Bimbo, Víctor M. Brea 0001, Manuel Mucientes	Relation Networks for Few-Shot Video Object Detection.	IbPRIA	2023	DBLP DOI BibTeX RDF
30	Daniel Cores, Víctor M. Brea 0001, Manuel Mucientes, Lorenzo Seidenari, Alberto Del Bimbo	Downsampling GAN for Small Object Data Augmentation.	CAIP (1)	2023	DBLP DOI BibTeX RDF
30	Lucía Cores-Sarría, Brent J. Hale, Annie Lang	Danger, Sex, and Everything Else: A Comparison of Camera Angle and Camera Distance Effects Across Pictures of Varied Emotional Content.	J. Media Psychol. Theor. Methods Appl.	2022	DBLP DOI BibTeX RDF
30	Daniel Cores, Víctor M. Brea 0001, Manuel Mucientes	Short-term anchor linking and long-term self-guided attention for video object detection.	Image Vis. Comput.	2021	DBLP DOI BibTeX RDF
30	Fernando Cores, Fernando Guirado, Josep Lluís Lérida	High throughput BLAST algorithm using spark and cassandra.	J. Supercomput.	2021	DBLP DOI BibTeX RDF
30	Jordi Lladós, Fernando Cores, Fernando Guirado, Josep L. Lérida	Accurate consistency-based MSA reducing the memory footprint.	Comput. Methods Programs Biomed.	2021	DBLP DOI BibTeX RDF
30	Daniel Cores, Víctor M. Brea 0001, Manuel Mucientes	Spatio-Temporal Object Detection from UAV On-Board Cameras.	CAIP (2)	2021	DBLP DOI BibTeX RDF
30	John P. Morrissey, Prabhat Totoo, Kevin J. Hanley, Stefanos-Aldo Papanicolopulos, Jin Y. Ooi, Iván Cores Gonzalez, Bruno Raffin, Seyedmorteza Mostajabodaveh, Thomas Gierlinger	Post-processing and visualization of large-scale DEM simulation data with the open-source VELaSSCo platform.	Simul.	2020	DBLP DOI BibTeX RDF
30	Daniel Cores, Víctor M. Brea 0001, Manuel Mucientes	Spatio-temporal Tubelet Feature Aggregation and Object Linking in Videos.	CoRR	2020	DBLP BibTeX RDF
30	Adrián González-Sieira, Daniel Cores, Manuel Mucientes, Alberto Bugarín	Autonomous navigation for UAVs managing motion and sensing uncertainty.	Robotics Auton. Syst.	2020	DBLP DOI BibTeX RDF
30	Sergi Vila, Josep L. Lérida, Fernando Cores, Fernando Guirado, Fábio L. Verdi	WPSP: A Multi-correlated Weighted Policy for VM Selection and Migration for Cloud Computing.	Euro-Par	2020	DBLP DOI BibTeX RDF