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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 5518 occurrences of 2681 keywords
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Results
Found 7331 publication records. Showing 7331 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
63 | K. Korotaev |
Hierarchical CPU Schedulers for Multiprocessor Systems, Fair CPU Scheduling and Processes Isolation. |
CLUSTER |
2005 |
DBLP DOI BibTeX RDF |
|
61 | Ping Yang, Shu Dai, Xiuhua Wu, Yong Yang |
The Hardware Research of Dual-port RAM for Main-spare CPU in Rural Power Terminal System of Power Quantity Collection. |
CCTA |
2007 |
DBLP DOI BibTeX RDF |
dual-port RAM, main-spare CPU, terminal of power quantity collection, data exchange, parallel communication |
53 | John G. Cleary, Murray Pearson, Husam Kinawi |
The architecture of an optimistic CPU: the WarpEngine. |
HICSS (1) |
1995 |
DBLP DOI BibTeX RDF |
optimistic CPU, WarpEngine, shared memory CPU, single instructions, memory latency tolerance, executable instructions, TimeWarp algorithm, optimistic, single linear address space, single thread of control, reliability, caches, parallel architectures, fault tolerant computing, concurrency control, synchronisation, synchronisation, shared memory systems, memory architecture, cache storage, memory system, memory model, time stamped, memory accesses, local memory |
52 | Xiaodong Zhang 0001, Yanxia Qu, Li Xiao 0001 |
Improving Distributed Workload Performance by Sharing both CPU and Memory Resources. |
ICDCS |
2000 |
DBLP DOI BibTeX RDF |
|
50 | Dongyu Liu, Songqing Chen, Bo Shen 0003 |
AMTrac: adaptive meta-caching for transcoding. |
NOSSDAV |
2006 |
DBLP DOI BibTeX RDF |
CPU intensive computing, meta-caching, adaptation, transcoding |
49 | Toshihiro Tabata, Satoshi Hakomori, Kazutoshi Yokoyama, Hideo Taniguchi |
Controlling CPU Usage for Processes with Execution Resource for Mitigating CPU DoS Attack. |
MUE |
2007 |
DBLP DOI BibTeX RDF |
|
47 | Andrea Santoro, Francesco Quaglia |
PCI-DMA/CPU Handoff for Increased Effectiveness of Checkpointing Functionalities in CCL. |
DS-RT |
2003 |
DBLP DOI BibTeX RDF |
|
47 | Shimin Chen, Anastassia Ailamaki, Phillip B. Gibbons, Todd C. Mowry |
Improving hash join performance through prefetching. |
ACM Trans. Database Syst. |
2007 |
DBLP DOI BibTeX RDF |
CPU cache performance, CPU cache prefetching, group prefetching, software-pipelined prefetching, Hash join |
47 | C. Javier Castro Peña, Joseph B. Evans |
Performance Evaluation of Software Virtual Private Networks (VPN). |
LCN |
2000 |
DBLP DOI BibTeX RDF |
software virtual private networks, software VPN, CPU usage, VPN programs, Ethernet link, transference speed, CPU overhead, low speed serial link, performance evaluation, compression, data compression, encryption, local area networks, performance measurements, software performance evaluation, software packages, software packages, VPN, network throughput, business communication, 100 Mbit/s |
47 | Ashish Mehra, Atri Indiresan, Kang G. Shin |
Resource management for real-time communication: making theory meet practice. |
IEEE Real Time Technology and Applications Symposium |
1996 |
DBLP DOI BibTeX RDF |
host CPU, link resources, channel admissibility, resource capacity, implementation paradigms, admission control procedure, resource preemption overheads, link bandwidth, CPU bandwidth allocation, real-time systems, resource allocation, distributed processing, resource management, packet switching, operating systems (computers), real-time communication, network operating systems, packet-switched networks, computer network management, telecommunication congestion control, telecommunication channels, real-time channels |
46 | Loïc Duflot |
CPU Bugs, CPU Backdoors and Consequences on Security. |
ESORICS |
2008 |
DBLP DOI BibTeX RDF |
hardware bug, hardware backdoor, CPU, x86 |
46 | Uwe Langer |
Integration of Performance Evaluations in the Design Process of CPUs and Computer Systems. |
MMB |
1995 |
DBLP DOI BibTeX RDF |
CPU design, workload hierarchy, generic objects, information re-use, simulation, performance evaluation, modelling, computer design |
45 | Vignesh T. Ravi, Wenjing Ma, David Chiu 0001, Gagan Agrawal |
Compiler and runtime support for enabling generalized reduction computations on heterogeneous parallel configurations. |
ICS |
2010 |
DBLP DOI BibTeX RDF |
dynamic work distribution, generalized reductions, multi-cores, GPGPU, heterogeneous systems |
44 | Nick Richardson, Lun Bin Huang, Razak Hossain, Tommy Zounes, Naresh Soni, Julian Lewis |
The iCOREtm 520 MHz synthesizable CPU core. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
high-frequency, st20, cache, synthesis, pipeline, embedded, ASIC, branch-prediction, microarchitecture, CPU |
43 | Swann Perarnau, Guillaume Huard |
KRASH: reproducible CPU load generation on many cores machines. |
PPoPP |
2010 |
DBLP DOI BibTeX RDF |
cpu load generation, many cores, experimentation testbed |
43 | Walter Binder, Jarle Hulaas |
Self-accounting as Principle for Portable CPU Control in Java. |
Net.ObjectDays |
2004 |
DBLP DOI BibTeX RDF |
Bytecode rewriting, CPU accounting and control, Java, program transformations |
43 | Lei Shi 0001, Yuyan Sun, Lin Wei |
Effect of Scheduling Discipline on CPU-MEM Load Sharing System. |
GCC |
2007 |
DBLP DOI BibTeX RDF |
|
41 | Ergude Bao, Yang Yang, Hui Chen, Yuan-Yuan Lu, Xiao Liu, Weisheng Li 0001 |
A study and implementation of self-adaptive allocation algorithm for parallel program. |
CSTST |
2008 |
DBLP DOI BibTeX RDF |
Microsoft WCCS system, counter propagation neutral network, self-adaptive, API, CPU time |
41 | Abhishek Udupa, R. Govindarajan, Matthew J. Thazhuthaveetil |
Synergistic execution of stream programs on multicores with accelerators. |
LCTES |
2009 |
DBLP DOI BibTeX RDF |
CUDAa, partitioning, software pipelining, stream programming, GPU programming |
41 | Victor W. Lee, Changkyu Kim, Jatin Chhugani, Michael Deisher, Daehyun Kim 0001, Anthony D. Nguyen, Nadathur Satish, Mikhail Smelyanskiy, Srinivas Chennupaty, Per Hammarlund, Ronak Singhal, Pradeep Dubey |
Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPU. |
ISCA |
2010 |
DBLP DOI BibTeX RDF |
cpu architecture, gpu architecture, throughput computing, performance analysis, performance measurement, software optimization |
40 | Gerasimos Xydas, Jérôme Tassel |
Experimentation in CPU Control with Real-Time Java. |
ISORC |
2000 |
DBLP DOI BibTeX RDF |
host resource manager, QoS, worst case execution time, streaming media, real-time Java, CPU, end-to-end, rate-monotonic |
39 | Fan Wu 0013, Emmanuel Agu, Clifford Lindsay |
Adaptive CPU Scheduling to Conserve Energy in Real-Time Mobile Graphics Applications. |
ISVC (1) |
2008 |
DBLP DOI BibTeX RDF |
Real-time rendering, Energy conservation, Multiresolution rendering, CPU scheduling |
39 | Guilhem Paroux, Bernard Toursel, Richard Olejnik, Violeta Felea |
A Java CPU Calibration Tool for Load Balancing in Distributed Applications. |
ISPDC/HeteroPar |
2004 |
DBLP DOI BibTeX RDF |
Load observation, Java, Calibration, Distributed applications, Network of workstations, CPU time |
39 | Marc A. Nurmi, William E. Bejcek, Rod N. Gregoire, K. C. Liu, Mark D. Pohl |
Automatic Management of CPU and I/O Bottlenecks in Distributed Applications on ATM Networks. |
HPDC |
1996 |
DBLP DOI BibTeX RDF |
CPU bottleneck management, input output bottleneck management, computationally intensive applications, distributed process management, centralized application management, parallel programming, asynchronous transfer mode, message passing, message passing, programming environments, local area networks, distributed applications, bandwidth, ATM networks, software performance evaluation, parallel programming environments, workstation networks, application performance, virtual shared memory |
38 | Isaac Gelado, John H. Kelm, Shane Ryoo, Steven S. Lumetta, Nacho Navarro, Wen-mei W. Hwu |
CUBA: an architecture for efficient CPU/co-processor data communication. |
ICS |
2008 |
DBLP DOI BibTeX RDF |
co-processors |
38 | Chung-Hsing Hsu, Wu-chun Feng |
Effective Dynamic Voltage Scaling Through CPU-Boundedness Detection. |
PACS |
2004 |
DBLP DOI BibTeX RDF |
|
38 | Yap Siong Chua, Charles N. Winton |
A Simulation Tool for Teaching CPU Design and Microprogramming Concepts. |
APL |
1989 |
DBLP DOI BibTeX RDF |
APL |
38 | Alois Ferscha, Johannes Lüthi |
Estimating rollback overhead for optimism control in Time Warp. |
Annual Simulation Symposium |
1995 |
DBLP DOI BibTeX RDF |
rollback overhead, adaptive optimism control mechanism, performance pitfall, Time Warp distributed discrete event simulation protocol, DDES protocol, overoptimistic progression, event execution, simulated future, premature event execution, causality violations, performance inefficiencies, observed model parallelism, local virtual time, LVT progression per unit CPU time, arriving messages, simulation engine, optimal CPU delay interval, rollback probability, synchronization behavior, iPSC/860, protocols, virtual machines, discrete event simulation, adaptive systems, optimal control, cost model, distributed memory multiprocessor, time warp simulation, logical processes |
38 | Gregory Bollella, Kevin Jeffay |
Support for real-time computing within general purpose operating systems-supporting co-resident operating systems. |
IEEE Real Time Technology and Applications Symposium |
1995 |
DBLP DOI BibTeX RDF |
real-time computing support, co-resident operating systems, workstation applications, real-time communication services, real-time computation services, real-time computing technology development, commercial systems, predictable real-time kernel, shared device multiplexing, shared data structure partitioning, CPU executive, IBM Microkernel, Mach microkernel, OSF/1 server, uniprocessor periodic task scheduling, CPU capacity allocation, scheduling, software engineering, real-time systems, hardware, multimedia systems, processor scheduling, operating systems (computers), operating system kernels, distributed multimedia applications, general purpose operating systems |
37 | Dimitris Tsirogiannis, Stavros Harizopoulos, Mehul A. Shah |
Analyzing the energy efficiency of a database server. |
SIGMOD Conference |
2010 |
DBLP DOI BibTeX RDF |
cpu power, ssd, energy efficiency, power consumption, database server |
37 | Yen-Tso Liu, Tyng-Yeu Liang, Chi-Ting Huang, Ce-Kuen Shieh |
Memory Resource Considerations in the Load Balancing of Software DSM Systems. |
ICPP Workshops |
2003 |
DBLP DOI BibTeX RDF |
CPU resource, memory resource, load balance, distributed shared memory, page replacement |
37 | Tatsuo Nakajima, Hiroshi Fujita |
Experiences with adaptive QOS mapping scheme. |
RTCSA |
1996 |
DBLP DOI BibTeX RDF |
QOS mapping, CPU capacity, Quality of Service, operating systems, feedback control, multimedia computing, multimedia computing, dynamic mapping |
36 | Michela Becchi, Surendra Byna, Srihari Cadambi, Srimat T. Chakradhar |
Data-aware scheduling of legacy kernels on heterogeneous platforms with distributed memory. |
SPAA |
2010 |
DBLP DOI BibTeX RDF |
accelerators, distributed memory, multi-core processors, runtime, heterogeneous platforms |
35 | Mahmut T. Kandemir, Ozcan Ozturk 0001 |
Software-directed combined cpu/link voltage scaling fornoc-based cmps. |
SIGMETRICS |
2008 |
DBLP DOI BibTeX RDF |
compiler, CMP, NoC, voltage scaling, cpu, communication link |
34 | Alexander Khutoretskij, Sergei Bredikhin |
Distributions and Schedules of CPU Time in a Multiprocessor System When the Users' Utility Functions Are Linear. |
PaCT |
2009 |
DBLP DOI BibTeX RDF |
paid services, scheduling, linear programming, Distribution, multiprocessor system, CPU time, market equilibrium |
34 | Yoshihiro Sugaya, Hiroshi Tatsumi, Mitiharu Kobayashi, Hirotomo Aso |
Long-Term CPU Load Prediction System for Scheduling of Distributed Processes and its Implementation. |
AINA |
2008 |
DBLP DOI BibTeX RDF |
Long-Term CPU load prediction, runtime prediction, load balancing |
34 | Sriram Govindan, Arjun R. Nath, Amitayu Das, Bhuvan Urgaonkar, Anand Sivasubramaniam |
Xen and co.: communication-aware CPU scheduling for consolidated xen-based hosting platforms. |
VEE |
2007 |
DBLP DOI BibTeX RDF |
virtual machine monitor, xen, CPU scheduler, multi-tier application |
34 | Bhuvan Urgaonkar, Prashant J. Shenoy |
Sharc: Managing CPU and Network Bandwidth in Shared Clusters. |
IEEE Trans. Parallel Distributed Syst. |
2004 |
DBLP DOI BibTeX RDF |
Shared clusters, dedicated clusters, Sharc, nucleus, CPU and network bandwidth, hosting platforms, Linux, control plane, capsule |
34 | Marta Beltrán, José Luis Bosque |
Estimating a Workstation CPU Assignment with the DYPAP Monitor. |
ISPDC/HeteroPar |
2004 |
DBLP DOI BibTeX RDF |
CPU availability, monitoring, resources management, Computational models |
34 | Jun Wu 0010, Tei-Wei Kuo |
Real-Time Scheduling of CPU-Bound and I/O-Bound Processes. |
RTCSA |
1999 |
DBLP DOI BibTeX RDF |
CPU-Bound Process, I/O-Bound Process, Real-Time Systems, Real-Time Scheduling, Priority Ceiling Protocol |
34 | Ricardo Salem Zebulum, Marco Aurélio Cavalcanti Pacheco, Marley M. B. R. Vellasco |
Evolutionary Systems Applied to the Synthesis of a CPU Controller. |
SEAL |
1998 |
DBLP DOI BibTeX RDF |
Evolutionary Hardware, CPU control, Sequential Circuits |
34 | Andrea Acquaviva, Nicola Bombieri, Franco Fummi, Sara Vinco |
Automatic customization of device drivers for IP-cores used with assorted CPU organizations. |
CODES+ISSS |
2009 |
DBLP DOI BibTeX RDF |
device driver design, embedded systems, hardware-software codesign |
34 | Lorenzo Martignoni, Roberto Paleari, Giampaolo Fresi Roglia, Danilo Bruschi |
Testing CPU emulators. |
ISSTA |
2009 |
DBLP DOI BibTeX RDF |
software testing, emulation, automatic test generation, fuzzing |
34 | Mark Joselli, Marcelo Panaro de Moraes Zamith, Esteban Walter Gonzalez Clua, Anselmo Antunes Montenegro, Aura Conci, Regina Leal-Toledo, Luis Valente, Bruno Feijó, Marcos Cordeiro d'Ornellas, Cesar Tadeu Pozzer |
Automatic Dynamic Task Distribution between CPU and GPU for Real-Time Systems. |
CSE |
2008 |
DBLP DOI BibTeX RDF |
real-time loop models, real-time systems, Parallel computing, GPGPU, task distribution |
34 | Wanghong Yuan, Klara Nahrstedt |
Energy-efficient CPU scheduling for multimedia applications. |
ACM Trans. Comput. Syst. |
2006 |
DBLP DOI BibTeX RDF |
mobile computing, multimedia, Power management, soft real-time |
34 | Hai Jin 0001, Qionghua Hu, Xiaofei Liao, Hao Chen 0002, Dafu Deng |
IMAC: an importance-level based adaptive CPU scheduling scheme for multimedia and non-real time applications. |
AICCSA |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Kui-Yon Mun, Dae Woong Kim, Do-Hun Kim, Chan-Ik Park |
dDVS: An Efficient Dynamic Voltage Scaling Algorithm Based on the Differential of CPU Utilization. |
Asia-Pacific Computer Systems Architecture Conference |
2004 |
DBLP DOI BibTeX RDF |
|
34 | Eric Eide, Tim Stack, John Regehr, Jay Lepreau |
Dynamic CPU Management for Real-Time, Middleware-Based Systems. |
IEEE Real-Time and Embedded Technology and Applications Symposium |
2004 |
DBLP DOI BibTeX RDF |
|
34 | Anil Patel |
An inside look at the Z80, 000 CPU: Zilog's new 32-bit microprocessor. |
AFIPS National Computer Conference |
1984 |
DBLP DOI BibTeX RDF |
|
33 | Toni Mastelic, Ivona Brandic, Jasmina Jaarevic |
CPU Performance Coefficient (CPU-PC): A Novel Performance Metric Based on Real-Time CPU Resource Provisioning in Time-Shared Cloud Environments. |
CloudCom |
2014 |
DBLP DOI BibTeX RDF |
|
32 | Bin Lin 0002, Arindam Mallik, Peter A. Dinda, Gokhan Memik, Robert P. Dick |
User- and process-driven dynamic voltage and frequency scaling. |
ISPASS |
2009 |
DBLP DOI BibTeX RDF |
|
32 | Ming Wu 0006, Xian-He Sun |
Memory Conscious Task Partition and Scheduling in Grid Environments. |
GRID |
2004 |
DBLP DOI BibTeX RDF |
|
32 | Li Xiao 0001, Songqing Chen, Xiaodong Zhang 0001 |
Dynamic Cluster Resource Allocations for Jobs with Known and Unknown Memory Demands. |
IEEE Trans. Parallel Distributed Syst. |
2002 |
DBLP DOI BibTeX RDF |
memory-intensive workloads and trace-driven simulations, distributed systems, cluster computing, load sharing |
31 | Loïc Duflot |
CPU bugs, CPU backdoors and consequences on security. |
J. Comput. Virol. |
2009 |
DBLP DOI BibTeX RDF |
|
31 | Stanley Mazor |
Intel 8080 CPU Chip Development. |
IEEE Ann. Hist. Comput. |
2007 |
DBLP DOI BibTeX RDF |
Intel 8080, microchip, microprocessor, history, CPU, microcomputer |
30 | Michael Schöbel, Andreas Polze |
Kernel-mode scheduling server for CPU partitioning: a case study using the Windows research kernel. |
SAC |
2008 |
DBLP DOI BibTeX RDF |
CPU partitioning, windows research kernel, scheduling |
30 | Amith Kumar Nuggehalli Ramachandra, Avin Kumar Kannur |
Analysis of CPU Utilisation and Stack Consumption of a Multimedia Embedded System. |
DELTA |
2008 |
DBLP DOI BibTeX RDF |
CPU Utilisation, Stack Consumption |
30 | Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi |
Instruction-level test methodology for CPU core self-testing. |
ACM Trans. Design Autom. Electr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
CPU core testing, Instruction level testing, test instruction set, BIST, pipelined processor, software-based self testing |
30 | Dimitris Nikolos, Haridimos T. Vergos |
On the Yield of VLSI Processors with on-chip CPU Cache. |
EDCC |
1996 |
DBLP DOI BibTeX RDF |
Indexing terms On-chip CPU caches, Partially good chips, Fault Tolerance, Yield Enhancement |
30 | R. Gopalakrishnan, Guru M. Parulkar |
RMDP-a real-time CPU scheduling algorithm to provide QoS guarantees for protocol processing. |
IEEE Real Time Technology and Applications Symposium |
1995 |
DBLP DOI BibTeX RDF |
RMDP real-time CPU scheduling algorithm, processing guarantees, reduced contest switch operations, bandwidth guarantees, protocol session, NetBSD operating system, simulation, simulation, scheduling, real-time systems, protocols, delays, multimedia applications, processor scheduling, operating systems (computers), multimedia computing, QoS guarantees, delay guarantees, schedulability test, protocol processing |
29 | Yen-Lin Huang, Yun-Chung Shen, Ja-Ling Wu |
Scalable computation for spatially scalable video coding using NVIDIA CUDA and multi-core CPU. |
ACM Multimedia |
2009 |
DBLP DOI BibTeX RDF |
parallel computing, GPU, multi-core, CUDA, SVC |
29 | Xiaotie Deng, Li-Sha Huang, Minming Li |
On Walrasian Price of CPU Time. |
Algorithmica |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Rong Ge 0002, Xizhou Feng, Wu-chun Feng, Kirk W. Cameron |
CPU MISER: A Performance-Directed, Run-Time System for Power-Aware Clusters. |
ICPP |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Andrea Camesi, Jarle Hulaas, Walter Binder |
Continuous Bytecode Instruction Counting for CPU Consumption Estimation. |
QEST |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Dong Guo 0002, Liang Hu 0001, Meng Zhang 0006, Zhuopeng Zhang |
GcpSensor: a CPU Performance Tool for Grid Environments. |
QSIC |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Xiaotie Deng, Li-Sha Huang, Minming Li |
On Walrasian Price of CPU Time. |
COCOON |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Xiaoqin Ma, Gene Cooperman |
Fast Query Processing by Distributing an Index over CPU Caches. |
CLUSTER |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi |
Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores. |
Asian Test Symposium |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Sayaka Akioka, Yoichi Muraoka |
Extended forecast of CPU and network load on computational Grid. |
CCGRID |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Wanghong Yuan, Klara Nahrstedt |
ReCalendar: Calendaring and Scheduling Applications with CPU and Energy Resource Guarantees for Mobile Devices. |
PerCom |
2003 |
DBLP DOI BibTeX RDF |
|
29 | Thomas L. Martin, Daniel P. Siewiorek |
Nonideal battery and main memory effects on CPU speed-setting for low power. |
IEEE Trans. Very Large Scale Integr. Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
29 | Richard Wolski, Neil T. Spring, Jim Hayes |
Predicting the CPU Availability of Time-shared Unix Systems on the Computational Grid. |
HPDC |
1999 |
DBLP DOI BibTeX RDF |
|
29 | Junho Ahn, Jung-Hi Min, Hojung Cha, Rhan Ha |
A Power Management mechanism for Handheld Systems having a Multimedia Accelerator. |
PerCom |
2008 |
DBLP DOI BibTeX RDF |
handheld systems, multimedia accelerator, power management, CPU |
28 | Hisao Kameda |
Optimality of a Central Processor Scheduling Policy for Processing a Job Stream |
ACM Trans. Comput. Syst. |
1984 |
DBLP DOI BibTeX RDF |
1/0 bound, CPU bound, Markovian queuing model, dispatching policy, finite-source queue, job stream, machine repairman model, multiple-resource system, near-complete decomposability, multiprogramming, CPU scheduling, preemptive priority |
28 | Sotaro Ohara, Makoto Suzuki, Shunsuke Saruwatari, Hiroyuki Morikawa |
A Prototype of a Multi-core Wireless Sensor Node for Reducing Power Consumption. |
SAINT |
2008 |
DBLP DOI BibTeX RDF |
multi-core CPU, sensor network, hard real-time, low power consumption |
28 | Faraz Idris Khan, Eui-nam Huh |
Adaptive Vertical Handoff Management Architecture. |
International Conference on Computational Science (4) |
2007 |
DBLP DOI BibTeX RDF |
feedback scheduling, CPU scheduler adaptation, quality of service, resource management, vertical handoff |
28 | Jacob Engel, Joseph Meneskie, Taskin Koçak |
Performance analysis of network protocol offload in a simulation environment. |
ACM Southeast Regional Conference |
2006 |
DBLP DOI BibTeX RDF |
CPU utilization, gigabit NIC, offload engines, TCP, IP, UDP |
28 | Cédric Dinont, Philippe Mathieu, Emmanuel Druon, Patrick Taillibert |
Artifacts for time-aware agents. |
AAMAS |
2006 |
DBLP DOI BibTeX RDF |
CPU sharing, coordination, artifacts |
27 | Chuliang Weng, Zhigang Wang, Minglu Li 0001, Xinda Lu |
The hybrid scheduling framework for virtual machine systems. |
VEE |
2009 |
DBLP DOI BibTeX RDF |
virtualization, scheduling strategy, hybrid scheduling |
27 | Henry Wong, Anne Bracy, Ethan Schuchman, Tor M. Aamodt, Jamison D. Collins, Perry H. Wang, Gautham N. Chinya, Ankur Khandelwal Groen, Hong Jiang, Hong Wang 0003 |
Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor. |
PACT |
2008 |
DBLP DOI BibTeX RDF |
ia32, on-chip integration, chip multiprocessor, heterogeneous |
27 | Young-Mi Kim, Dae-Joon Hwang |
The Flow Control of Audio Data Using Distributed Terminal Mixing in Multi-point Communication. |
FQAS |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Dong-Jae Kang, Young-Ho Kim, Gyu-Il Cha, Sung-In Jung, Myung-Joon Kim, Hae-Young Bae |
Design and Implementation of Zero-Copy Data Path for Efficient File Transmission. |
HPCC |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Mee Young Sung, Suk-Min Whang, Yonghee Yoo, Nam-Joong Kim, Jong Seung Park, Wonik Choi |
Parallel Processing for Reducing the Bottleneck in Realtime Graphics Rendering. |
PCM |
2006 |
DBLP DOI BibTeX RDF |
Realtime graphics rendering, Distribution of rendering operations, Optimization, Parallel processing, Multithreading, Bottleneck |
27 | Youngjin Cho, Naehyuck Chang |
Memory-aware energy-optimal frequency assignment for dynamic supply voltage scaling. |
ISLPED |
2004 |
DBLP DOI BibTeX RDF |
low power, memory system, SDRAM |
27 | Stefan Manegold, Peter A. Boncz, Martin L. Kersten |
Optimizing Main-Memory Join on Modern Hardware. |
IEEE Trans. Knowl. Data Eng. |
2002 |
DBLP DOI BibTeX RDF |
memory access optimization, decomposed storage model, query processing, Main-memory databases, join algorithms, implementation techniques |
27 | Hisao Kameda |
Effects of Job Loading Policies for Multiprogramming Systems in Processing a Job Stream. |
ACM Trans. Comput. Syst. |
1986 |
DBLP DOI BibTeX RDF |
|
27 | Jeffrey R. Spirn |
Multi-queue scheduling of two tasks. |
SIGMETRICS |
1976 |
DBLP DOI BibTeX RDF |
|
26 | Joel Grodstein, Rachid Rayess, Tad Truex, Linda Shattuck, Sue Lowell, Dan Bailey, David Bertucci, Gabriel P. Bischoff, Daniel E. Dever, Mike Gowan, Roy Lane, Brian Lilly, Krishna Nagalla, Rahul Shah 0004, Emily Shriver, Shi-Huang Yin, Shannon V. Morton |
Power and CAD considerations for the 1.75mbyte, 1.2ghz L2 cache on the alpha 21364 CPU. |
ACM Great Lakes Symposium on VLSI |
2002 |
DBLP DOI BibTeX RDF |
low-power, cache memory, CPU, timing verification, logic verification |
25 | Janusz Sosnowski, Lukasz Tupaj |
CPU Testability in Embedded Systems. |
DELTA |
2010 |
DBLP DOI BibTeX RDF |
CPU testing, embedded systems, testability, software-based-self-test |
25 | Enrico Bini, Giorgio C. Buttazzo, Giuseppe Lipari |
Minimizing CPU energy in real-time systems with discrete speed management. |
ACM Trans. Embed. Comput. Syst. |
2009 |
DBLP DOI BibTeX RDF |
CPU energy, Real-time systems |
25 | Jemal H. Abawajy, Sivarama P. Dandamudi |
Scheduling Parallel Jobs with CPU and I/O Resource Requirements in Cluster Computing Systems. |
MASCOTS |
2003 |
DBLP DOI BibTeX RDF |
Coordinated CPU-I/O Resources Scheduling, High-Performance Computing, Cluster computing, Parallel I/O, Parallel Job Scheduling |
25 | Lingyun Yang, Ian T. Foster, Jennifer M. Schopf |
Homeostatic and Tendency-Based CPU Load Predictions. |
IPDPS |
2003 |
DBLP DOI BibTeX RDF |
CPU Load prediction, resource-sharing environment, time series |
25 | Dimitris Nikolos, Haridimos T. Vergos |
On the Yield of VLSI Processors with On-Chip CPU Cache. |
IEEE Trans. Computers |
1999 |
DBLP DOI BibTeX RDF |
on-chip CPU caches, partially good chips, Fault tolerance, yield enhancement |
25 | Stephanie Dogimont, Martin Gumm, Friederich Mombers, Daniel Mlynek, Alessandro Torielli |
Conception and design of a RISC CPU for the use as embedded controller within a parallel multimedia architecture. |
ASAP |
1997 |
DBLP DOI BibTeX RDF |
RISC CPU, parallel multimedia architecture, high performance control structure, parallel motion estimation architecture, MPEG2 coding, combined MIMD-SIMD approach, motion estimation, ASIP, subword parallelism, embedded controller |
25 | F. Frances Yao, Alan J. Demers, Scott Shenker |
A Scheduling Model for Reduced CPU Energy. |
FOCS |
1995 |
DBLP DOI BibTeX RDF |
computer power supplies, reduced CPU energy, energy usage, minimum-energy schedule, competitive performance, scheduling, power consumption, job scheduling, on-line algorithms, power function, scheduling model |
25 | Mark D. Hill, Alan Jay Smith |
Evaluating Associativity in CPU Caches. |
IEEE Trans. Computers |
1989 |
DBLP DOI BibTeX RDF |
CPU caches, cache miss ratio, forest simulation, all-associativity simulation, stack simulation, associativity, buffer storage, content-addressable storage, direct-mapped, set-associative |
24 | Haoqiang Zheng, Jason Nieh |
WARP: Enabling fast CPU scheduler development and evaluation. |
ISPASS |
2009 |
DBLP DOI BibTeX RDF |
|
24 | Yasuhiko Ogata, Toshio Endo, Naoya Maruyama, Satoshi Matsuoka |
An efficient, model-based CPU-GPU heterogeneous FFT library. |
IPDPS |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Arun A. Nair, Lizy K. John |
Simulation points for SPEC CPU 2006. |
ICCD |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Chun Zhang, Rong N. Chang, Chang-Shing Perng, Edward So, Chunqiang Tang, Tao Tao |
Leveraging Service Composition Relationship to Improve CPU Demand Estimation in SOA Environments. |
IEEE SCC (1) |
2008 |
DBLP DOI BibTeX RDF |
|
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