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Searching for phrase cycle-accurate (changed automatically) with no syntactic query expansion in all metadata.

Publication years (Num. hits)
1995-2000 (26) 2001-2002 (33) 2003 (32) 2004 (57) 2005 (68) 2006 (60) 2007 (60) 2008 (54) 2009 (35) 2010 (17) 2011-2012 (17) 2013-2014 (15) 2015-2017 (27) 2018-2019 (18) 2020-2023 (17) 2024 (1)
Publication types (Num. hits)
article(93) inproceedings(440) phdthesis(4)
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The graphs summarize 455 occurrences of 299 keywords

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Found 537 publication records. Showing 537 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
68Jaejin Lee, Junghyun Kim, Choonki Jang, Seungkyun Kim, Bernhard Egger 0002, Kwangsub Kim, Sangyong Han FaCSim: a fast and cycle-accurate architecture simulator for embedded systems. Search on Bibsonomy LCTES The full citation details ... 2008 DBLP  DOI  BibTeX  RDF virtual prototyping, architecture simulator, full-system simulation, simulator parallelization, cycle-accurate simulation
55Matt T. Yourst PTLsim: A Cycle Accurate Full System x86-64 Microarchitectural Simulator. Search on Bibsonomy ISPASS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF client-server networked benchmark, PTLsim, cycle accurate full system, x86-64 microarchitectural simulator, superscalar x86-64 processor core, full-speed native execution, microarchitectural simulators, x86 ISA, microoperation level, multiprocessor capable simulation, Xen hypervisor, AMD Athlon 64 machine, virtual machine
51Hoonmo Yang, Moonkey Lee Embedded Processor Validation Environment Using a Cycle-Accurate Retargetable Instruction-Set Simulator. Search on Bibsonomy J. Supercomput. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF cycle-accurate, validation, system-on-chip (SoC), architecture description language (ADL), retargetable, instruction-set simulator
50Guillermo Maturana, James L. Ball, Jeffery Gee, Amaresh Iyer, J. Michael O'Connor Incas: a cycle accurate model of UltraSPARC. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF cycle accurate model, UltraSPARC, Incas, message-passing mechanism, simulating concurrent modules, performance evaluation, C++, virtual machines, logic testing, microprocessor chips, performance estimates, diagnostics, tuning, RTL simulations, processor verification
47Scott J. Weber, Matthew W. Moskewicz, Matthias Gries, Christian Sauer 0001, Kurt Keutzer Fast cycle-accurate simulation and instruction set generation for constraint-based descriptions of programmable architectures. Search on Bibsonomy CODES+ISSS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF automatic control generation, instruction set extraction, cycle-accurate simulation
47Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane Fast exploration of bus-based on-chip communication architectures. Search on Bibsonomy CODES+ISSS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF bus cycle accurate modeling, fast communication architecture exploration, shared bus architectures, transaction level modeling, AMBA
42Mehrdad Reshadi, Daniel Gajski A cycle-accurate compilation algorithm for custom pipelined datapaths. Search on Bibsonomy CODES+ISSS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF NISC, cycle-accurate compiler, scheduling
42Chen Kang Lo, Ren-Song Tsay Automatic generation of Cycle Accurate and Cycle Count Accurate transaction level bus models from a formal model. Search on Bibsonomy ASP-DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
39Márcio Oyamada, Flávio Rech Wagner, Marius Bonaciu, Wander O. Cesário, Ahmed Amine Jerraya Software Performance Estimation in MPSoC Design. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF cycle-accurate simulation model, software performance estimation, MPSoC design, software-dominated embedded systems, integrated methodology, bus-functional model, multiprocessor platform, MPEG4 encoder, neural networks, performance analysis, design space exploration, design validation
39Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane Extending the transaction level modeling approach for fast communication architecture exploration. Search on Bibsonomy DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF bus cycle accurate modeling, communication architecture exploration, shared bus architectures, transaction level modeling, AMBA
39Daniel Christopher Powell, Björn Franke Using continuous statistical machine learning to enable high-speed performance prediction in hybrid instruction-/cycle-accurate instruction set simulators. Search on Bibsonomy CODES+ISSS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF continuous statistical machine learning, performance prediction, instruction set simulator
38Joshua L. Kihm, Samuel D. Strom, Daniel A. Connors Phase-Guided Small-Sample Simulation. Search on Bibsonomy ISPASS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF SpedOOO benchmark suite, phase-guided small-sample simulation, sampled simulation, phase-based simulation, benchmark evaluation suite, execution-aware sampling-based simulation, design space exploration, sampling method, processor design, cycle-accurate simulation
37Ines Viskic, Samar Abdi, Daniel D. Gajski Automatic generation of embedded communication SW for heterogeneous MPSoC platforms. Search on Bibsonomy LCTES The full citation details ... 2007 DBLP  DOI  BibTeX  RDF custom communication SW, pin/cycle accurate models, MPSoC, system level design, transaction level models, platform based design, automatic synthesis, on-chip communication
36Seongbeom Kim, Fang Liu, Yan Solihin, Ravi R. Iyer 0001, Li Zhao 0002, W. Cohen Accelerating Full-System Simulation through Characterizing and Predicting Operating System Performance. Search on Bibsonomy ISPASS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF memory hierarchy model, full-system simulation acceleration, operating system performance characterization, operating system performance prediction, computer hardware complexity, cycle-accurate processor system simulation overheads, system libraries, OS service performance behavior, processor hierarchy model, Linux, software complexity
36Hiroshi Nakashima, Masahiro Konishi, Takashi Nakada An accurate and efficient simulation-based analysis for worst case interruption delay. Search on Bibsonomy CASES The full citation details ... 2006 DBLP  DOI  BibTeX  RDF worst case interruption delay, cycle accurate simulation
35Soheil Samii, Mikko Selkälä, Erik Larsson, Krishnendu Chakrabarty, Zebo Peng Cycle-Accurate Test Power Modeling and Its Application to SoC Test Architecture Design and Scheduling. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
35Smruti R. Sarangi, Brian Greskamp, Josep Torrellas CADRE: Cycle-Accurate Deterministic Replay for Hardware Debugging. Search on Bibsonomy DSN The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
33Qing Wu 0002, Qinru Qiu, Massoud Pedram, Chih-Shun Ding Cycle-accurate macro-models for RT-level power analysis. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
33Michael Ferdman, Babak Falsafi Last-Touch Correlated Data Streaming. Search on Bibsonomy ISPASS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF predictor lookahead, last-touch correlated data streaming, address-correlating predictor, cache block address identification, correlation data storage, program active memory footprint, prediction lookahead, off-chip correlation data lookup, scalable on-chip table, low-latency lookup, on-chip storage, last-touch predictor, prefetch, superscalar processor, cycle-accurate simulation
33Shobana Padmanabhan, Phillip H. Jones, David V. Schuehler, Scott J. Friedman, Praveen Krishnamurthy, Huakai Zhang, Roger D. Chamberlain, Ron Cytron, Jason E. Fritts, John W. Lockwood Extracting and Improving Microarchitecture Performance on Reconfigurable Architectures. Search on Bibsonomy Int. J. Parallel Program. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF cycle-accurate hardware profiling, performance, architecture, Reconfigurable
31Pankaj Chauhan, Deepak Goyal, Gagan Hasteer, Anmol Mathur, Nikhil Sharma Non-cycle-accurate sequential equivalence checking. Search on Bibsonomy DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF unit product machine, model checking, formal verification, high level synthesis, sequential equivalence checking
31Dohyung Kim 0007, Soonhoi Ha, Rajesh Gupta 0001 CATS: cycle accurate transaction-driven simulation with multiple processor simulators. Search on Bibsonomy DATE The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
31Lin Zhong 0001, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha RTL-Aware Cycle-Accurate Functional Power Estimation. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
31Mehrdad Reshadi, Bita Gorjiara, Nikil D. Dutt Generic Processor Modeling for Automatically Generating Very Fast Cycle-Accurate Simulators. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
31Mehrdad Reshadi, Nikil D. Dutt Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation. Search on Bibsonomy DATE The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
31Lin Zhong 0001, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha Power estimation for cycle-accurate functional descriptions of hardware. Search on Bibsonomy ICCAD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
30Junghee Lee, Joonhwan Yi Cycle error correction in asynchronous clock modeling for cycle-based simulation. Search on Bibsonomy ASP-DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
30John W. Haskins Jr., Kevin Skadron Accelerated warmup for sampled microarchitecture simulation. Search on Bibsonomy ACM Trans. Archit. Code Optim. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Reuse latency, sampled simulation, warmup
29Cristiano Pereira, Jeremy Lau, Brad Calder, Rajesh K. Gupta 0001 Dynamic phase analysis for cycle-close trace generation. Search on Bibsonomy CODES+ISSS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF SimPoint, simulation, tracing, phase
29Björn Franke Fast cycle-approximate instruction set simulation. Search on Bibsonomy SCOPES The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
28Hans Eveking, Tobias Dornes, Martin Schweikert Using SystemVerilog assertions to relate non-cycle-accurate to cycle-accurate designs. Search on Bibsonomy HLDVT The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
28Ben L. Titzer, Jens Palsberg Nonintrusive precision instrumentation of microcontroller software. Search on Bibsonomy LCTES The full citation details ... 2005 DBLP  DOI  BibTeX  RDF cycle-accurate, instruction-level simulation, sensor networks, monitoring, debugging, profiling, instrumentation, parallel simulation
28Leonardo R. Bachega, José R. Brunheroto, Luiz De Rose, Pedro Mindlin, José E. Moreira The BlueGene/L pseudo cycle-accurate simulator. Search on Bibsonomy ISPASS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
27Jürgen Schnerr, Oliver Bringmann 0001, Wolfgang Rosenstiel Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs. Search on Bibsonomy DATE The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
26Masahiro Yano, Toru Takasaki, Takashi Nakada, Hiroshi Nakashima An Accurate and Efficient Time-Division Parallelization of Cycle Accurate Architectural Simulators. Search on Bibsonomy Annual Simulation Symposium The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
25Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs. Search on Bibsonomy FPGA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF simulation, FPGA, prototyping, performance models, emulation
25José Gabriel F. Coutinho, Jun Jiang, Wayne Luk Interleaving Behavioral and Cycle-Accurate Descriptions for Reconfigurable Hardware Compilation. Search on Bibsonomy FCCM The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
25Antoine Fraboulet, Tanguy Risset, Antoine Scherrer Cycle Accurate Simulation Model Generation for SoC Prototyping. Search on Bibsonomy SAMOS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
25Syed Saif Abrar Cycle-Accurate Energy Model and Source-Independent Characterization Methodology for Embedded Processors. Search on Bibsonomy VLSI Design The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
25Antonio Carlos Schneider Beck, Júlio C. B. de Mattos, Flávio Rech Wagner, Luigi Carro CACO-PS: A General Purpose Cycle-Accurate Configurable Power Simulator. Search on Bibsonomy SBCCI The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
25Bengt Werner, Peter S. Magnusson A Hybrid Simulation Approach Enabling Performance Characterization of Large Software Systems. Search on Bibsonomy MASCOTS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
23Rajat Chaudhry, Daniel L. Stasiak, Stephen D. Posluszny, Sang H. Dhong A cycle accurate power estimation tool. Search on Bibsonomy ASP-DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
23Hoonmo Yang, Moonkey Lee Design of a Cycle-Accurate User-Retargetable Instruction-Set Simulator Using Process-Based Scheduling Scheme. Search on Bibsonomy CIS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
23Jingzhao Ou, Viktor K. Prasanna Design space exploration using arithmetic-level hardware--software cosimulation for configurable multiprocessor platforms. Search on Bibsonomy ACM Trans. Embed. Comput. Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF FPGA, design space exploration, processor, cosimulation
22Stefan Farfeleder, Andreas Krall, R. Nigel Horspool Ultra Fast Cycle-Accurate Compiled Emulation of Inorder Pipelined Architectures. Search on Bibsonomy SAMOS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
22Andrew Over, Peter E. Strazdins, Bill Clarke Cycle Accurate Memory Modelling: A Case-Study in Validation. Search on Bibsonomy MASCOTS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
22Naehyuck Chang, Kwanho Kim, Hyung Gyu Lee Cycle-accurate energy measurement and characterization with a case study of the ARM7TDMI [microprocessors]. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
22Habib ul Hasan Khan, Diana Göhringer Cycle-Accurate and Cycle-Reproducible Debugging of Embedded Designs Using Artificial Intelligence. Search on Bibsonomy FPL The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
22Sameh W. Asaad, Ralph Bellofatto, Bernard Brezzo, Chuck Haymes, Mohit Kapur, Benjamin D. Parker, Thomas Roewer, Proshanta Saha, Todd Takken, José A. Tierno A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation. Search on Bibsonomy FPGA The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
22Junghee Lee, Joonhwan Yi Industrial experience with cycle error computation of cycle-accurate transaction level models. Search on Bibsonomy SoCC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
22Richard Buchmann Modélisation et Simulation Rapide au niveau cycle pour l'Exploration Architecturale de Systèmes Intégrés sur puce. (Modeling and Fast Cycle Accurate Simulation for Architectural Exploration of System On Chip). Search on Bibsonomy 2006   RDF
21Hyo-Joong Suh, Sung Woo Chung An Accurate Architectural Simulator for ARM1136. Search on Bibsonomy EUC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
20Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints. Search on Bibsonomy ASP-DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF TAM design, thermal-aware test, wrapper design, test scheduling, SOC test
20Derek Chiou, Dam Sunwoo, Joonsoo Kim, Nikhil A. Patil, William H. Reinhart, Darrel Eric Johnson, Jebediah Keefe, Hari Angepat FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators. Search on Bibsonomy MICRO The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
20Nicholas Jun Hao Ip, Stephen A. Edwards A Processor Extension for Cycle-Accurate Real-Time Software. Search on Bibsonomy EUC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
20Eunseok Song, Young-Kil Park, Soon Kwon, Soo-Ik Chae A Cycle-Accurate Energy Estimator for CMOS Digital Circuits. Search on Bibsonomy PATMOS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
20In-Cheol Park, Se-Hyeon Kang, Yongseok Yi Fast Cycle-accurate Behavioral Simulation for Pipelined Processors Using Early Pipeline Evaluation. Search on Bibsonomy ICCAD The full citation details ... 2003 DBLP  DOI  BibTeX  RDF C++
20Hyung Gyu Lee, Sungyuep Nam, Naehyuck Chang Cycle-accurate Energy Measurement and High-Level Energy Characterization of FPGAs. Search on Bibsonomy ISQED The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
20Naehyuck Chang, Kwanho Kim, Hyung Gyu Lee Cycle-accurate energy consumption measurement and analysis: case study of ARM7TDMI. Search on Bibsonomy ISLPED The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
20Wu Ye, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin The design and use of simplepower: a cycle-accurate energy estimation tool. Search on Bibsonomy DAC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
20Muhammad Rashid, Bernard Pottier Application Capturing and Performance Estimation in an Holistic Design Environment. Search on Bibsonomy ECBS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
20Tarek M. Taha, D. Scott Wills An Instruction Throughput Model of Superscalar Processors. Search on Bibsonomy IEEE International Workshop on Rapid System Prototyping The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
17Olaf Landsiedel, Muhammad Hamad Alizai, Klaus Wehrle When Timing Matters: Enabling Time Accurate and Scalable Simulation of Sensor Network Applications. Search on Bibsonomy IPSN The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
17Derek Chiou, Dam Sunwoo, Joonsoo Kim, Nikhil A. Patil, William H. Reinhart, Darrel Eric Johnson, Zheng Xu 0004 The FAST methodology for high-speed SoC/computer simulation. Search on Bibsonomy ICCAD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
17Alex Bobrek, JoAnn M. Paul, Donald E. Thomas Shared Resource Access Attributes for High-Level Contention Models. Search on Bibsonomy DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
17Ivan Augé, Frédéric Pétrot, François Donnet, Pascal Gomez Platform-based design from parallel C specifications. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
17Jingzhao Ou, Viktor K. Prasanna MATLAB/Simulink Based Hardware/Software Co-Simulation for Designing Using FPGA Configured Soft Processors. Search on Bibsonomy IPDPS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
17Ozgur Celebican, Tajana Simunic Rosing, Vincent John Mooney III Energy estimation of peripheral devices in embedded systems. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF audio, device drivers, energy estimation, software optimization
16Ram Srinivasan, Jeanine E. Cook, Olaf M. Lubeck Performance modeling using Monte Carlo simulation. Search on Bibsonomy IEEE Comput. Archit. Lett. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
15Ivano Barbieri, Massimo Bariani, Alberto Cabitto, Marco Raggio A Simulation and Exploration Technology for Multimedia-Application-Driven Architectures. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Hw-Sw co-design, simulation speed, simulation accuracy, simulation, multimedia, system on chip, DSP, flexibility, VLIW, architecture exploration, ISA
15Tero Rissa, Adam Donlin, Wayne Luk Evaluation of SystemC Modelling of Reconfigurable Embedded Systems. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
15Tao Wang 0004, Qigang Wang, Dong Liu, Michael Liao, Kevin Wang, Lu Cao, Li Zhao 0002, Ravi R. Iyer 0001, Ramesh Illikkal, John Du, Liang Wang Hardware/Software Co-Simulation for Last Level Cache Exploration. Search on Bibsonomy NAS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
15Rabie Ben Atitallah, Smaïl Niar, Samy Meftali, Jean-Luc Dekeyser An MPSoC Performance Estimation Framework Using Transaction Level Modeling. Search on Bibsonomy RTCSA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
14Daniela Genius, Ludovic Apvrille Cycle-Accurate Virtual Prototyping with Multiplicity. Search on Bibsonomy MODELSWARD The full citation details ... 2024 DBLP  BibTeX  RDF
14Eduardo Rhod, Behnam Ghavami, Zhenman Fang, Lesley Shannon A Cycle-Accurate Soft Error Vulnerability Analysis Framework for FPGA-based Designs. Search on Bibsonomy CoRR The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
14Pietro Nannipieri, Stefano Di Matteo, Luca Crocetti, Luca Zulberti, Luca Fanucci, Sergio Saponara Cycle-Accurate Verification of the Cryptographic Co-Processor for the European Processor Initiative. Search on Bibsonomy ApplePies The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
14Alban Gruin, Thomas Carle, Christine Rochange, Pascal Sainrat Validation of Processor Timing Models Using Cycle-Accurate Timing Simulators. Search on Bibsonomy WCET The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
14You Li, Guannan Zhao, Yunqi He, Hai Zhou 0001 SE3: Sequential Equivalence Checking for Non-Cycle-Accurate Design Transformations †. Search on Bibsonomy DAC The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
14Leilei Jin, Wenjie Fu, Ming Ling, Longxing Shi A Fast Cross-Layer Dynamic Power Estimation Method by Tracking Cycle-Accurate Activity Factors With Spark Streaming. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
14Nils Wisiol, Patrick Gersch, Jean-Pierre Seifert Cycle-Accurate Power Side-Channel Analysis Using the ChipWhisperer: a Case Study on Gaussian Sampling. Search on Bibsonomy IACR Cryptol. ePrint Arch. The full citation details ... 2022 DBLP  BibTeX  RDF
14Nils Wisiol, Patrick Gersch, Jean-Pierre Seifert Cycle-Accurate Power Side-Channel Analysis Using the ChipWhisperer: A Case Study on Gaussian Sampling. Search on Bibsonomy CARDIS The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
14Kanishkan Vadivel, Fernando García-Redondo, Ali BanaGozar, Henk Corporaal, Shidhartha Das SACA: System-level Analog CIM Accelerators Simulation Framework: Architecture and Cycle-accurate System-to-device Simulator. Search on Bibsonomy DCIS The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
14Shang Li 0001, Zhiyuan Yang 0001, Dhiraj Reddy, Ankur Srivastava 0001, Bruce L. Jacob DRAMsim3: A Cycle-Accurate, Thermal-Capable DRAM Simulator. Search on Bibsonomy IEEE Comput. Archit. Lett. The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
14Wenjie Fu, Ming Ling, Wei Wang, Longxing Shi AMPS: Accelerating McPAT Power Evaluation Without Cycle-Accurate Simulations. Search on Bibsonomy IEEE Embed. Syst. Lett. The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
14Moon Gi Seok, Hessam S. Sarjoughian, Changbeom Choi, Daejin Park Fast and Cycle-Accurate Simulation of RTL NoC Designs Using Test-Driven Cellular Automata. Search on Bibsonomy IEEE Access The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
14Riaz-ul-haque Mian, Michihiro Shintani, Michiko Inoue Cycle-Accurate Evaluation of Software-Hardware Co-Design of Decimal Computation in RISC-V Ecosystem. Search on Bibsonomy CoRR The full citation details ... 2020 DBLP  BibTeX  RDF
14Juan M. Cebrian, Adrián Barredo, Helena Caminal, Miquel Moretó, Marc Casas, Mateo Valero Semi-automatic validation of cycle-accurate simulation infrastructures: The case for gem5-x86. Search on Bibsonomy Future Gener. Comput. Syst. The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
14Lukas Steiner, Matthias Jung 0001, Felipe S. Prado, Kirill Bykov, Norbert Wehn DRAMSys4.0: A Fast and Cycle-Accurate SystemC/TLM-Based DRAM Simulator. Search on Bibsonomy SAMOS The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
14Habib ul Hasan Khan, Ariel Podlubne, Gökhan Akgün, Diana Göhringer Cycle-Accurate Debugging of Embedded Designs Using Recurrent Neural Networks. Search on Bibsonomy ARC The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
14Erwan Lenormand, Thierry Goubier, Loïc Cudennec, Henri-Pierre Charles A combined fast/cycle accurate simulation tool for reconfigurable accelerator evaluation: application to distributed data management. Search on Bibsonomy RSP The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
14Michael F. Dossis Rapid, Formal Verification with Automated and Executable, Cycle-accurate simulators, and Generated Testbenches. Search on Bibsonomy PCI The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
14Asif Ali Khan, Fazal Hameed, Robin Bläsing, Stuart S. P. Parkin, Jerónimo Castrillón RTSim: A Cycle-Accurate Simulator for Racetrack Memories. Search on Bibsonomy IEEE Comput. Archit. Lett. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
14Yuze Chi, Young-kyu Choi, Jason Cong, Jie Wang 0022 Rapid Cycle-Accurate Simulator for High-Level Synthesis. Search on Bibsonomy FPGA The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
14Habib ul Hasan Khan, Gökhan Akgün, Ariel Podlubne, Felix Wegener, Amir Moradi 0001, Diana Göhringer Cycle-Accurate Debugging of Multi-clock Reconfigurable Systems. Search on Bibsonomy ReConFig The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
14Shang Li 0001, Rommel Sánchez Verdejo, Petar Radojkovic, Bruce L. Jacob Rethinking cycle accurate DRAM simulation. Search on Bibsonomy MEMSYS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
14Konstantinos Iordanou, Oscar Palomar, John Mawer, Cosmin Gorgovan, Andy Nisbet, Mikel Luján SimAcc: A Configurable Cycle-Accurate Simulator for Customized Accelerators on CPU-FPGAs SoCs. Search on Bibsonomy FCCM The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
14Riaz-ul-haque Mian, Michihiro Shintani, Michiko Inoue Cycle-Accurate Evaluation of Software-Hardware Co-Design of Decimal Computation in RISC-V Ecosystem. Search on Bibsonomy SoCC The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
14Kun-Chih Jimmy Chen, Ting-Yi George Wang, Yueh-Chi Andrew Yang Cycle-Accurate NoC-based Convolutional Neural Network Simulator. Search on Bibsonomy COINS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
14Anushree Mahapatra, Yidi Liu, Benjamin Carrión Schäfer Accelerating cycle-accurate system-level simulations through behavioral templates. Search on Bibsonomy Integr. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
14Chalak Ori, Weiguang Cai, Wei Li, Lei Fang, Libing Zheng, Jintang Wang, Zuguang Wu, Xiongli Gu, Haibin Wang, Avi Mendelson ScaleSimulator: A Fast and Cycle-Accurate Parallel Simulator for Architectural Exploration. Search on Bibsonomy CoRR The full citation details ... 2018 DBLP  BibTeX  RDF
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