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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 10 occurrences of 10 keywords
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Results
Found 3 publication records. Showing 3 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
62 | Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn |
Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. |
ICCAD |
1995 |
DBLP DOI BibTeX RDF |
acyclic pipelines, area-delay tradeoff, clock skew optimization, cycle-borrowing, logic design, combinational circuits, logic CAD, pipeline processing, circuit CAD, circuit optimisation, gate sizing, logic gates, pipelined circuits, timing specifications |
30 | Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn |
Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1998 |
DBLP DOI BibTeX RDF |
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26 | Glenn Jennings |
On cycle borrowing analyses for interconnected chips driven by clocks having different but commensurable speeds. |
ASAP |
1992 |
DBLP DOI BibTeX RDF |
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