Search results for "datapath"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
96	Mahmood Fazlali, Mohammad K. Fallah, Mahdy Zolghadr, Ali Zakerolhosseini	A New Datapath Merging Method for Reconfigurable System.	ARC	2009	DBLP DOI BibTeX RDF	Datapath Merging, Maximum Weighted Clique Algorithm, High Level Synthesis, Reconfigurable Computing
88	Reiner W. Hartenstein, Jürgen Becker 0001, Michael Herz, Rainer Kress 0002, Ulrich Nageldinger	A Synthesis System For Bus-Based Wavefront Array Architectures.	ASAP	1996	DBLP DOI BibTeX RDF	synthesis system, bus-based wavefront array architectures, datapath synthesis system, reconfigurable datapath architecture, internal data bus, automatic mapping, datapath units, high speed datapaths, parallel architectures, rapid prototyping, reconfigurable architectures, software prototyping, fine grained parallelism, data manipulations
87	Terry Tao Ye, Samit Chaudhuri, F. Huang, Hamid Savoj, Giovanni De Micheli	Physical synthesis for ASIC datapath circuits.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
79	Mehrdad Reshadi, Daniel Gajski	A cycle-accurate compilation algorithm for custom pipelined datapaths.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	NISC, cycle-accurate compiler, scheduling
78	Michalis D. Galanis, Gregory Dimitroulakos, Spyros Tragoudas, Costas E. Goutis	Speedups in embedded systems with a high-performance coprocessor datapath.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	coprocessor datapath, synthesis, kernels, Performance improvements, design flow, chaining
78	Andy Gean Ye, Jonathan Rose	Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits.	FPGA	2005	DBLP DOI BibTeX RDF	datapath regularity, reconfigurable fabric, FPGA architecture, routing architecture, area efficiency
70	Sabyasachi Das, Sunil P. Khatri	An efficient and regular routing methodology for datapath designsusing net regularity extraction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
70	Amit Chowdhary, Sudhakar Kale, Phani K. Saripella, Naresh Sehgal, Rajesh K. Gupta 0001	Extraction of functional regularity in datapath circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
69	Saraju P. Mohanty, N. Ranganathan	Energy-efficient datapath scheduling using multiple voltages and dynamic clocking.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	dynamic frequency clocking, low-power datapath synthesis, multiple voltage scheduling, time-constrained scheduling, High-level synthesis, resource-constrained scheduling
69	Mark C. Johnson, Kaushik Roy 0001	Datapath scheduling with multiple supply voltages and level converters.	ACM Trans. Design Autom. Electr. Syst.	1997	DBLP DOI BibTeX RDF	datapath scheduling, level conversion, scheduling, high-level synthesis, low power design, DSP, power optimization, multiple voltage
69	Zhining Huang, Sharad Malik, Nahri Moreano, Guido Araujo	The design of dynamically reconfigurable datapath coprocessors.	ACM Trans. Embed. Comput. Syst.	2004	DBLP DOI BibTeX RDF	coarse-grain reconfigurable fabric, reconfigurable datapath, Loop pipelining, interconnection design, datapath synthesis
61	Martin Thuresson, Magnus Själander, Magnus Björk, Lars J. Svensson, Per Larsson-Edefors, Per Stenström	FlexCore: Utilizing Exposed Datapath Control for Efficient Computing.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Reconfigurable, Computer architecture, Interconnect, Flexible
61	Martin Thuresson, Magnus Själander, Magnus Björk, Lars J. Svensson, Per Larsson-Edefors, Per Stenström	FlexCore: Utilizing Exposed Datapath Control for Efficient Computing.	ICSAMOS	2007	DBLP DOI BibTeX RDF
61	Andy Gean Ye, Jonathan Rose	Using Bus-Based Connections to Improve Field-Programmable Gate-Array Density for Implementing Datapath Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
61	Gilles Pokam, Olivier Rochecouste, André Seznec, François Bodin	Speculative software management of datapath-width for energy optimization.	LCTES	2004	DBLP DOI BibTeX RDF	narrow-width regions, compiler, reconfigurable computing, speculative execution, energy management, clock-gating
61	Guido Araujo, Sharad Malik, Zhining Huang, Nahri Moreano	Datapath Merging and Interconnection Sharing for Reconfigurable Architectures.	ISSS	2002	DBLP DOI BibTeX RDF	high level and architectural synthesis, reconfigurable computing
61	Dmitry V. Ponomarev, Gurhan Kucuk, Kanad Ghose	Dynamic Resizing of Superscalar Datapath Components for Energy Efficiency.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	energy-efficient datapath, Superscalar processor, power reduction, dynamic instruction scheduling
61	Jing-Ling Yang, Oliver Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun	Design for Self-Checking and Self-Timed Datapath.	VTS	2003	DBLP DOI BibTeX RDF	asynchronous datapath, differential cascode voltage switch logic, Self-checking, dynamic circuits
61	Yiorgos Makris, Jamison Collins, Alex Orailoglu	Fast Hierarchical Test Path Construction for Circuits with DFT-Free Controller-Datapath Interface.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	controller-datapath circuit, hierarchical test path, influence tables, transparency
61	Jing-Ling Yang, Oliver Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun	A Totally Self-Checking Dynamic Asynchronous Datapath.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF	Totally self-checking asynchronous datapath, differential cascade voltage switch logic, divider
53	Bita Gorjiara, Daniel D. Gajski	Custom Processor Design Using NISC: A Case-Study on DCT algorithm.	ESTIMedia	2005	DBLP DOI BibTeX RDF
53	Mehrdad Reshadi, Bita Gorjiara, Daniel D. Gajski	Utilizing Horizontal and Vertical Parallelism with a No-Instruction-Set Compiler for Custom Datapaths.	ICCD	2005	DBLP DOI BibTeX RDF
53	Jennifer Y.-L. Lo, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang	A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs.	DATE	2003	DBLP DOI BibTeX RDF
53	Mahadevamurty Nemani, Vivek Tiwari	Macro-driven circuit design methodology for high-performance datapaths.	DAC	2000	DBLP DOI BibTeX RDF
53	Steve C.-Y. Huang, Wayne H. Wolf	Unifiable scheduling and allocation for minimizing system cycle time.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
52	Magnus Själander, Per Larsson-Edefors, Magnus Björk	A Flexible Datapath Interconnect for Embedded Applications.	ISVLSI	2007	DBLP DOI BibTeX RDF
52	Brian G. VanBuren, Muhammad Shaaban	MicroTiger: a graphical microcode simulator with a reconfigurable datapath.	SIGCSE	2007	DBLP DOI BibTeX RDF	simulator, visualization, architecture, microcode
52	Nahri Moreano, Edson Borin, Cid C. de Souza, Guido Araujo	Efficient datapath merging for partially reconfigurable architectures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
52	Marcos R. Boschetti, Ivan Saraiva Silva, Sergio Bampi	A Run-Time Reconfigurable Datapath Architecture for Image Processing Applications.	DATE	2004	DBLP DOI BibTeX RDF
52	Maciej J. Ciesielski, Serkan Askar, Samuel Levitin	Analytical approach to layout generation of datapath cells.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
52	Leilei Song, Keshab K. Parhi, Ichiro Kuroda, Takao Nishitani	Hardware/software codesign of finite field datapath for low-energy Reed-Solomon codecs.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
52	Kyumyung Choi, Steven P. Levitan	A flexible datapath allocation method for architectural synthesis.	ACM Trans. Design Autom. Electr. Syst.	1999	DBLP DOI BibTeX RDF	allocation and binding, high-level synthesis
52	Samuel Norman Hamilton, Alex Orailoglu, Andre Hertwig	Self Recovering Controller and Datapath Codesign.	DATE	1999	DBLP DOI BibTeX RDF
52	István Erényi, István Vassányi, T. Nemes, É. Nikodemusz, Z. Katona	FPGA-based Automated Datapath Design.	EUROMICRO	1997	DBLP DOI BibTeX RDF
52	Nobu Matsumoto, Yoko Watanabe, Kimiyoshi Usami, Yukio Sugeno, Hiroshi Hatada, Shojiro Mori	Datapath Generator Based on Gate-Level Symbolic Layout.	DAC	1990	DBLP DOI BibTeX RDF
52	Eriko Nurvitadhi, James C. Hoe, Shih-Lien Lu, Timothy Kam	Automatic multithreaded pipeline synthesis from transactional datapath specifications.	DAC	2010	DBLP DOI BibTeX RDF	automatic pipelining, datapath specification, design exploration of x86 processor pipelines, multithreading, hardware synthesis
52	Süleyman Sirri Demirsoy, Martin Langhammer	Cholesky decomposition using fused datapath synthesis.	FPGA	2009	DBLP DOI BibTeX RDF	cholesky, fused datapath synthesis, fpga, floating-point
52	Koji Ohashi, Mineo Kaneko	Extended register-sharing in the synthesis of dual-rail two-phase asynchronous datapath.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	high-level synthesis, asynchronous circuit, datapath, register binding
52	Marco Lanuzza, Martin Margala, Pasquale Corsonello	Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications.	ISLPED	2005	DBLP DOI BibTeX RDF	reconfigurable computing, datapath, processor-in-memory
52	Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi	Simultaneous peak and average power minimization during datapath scheduling for DSP processors.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	average power, datapath scheduling, dynamic frequency clocking, high-level synthesis, peak power, multiple voltages
52	Dmitry Ponomarev 0001, Gurhan Kucuk, Kanad Ghose	Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources.	MICRO	2001	DBLP DOI BibTeX RDF	energy-efficient datapath, superscalar processor, power reduction, dynamic instruction scheduling
52	Yiorgos Makris, Jamison Collins, Alex Orailoglu	Fast hierarchical test path construction for DFT-free controller-datapath circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	fast hierarchical test path construction, DFT-free controller-datapath circuits, transparency based scheme, locally generated vectors, global design test, influence tables, valid control state sequences, module testing, fault coverage levels, vector counts, logic testing, test generation, automatic test pattern generation, ATPG, computational cost reduction
52	Hussain Al-Asaad, John P. Hayes, Brian T. Murray	Scalable Test Generators for High-Speed Datapath Circuits.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	datapath circuits, scalability, built-in self-test, test generation, on-line testing, carry lookahead
52	Andrew Wolfe, Jason Fritts, Santanu Dutta, Edil S. T. Fernandes	Datapath Design for a VLIW Video Signal Processor.	HPCA	1997	DBLP DOI BibTeX RDF	datapath design, VLIW video signal processor, very long instruction word, high parallelism, high-level language programmability, high-bandwidth interconnect, high-connectivity register files, parameterizable versions, VLSI, video signal processing, VLIW architectures, compiler design
44	Timothy J. Callahan, Philip Chong, André DeHon, John Wawrzynek	Fast Module Mapping and Placement for Datapaths in FPGAs.	FPGA	1998	DBLP DOI BibTeX RDF
44	Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi	ILP models for simultaneous energy and transient power minimization during behavioral synthesis.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	average power, cycle difference power, datapath scheduling, dynamic frequency clocking, multicycling, multiple supply voltages, peak power differential, Peak power
43	Subi Arumugam, Alin Dobra, Christopher M. Jermaine, Niketan Pansare, Luis Leopoldo Perez	The DataPath system: a data-centric analytic processing engine for large data warehouses.	SIGMOD Conference	2010	DBLP DOI BibTeX RDF	algorithms
43	Martin Langhammer	Floating point datapath synthesis for FPGAs.	FPL	2008	DBLP DOI BibTeX RDF
43	Peter A. Milder, Franz Franchetti, James C. Hoe, Markus Püschel	Formal datapath representation and manipulation for implementing DSP transforms.	DAC	2008	DBLP DOI BibTeX RDF	high-level synthesis, streaming, discrete Fourier transform, linear transform
43	Mazen A. R. Saghir, Mohamad El-Majzoub, Patrick Akl	Customizing the Datapath and ISA of Soft VLIW Processors.	HiPEAC	2007	DBLP DOI BibTeX RDF
43	Nilanjan Banerjee, Arijit Raychowdhury, Kaushik Roy 0001, Swarup Bhunia, Hamid Mahmoodi	Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
43	Petros Oikonomakos, Mark Zwolinski	On the Design of Self-Checking Controllers with Datapath Interactions.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	fault tolerance, Reliability, testing, automatic synthesis, error-checking, redundant design
43	Andrea Lodi 0002, Luca Ciccarelli, Claudio Mucci, Roberto Giansante, Andrea Cappelli, Mario Toma	An Embedded Reconfigurable Datapath for SoC.	FCCM	2005	DBLP DOI BibTeX RDF
43	Nilanjan Banerjee, Arijit Raychowdhury, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy 0001	Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis.	ICCD	2005	DBLP DOI BibTeX RDF
43	Koji Ohashi, Mineo Kaneko	Statistical schedule length analysis in asynchronous datapath synthesis.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
43	Yiorgos Makris, Ismet Bayraktaroglu, Alex Orailoglu	Enhancing reliability of RTL controller-datapath circuits via Invariant-based concurrent test.	IEEE Trans. Reliab.	2004	DBLP DOI BibTeX RDF
43	Jing-Ling Yang, Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun	A high-efficiency strongly self-checking asynchronous datapath.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
43	Fang Fang, Jianwen Zhu	Automatic process migration of datapath hard IP libraries.	ASP-DAC	2004	DBLP DOI BibTeX RDF
43	Ju-Ho Sohn, Ramchan Woo, Hoi-Jun Yoo	A programmable vertex shader with fixed-point SIMD datapath for low power wireless applications.	Graphics Hardware	2004	DBLP DOI BibTeX RDF
43	Sunwoong Yang, MoonJoon Kim, JaeHeung Park, Hoon Chang	A Study on Methodology for Enhancing Reliability of Datapath.	ICCSA (1)	2004	DBLP DOI BibTeX RDF
43	Katarzyna Leijten-Nowak, Jef L. van Meerbergen	An FPGA architecture with enhanced datapath functionality.	FPGA	2003	DBLP DOI BibTeX RDF	adder inverting property, application-domain tuning, logic block architectures, FPGAs, DSP, symmetry
43	Jürgen Becker 0001, Alexander Thomas, Maik Scheer	Efficient Processor Instruction Set Extension by Asynchronous Reconfigurable Datapath Integration.	SBCCI	2003	DBLP DOI BibTeX RDF
43	Mineo Kaneko, Kazuaki Oshio	Fault tolerant datapath based on algorithm redundancy and vote-writeback mechanism.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
43	Alex Talpasanu, G. Milford, K. S. A. Miles, Jeffrey A. Davis	Computer Educational Datapath (CED): Basic Computer Design for K-12 Education.	ITCC	2003	DBLP DOI BibTeX RDF
43	Nagisa Ishiura, Tatsuo Watanabe	Datapath oriented codesign method of application specific DSPs using retargetable compiler.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
43	Yiorgos Makris, Ismet Bayraktaroglu, Alex Orailoglu	Invariance-Based On-Line Test for RTL Controller-Datapath Circuits.	VTS	2000	DBLP DOI BibTeX RDF
43	Santanu Dutta, Wayne H. Wolf	A circuit-driven design methodology for video signal-processing datapath elements.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
43	Joan Carletta, Mehrdad Nourani, Christos A. Papachristou	Synthesis of Controllers for Full Testability of Integrated Datapath-Controller Pairs.	DATE	1999	DBLP DOI BibTeX RDF
43	Leilei Song, Keshab K. Parhi	Low-energy software Reed-Solomon codecs using specialized finite field datapath and division-free Berlekamp-Massey algorithm.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
43	Gila Kamhi, Osnat Weissberg, Limor Fix	Automatic Datapath Extraction for Efficient Usage of HDD.	CAV	1997	DBLP DOI BibTeX RDF
43	Steve C.-Y. Huang, Wayne H. Wolf	Performance-driven synthesis in controller-datapath systems.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
43	Tom Marshburn, Ivy Lui, Rick Brown, Dan Cheung, Gary Lum, Peter Cheng	DATAPATH: a CMOS data path silicon assembler.	DAC	1986	DBLP DOI BibTeX RDF
43	Tay-Jyi Lin, Pi-Chen Hsiao, Chi-Hung Lin, Shu-Chang Kuo, Chou-Kun Lin, Yu-Ting Kuo, Chih-Wei Liu, Yuan-Hua Chu	Collaborative voltage scaling with online STA and variable-latency datapath.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	collaborative voltage scaling, online STA, variable-latency datapath, adaptive voltage scaling
43	Omid Sarbishei, Bijan Alizadeh, Masahiro Fujita	Polynomial datapath optimization using partitioning and compensation heuristics.	DAC	2009	DBLP DOI BibTeX RDF	modular HED, polynomial datapath, high-level synthesis
43	Steven J. E. Wilton, Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Bradley R. Quinton	A synthesizable datapath-oriented embedded FPGA fabric.	FPGA	2007	DBLP DOI BibTeX RDF	embedded block, field programmable gate array, system-on-chip, synthesis, integrated circuit, datapath
35	Takeshi Sugawara 0001, Naofumi Homma, Takafumi Aoki, Akashi Satoh	Compact ASIC Architectures for the 512-Bit Hash Function Whirlpool.	WISA	2008	DBLP DOI BibTeX RDF	Hash function, Hardware architecture, Whirlpool, Cryptographic hardware
35	Sabyasachi Das, Sunil P. Khatri	A Merged Synthesis Technique for Fast Arithmetic Blocks Involving Sum-of-Products and Shifters.	VLSI Design	2008	DBLP DOI BibTeX RDF
35	Loganathan Lingappan, Vijay Gangaram, Niraj K. Jha	Fast Enhancement of Validation Test Sets to Improve Stuck-at Fault Coverage for RTL circuits.	VLSI Design	2007	DBLP DOI BibTeX RDF
35	William B. Toms, David A. Edwards, Andrew Bardsley	Synthesising Heterogeneously Encoded Systems.	ASYNC	2006	DBLP DOI BibTeX RDF
35	Anand Raghunathan, Sujit Dey, Niraj K. Jha	High-level macro-modeling and estimation techniques for switching activity and power consumption.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
35	Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Hyun Suk Kim, Wu Ye, David Duarte	Evaluating Integrated Hardware-Software Optimizations Using a Unified Energy Estimation Framework.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	simulation, optimizations, energy models, Energy estimation
35	Chung-Yang Huang, Kwang-Ting Cheng	Using word-level ATPG and modular arithmetic constraint-solvingtechniques for assertion property checking.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
35	Mehrdad Nourani, Joan Carletta, Christos A. Papachristou	Integrated test of interacting controllers and datapaths.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	built-in self-test, register transfer level, synthesis-for-testability
35	Chung-Yang Huang, Kwang-Ting Cheng	Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques.	DAC	2000	DBLP DOI BibTeX RDF
35	David Knapp	An Interactive Tool for Register-level Structure Optimization.	DAC	1989	DBLP DOI BibTeX RDF
35	Markus Püschel, Peter A. Milder, James C. Hoe	Permuting streaming data using RAMs.	J. ACM	2009	DBLP DOI BibTeX RDF	data reordering, linear bit mapping, streaming datapath, stride permutation, Permutation, switch, RAM, connection network, matrix transposition
35	Yee Jern Chong, Sri Parameswaran	Rapid application specific floating-point unit generation with bit-alignment.	DAC	2008	DBLP DOI BibTeX RDF	bit-alignment, datapath merging, floating-point
35	Ki-Bog Kim, Chi-Ho Lin	An Optimal ILP Model for Delay Time to Minimize Peak Power and Area.	IWSOC	2005	DBLP DOI BibTeX RDF	B&B, scheduling, Pipelined, ILP, area, peak-power, datapath
34	Steven J. E. Wilton, Chun Hok Ho, Bradley R. Quinton, Philip Heng Wai Leong, Wayne Luk	A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications.	ACM Trans. Reconfigurable Technol. Syst.	2008	DBLP DOI BibTeX RDF	Field programmable gate array, system-on-chip, integrated circuit, silicon debug
34	Laura Frigerio, Fabio Salice	A performance-oriented hardware/software partitioning for datapath applications.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	hardware/software systems, performance oriented patitioning
34	Steffen Köhler, Jan Schirok, Jens Braunes, Rainer G. Spallek	Efficiency of Dynamic Reconfigurable Datapath Extensions -- A Case Study.	ARC	2008	DBLP DOI BibTeX RDF
34	Rajaraman Ramanarayanan, Sanu Mathew, Vasantha Erraguntla, Ram Krishnamurthy 0001, Shay Gueron	A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm High-Performance Microprocessor Execution Cores.	VLSI Design	2008	DBLP DOI BibTeX RDF
34	Vijay Sundaresan, Ranga Vemuri	A Novel Approach to Performance-Oriented Datapath Allocation and Floorplanning.	ISVLSI	2006	DBLP DOI BibTeX RDF
34	Akira Mochizuki, Takeshi Kitamura, Hirokatsu Shirahama, Takahiro Hanyu	Design of a Microprocessor Datapath Using Four-Valued Differential-Pair Circuits.	ISMVL	2006	DBLP DOI BibTeX RDF
34	Kaijie Wu 0001, Ramesh Karri	Fault secure datapath synthesis using hybrid time and hardware redundancy.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
34	Jiang Chau Wang, Paulo Sérgio Cardoso, Jose Artur Quilici González, Marius Strum, Ricardo Pires	Datapath BIST Insertion Using Pre-Characterized Area and Testability Data.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	test library, RTL architecture, pre-computed testability, self-test
34	Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi	Peak Power Minimization Through Datapath Scheduling.	ISVLSI	2003	DBLP DOI BibTeX RDF
34	Yee William Li, George Patounakis, Anup P. Jose, Kenneth L. Shepard, Steven M. Nowick	Asynchronous Datapath with Software-Controlled On-Chip Adaptive Voltage Scaling for Multirate Signal Processing Application.	ASYNC	2003	DBLP DOI BibTeX RDF
34	Kaijie Wu 0001, Ramesh Karri	Register Transfer Level Approach to Hybrid Time and Hardware Redundancy Based Fault Secure Datapath Synthesis.	ITC	2003	DBLP DOI BibTeX RDF
34	Saraju P. Mohanty, N. Ranganathan, Vamsi Krishna	Datapath Scheduling using Dynamic Frequency Clocking.	ISVLSI	2002	DBLP DOI BibTeX RDF