Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
96 | Sivaram Gopalakrishnan, Priyank Kalla |
Optimization of polynomial datapaths using finite ring algebra. |
ACM Trans. Design Autom. Electr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
arithmetic datapaths, finite ring algebra, modulo arithmetic, polynomial datapaths, High-level synthesis |
58 | Sivaram Gopalakrishnan, Priyank Kalla, Florian Enescu |
Optimization of Arithmetic Datapaths with Finite Word-Length Operands. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
arithmetic datapaths, finite word length, operands, polynomial computations, finite integer rings, CAD, area optimization, bit vectors |
57 | Masahiro Fujita |
Behavior-RTL Equivalence Checking Based on Data Transfer Analysis with Virtual Controllers and Datapaths. |
CHARME |
2005 |
DBLP DOI BibTeX RDF |
|
50 | Seokjin Kim, Ramalingam Sridhar |
A local clocking approach for self-timed datapath designs. |
Great Lakes Symposium on VLSI |
1995 |
DBLP DOI BibTeX RDF |
self-timed datapath designs, local clock control circuit, synchronous datapaths, asynchronous environment, locally-clocked multiplier, asynchronous system implementation, timing, logic design, logic design, digital arithmetic, asynchronous circuits, multiplying circuits |
49 | Sabyasachi Das, Sunil P. Khatri |
An efficient and regular routing methodology for datapath designsusing net regularity extraction. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
45 | Wei-Sheng Huang, Tay-Jyi Lin, Shih-Hao Ou, Chih-Wei Liu, Chein-Wei Jen |
Pipelining technique for energy-aware datapaths. |
ISCAS (2) |
2005 |
DBLP DOI BibTeX RDF |
|
45 | Dmitry V. Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose |
Energy Efficient Comparators for Superscalar Datapaths. |
IEEE Trans. Computers |
2004 |
DBLP DOI BibTeX RDF |
|
45 | Michiko Inoue, Kazuhiro Suzuki, Hiroyuki Okamoto, Hideo Fujiwara |
Test Synthesis for Datapaths Using Datapath-Controller Functions. |
Asian Test Symposium |
2003 |
DBLP DOI BibTeX RDF |
hierarchical test generation, non-scan design, design-for-testability, at-speed testing, RTL circuit |
45 | Mehrdad Nourani, Joan Carletta, Christos A. Papachristou |
Integrated test of interacting controllers and datapaths. |
ACM Trans. Design Autom. Electr. Syst. |
2001 |
DBLP DOI BibTeX RDF |
built-in self-test, register transfer level, synthesis-for-testability |
45 | Laurence Goodby, Alex Orailoglu |
Redundancy and testability in digital filter datapaths. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1999 |
DBLP DOI BibTeX RDF |
|
45 | Margarida F. Jacome, Gustavo de Veciana |
Lower bound on latency for VLIW ASIP datapaths. |
ICCAD |
1999 |
DBLP DOI BibTeX RDF |
|
37 | Viktor S. Lapinskii, Margarida F. Jacome, Gustavo de Veciana |
Cluster assignment for high-performance embedded VLIW processors. |
ACM Trans. Design Autom. Electr. Syst. |
2002 |
DBLP DOI BibTeX RDF |
Operation binding, clustered VLIW datapaths, embedded systems, partitioning, embedded processors |
37 | Reiner W. Hartenstein, Jürgen Becker 0001, Michael Herz, Rainer Kress 0002, Ulrich Nageldinger |
A Synthesis System For Bus-Based Wavefront Array Architectures. |
ASAP |
1996 |
DBLP DOI BibTeX RDF |
synthesis system, bus-based wavefront array architectures, datapath synthesis system, reconfigurable datapath architecture, internal data bus, automatic mapping, datapath units, high speed datapaths, parallel architectures, rapid prototyping, reconfigurable architectures, software prototyping, fine grained parallelism, data manipulations |
37 | Seong Yong Ohm, Fadi J. Kurdahi, Nikil D. Dutt, Min Xu |
A comprehensive estimation technique for high-level synthesis. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
HLS benchmarks, RT level components, RTL datapaths, estimation technique, delays, high level synthesis, high-level synthesis, timing, design space exploration, granularity, hardware description languages, data flow graphs, registers, system buses, timing model, buses, behavioral description, layout area |
37 | Wei Zhao, Christos A. Papachristou |
Architectural partitioning of control memory for application specific programmable processors. |
ICCAD |
1995 |
DBLP DOI BibTeX RDF |
application specific programmable processors, control memory, distributed microcode memory model, microcode memory, repetitive microcodes, distributed memory systems, memory architecture, programmability, microprogram, datapaths, firmware, memory module |
37 | Je-Hoon Lee, Seung-Sook Lee, Kyoung-Rok Cho |
Asynchronous ARM Processor Employing an Adaptive Pipeline Architecture. |
ARC |
2007 |
DBLP DOI BibTeX RDF |
adaptive pipeline, processor, Asynchronous design |
37 | Liang Han, Jie Chen 0012, Chaoxian Zhou, Ying Li, Xin Zhang, Zhibi Liu, Xiaoyun Wei, Baofeng Li |
An Embedded Reconfigurable SIMD DSP with Capability of Dimension-Controllable Vector Processing. |
ICCD |
2004 |
DBLP DOI BibTeX RDF |
|
37 | Tay-Jyi Lin, Chein-Wei Jen |
CASCADE - configurable and scalable DSP environment. |
ISCAS (4) |
2002 |
DBLP DOI BibTeX RDF |
|
33 | Namrata Shekhar, Priyank Kalla, M. Brandon Meredith, Florian Enescu |
Simulation Bounds for Equivalence Verification of Polynomial Datapaths Using Finite Ring Algebra. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
33 | Neal Tew, Priyank Kalla, Namrata Shekhar, Sivaram Gopalakrishnan |
Verification of arithmetic datapaths using polynomial function models and congruence solving. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
|
33 | Namrata Shekhar, Sudhakar Kalla, Florian Enescu |
Equivalence Verification of Polynomial Datapaths Using Ideal Membership Testing. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
33 | Vyas Krishnan, Srinivas Katkoori |
A genetic algorithm for the design space exploration of datapaths during high-level synthesis. |
IEEE Trans. Evol. Comput. |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Namrata Shekhar, Priyank Kalla, Florian Enescu |
Equivalence verification of arithmetic datapaths with multiple word-length operands. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Namrata Shekhar, Priyank Kalla, M. Brandon Meredith, Florian Enescu |
Simulation Bounds for Equivalence Verification of Arithmetic Datapaths with Finite Word-Length Operands. |
FMCAD |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Masahiro Fujita |
Equivalence checking between behavioral and RTL descriptions with virtual controllers and datapaths. |
ACM Trans. Design Autom. Electr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
formal verification, High-level synthesis, equivalence checking, behavior synthesis |
33 | Ranganath Gopalan, Chandramouli Gopalakrishnan, Srinivas Katkoori |
Leakage Power Driven Behavioral Synthesis of Pipelined Datapaths. |
ISVLSI |
2005 |
DBLP DOI BibTeX RDF |
|
33 | Manjunath Kudlur, Kevin Fan, Michael L. Chu, Rajiv A. Ravindran, Nathan Clark, Scott A. Mahlke |
FLASH: Foresighted Latency-Aware Scheduling Heuristic for Processors with Customized Datapaths. |
CGO |
2004 |
DBLP DOI BibTeX RDF |
|
33 | Chandramouli Gopalakrishnan, Srinivas Katkoori |
An Architectural Leakage Power Simulator for VHDL Structural Datapaths. |
ISVLSI |
2003 |
DBLP DOI BibTeX RDF |
|
33 | Chandramouli Gopalakrishnan, Srinivas Katkoori |
KnapBind: An Area-Efficient Binding Algorithm for Low-leakage Datapaths. |
ICCD |
2003 |
DBLP DOI BibTeX RDF |
|
33 | Viktor S. Lapinskii, Margarida F. Jacome, Gustavo de Veciana |
Application-specific clustered VLIW datapaths: early exploration on a parameterized design space. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
33 | Katarzyna Radecka, Zeljko Zilic |
Specifying and verifying imprecise sequential datapaths by Arithmetic Transforms. |
ICCAD |
2002 |
DBLP DOI BibTeX RDF |
|
33 | Chandramouli Gopalakrishnan, Srinivas Katkoori |
Behavioral synthesis of datapaths with low leakage power. |
ISCAS (4) |
2002 |
DBLP DOI BibTeX RDF |
|
33 | Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Mihalis Psarakis, Yervant Zorian |
An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths. |
J. Electron. Test. |
2001 |
DBLP DOI BibTeX RDF |
datapath test, shifter, Built-in self-test, accumulator, arithmetic-logic unit, processor test |
33 | Nektarios Kranitis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian |
An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths. |
ISQED |
2001 |
DBLP DOI BibTeX RDF |
|
33 | Montek Singh, Steven M. Nowick |
High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic Datapaths. |
ASYNC |
2000 |
DBLP DOI BibTeX RDF |
fine-grain pipelining, VLSI, pipelines, asynchronous, dynamic logic, FIFO, high-throughput, digital design |
33 | Mahadevamurty Nemani, Vivek Tiwari |
Macro-driven circuit design methodology for high-performance datapaths. |
DAC |
2000 |
DBLP DOI BibTeX RDF |
|
33 | David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre |
BISTing Datapaths under Heterogeneous Test Schemes. |
J. Electron. Test. |
1999 |
DBLP DOI BibTeX RDF |
RT level, BIST, datapath, test synthesis |
33 | Darren C. Cronquist, Chris Fisher, Miguel E. Figueroa, Paul Franklin, Carl Ebeling |
Architecture Design of Reconfigurable Pipelined Datapaths. |
ARVLSI |
1999 |
DBLP DOI BibTeX RDF |
High-speed computation, Pipelining, Signal processing, Reconfigurable architectures, Configurable computing |
33 | Marie-Lise Flottes, R. Pires, Bruno Rouzeyre, Laurent Volpe |
Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
Scan chain selection, RT and gate levels, Partial scan, Synthesis for testability |
33 | Saman Adham, Sanjay Gupta |
DP-BIST: A Built-In Self Test For DSP DataPaths A Low Overhead and High Fault Coverage Technique. |
Asian Test Symposium |
1996 |
DBLP DOI BibTeX RDF |
|
33 | Baher Haroun, Behzad Sajjadi |
Synthesis of Signal Processing Structured Datapaths for FPGAs Supporting RAMs and Busses. |
FPGA |
1995 |
DBLP DOI BibTeX RDF |
|
25 | Juan Carlos López 0001, Fernando Rincón, Francisco Moya, José Manuel Moya |
Improving Embedded System Design by Means of HW-SW Compilation on Reconfigurable Coprocessors. |
ISSS |
2002 |
DBLP DOI BibTeX RDF |
reconfigurable datapaths, hardware-software codesign |
25 | H. Fatih Ugurdag, Thomas E. Fuhrman |
Autocircuit: a clock edge general behavioral synthesis system with a direct path to physical datapath. |
ICCD |
1996 |
DBLP DOI BibTeX RDF |
Autocircuit, clock edge general behavioral synthesis system, physical datapaths, next-generation synthesis tool, behavioral HDL input descriptions, data-flow representations, use-trees, raw-states, word-oriented synthesis, unique parameterized netlist representation, high level synthesis, high-level design |
24 | Yedidya Hilewitz, Ruby B. Lee |
Fast Bit Gather, Bit Scatter and Bit Permutation Instructions for Commodity Microprocessors. |
J. Signal Process. Syst. |
2008 |
DBLP DOI BibTeX RDF |
Bit scatter, Bit gather, Parallel deposit, Unpack, Algorithm acceleration, Bioinformatics, Compression, Pattern matching, Steganography, Microprocessors, Permutations, Pack, Instruction set architecture, Cryptology, ISA, Parallel extract, Bit manipulations |
24 | Omkar Dandekar, William Plishker, Shuvra S. Bhattacharyya, Raj Shekhar |
Multiobjective Optimization of FPGA-Based Medical Image Registration. |
FCCM |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Yee Jern Chong, Sri Parameswaran |
Rapid application specific floating-point unit generation with bit-alignment. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
bit-alignment, datapath merging, floating-point |
24 | Peter A. Milder, Franz Franchetti, James C. Hoe, Markus Püschel |
Formal datapath representation and manipulation for implementing DSP transforms. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
high-level synthesis, streaming, discrete Fourier transform, linear transform |
24 | Harmander Singh, Kanak Agarwal, Dennis Sylvester, Kevin J. Nowka |
Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating. |
IEEE Trans. Very Large Scale Integr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Sotirios Xydis, George Economakos, Kiamal Z. Pekmestzi |
Flexibility Inlining into Arithmetic Data-paths Exploiting A Regular Interconnection Scheme. |
ICSAMOS |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Kristopher D. Peterson, Justin L. Tripp |
Effective Automatic Memory Allocation Algorithm Based on Schedule Length in Cycles in a Novel C to FPGA Compiler. |
FPL |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Kaushal R. Gandhi, Nihar R. Mahapatra |
Exploiting data-dependent slack using dynamic multi-VDD to minimize energy consumption in datapath circuits. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
24 | William B. Toms, David A. Edwards, Andrew Bardsley |
Synthesising Heterogeneously Encoded Systems. |
ASYNC |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Xun Liu, Marios C. Papaefthymiou |
HyPE: hybrid power estimation for IP-based systems-on-chip. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
24 | Nahri Moreano, Edson Borin, Cid C. de Souza, Guido Araujo |
Efficient datapath merging for partially reconfigurable architectures. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
24 | Abdelhalim Alsharqawi, Abdel Ejnioui |
Synthesis of Self-Resetting Stage Logic Pipelines. |
ISVLSI |
2005 |
DBLP DOI BibTeX RDF |
|
24 | Dara Kusic, Raymond Hoare, Alex K. Jones, Joshua Fazekas, John Foster 0001 |
Extracting Speedup From C-Code With Poor Instruction-Level Parallelism. |
IPDPS |
2005 |
DBLP DOI BibTeX RDF |
|
24 | Philip Brisk, Adam Kaplan, Majid Sarrafzadeh |
Area-efficient instruction set synthesis for reconfigurable system-on-chip designs. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
field-programmable gate array (FPGA), compiler, resource sharing, integer linear programming (ILP) |
24 | Jürgen Becker 0001, Alexander Thomas, Maik Scheer |
Efficient Processor Instruction Set Extension by Asynchronous Reconfigurable Datapath Integration. |
SBCCI |
2003 |
DBLP DOI BibTeX RDF |
|
24 | Amitabh Menon, S. K. Nandy 0001, Mahesh Mehendale |
Multivoltage scheduling with voltage-partitioned variable storage. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
multivoltage, high level synthesis, datapath synthesis |
24 | Recep O. Ozdag, Peter A. Beerel, Montek Singh, Steven M. Nowick |
High-Speed Non-Linear Asynchronous Pipelines. |
DATE |
2002 |
DBLP DOI BibTeX RDF |
|
24 | María C. Molina, José M. Mendías, Román Hermida |
Bit-level scheduling of heterogeneous behavioural specifications. |
ICCAD |
2002 |
DBLP DOI BibTeX RDF |
|
24 | Leilei Song, Keshab K. Parhi, Ichiro Kuroda, Takao Nishitani |
Hardware/software codesign of finite field datapath for low-energy Reed-Solomon codecs. |
IEEE Trans. Very Large Scale Integr. Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
24 | Joan Carletta, Christos A. Papachristou, Mehrdad Nourani |
Detecting Undetectable Controller Faults Using Power Analysis. |
DATE |
2000 |
DBLP DOI BibTeX RDF |
|
24 | Kenneth Y. Yun |
Recent Advances in Asynchronous Design Methodologies. |
ASP-DAC |
1999 |
DBLP DOI BibTeX RDF |
|
24 | Mehrdad Nourani, Joan Carletta, Christos A. Papachristou |
A Scheme for Integrated Controller-Datapath Fault Testing. |
DAC |
1997 |
DBLP DOI BibTeX RDF |
|
24 | Hong-Shin Jun, Sun-Young Hwang |
Design of a pipelined datapath synthesis system for digital signal processing. |
IEEE Trans. Very Large Scale Integr. Syst. |
1994 |
DBLP DOI BibTeX RDF |
|
21 | Yongqiang Zhang 0006, Siting Liu 0001, Jie Han 0001, Zhendong Lin, Shaowei Wang, Xin Cheng 0001, Guangjun Xie |
An Energy-Efficient Binary-Interfaced Stochastic Multiplier Using Parallel Datapaths. |
IEEE Trans. Very Large Scale Integr. Syst. |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Tomasz Osinski, Halina Tarasiuk |
New approaches to data plane programmability for software datapaths in the NFV infrastructure. |
NetSoft |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Nusa Zidaric, Mark D. Aagaard |
Tower field support for synthesis of datapaths. |
CF |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Ahsen Ejaz, Ioannis Sourdis |
FastTrackNoC: A NoC with FastTrack Router Datapaths. |
HPCA |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Samira Ait Bensaid, Mihail Asavoae, Farhat Thabet, Mathieu Jan |
Work in Progress: Automatic Construction of Pipeline Datapaths from High-Level HDL Code. |
RTAS |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Daniel Vázquez, Alfonso Rodríguez 0002, Andrés Otero, Eduardo de la Torre |
Extending RISC-V Processor Datapaths with Multi-Grain Reconfigurable Overlays. |
DCIS |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Yoshiya Shikama, Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto, Michihiro Koibuchi |
Low-Latency Low-Energy Memory-Cube Networks using Dual-Voltage Datapaths. |
PDP |
2021 |
DBLP DOI BibTeX RDF |
|
21 | Inbal Stanger, Netanel Shavit, Ramiro Taco, Marco Lanuzza, Alexander Fish |
Live Demo: Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths. |
ISCAS |
2021 |
DBLP DOI BibTeX RDF |
|
21 | Yiming Qiu, Hongyi Liu, Thomas E. Anderson, Yingyan Lin, Ang Chen 0001 |
Toward reconfigurable kernel datapaths with learned optimizations. |
HotOS |
2021 |
DBLP DOI BibTeX RDF |
|
21 | Philip Rohde |
Merging Datapaths using Data Processing Graphs. |
|
2021 |
RDF |
|
21 | Mohammad Reza Esmaeili, Seyed Hamid Zahiri, Seyed Mohammad Razavi |
A novel method for high-level synthesis of datapaths in digital filters using a moth-flame optimization algorithm. |
Evol. Intell. |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Inbal Stanger, Netanel Shavit, Ramiro Taco, Marco Lanuzza, Alexander Fish |
Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths. |
IEEE Trans. Circuits Syst. II Express Briefs |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Vasileios Kokkinos, Athanasios Kakarountas |
Design of Reconfigurable Fault-Tolerant Datapaths. |
SEEDA-CECNSM |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Loris Duch, Soumya Basu 0002, Miguel Peón Quirós, Giovanni Ansaloni, Laura Pozzi, David Atienza |
i-DPs CGRA: An Interleaved-Datapaths Reconfigurable Accelerator for Embedded Bio-Signal Processing. |
IEEE Embed. Syst. Lett. |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Keith A. Campbell, Chen-Hsuan Lin, Deming Chen |
Cost-Effective Error Detection Through Mersenne Modulo Shadow Datapaths. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Alberto A. Del Barrio, Román Hermida, Seda Ogrenci Memik |
A Combined Arithmetic-High-Level Synthesis Solution to Deploy Partial Carry-Save Radix-8 Booth Multipliers in Datapaths. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Alexander J. Groszewski, Travis Lenz |
Deterministic Stochastic Computation Using Parallel Datapaths. |
ISQED |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Paul Chaignon |
Software Datapaths for Multi-Tenant Packet Processing. (Plans de données logiciels pour les traitements réseaux en environnements partagés). |
|
2019 |
RDF |
|
21 | Arman Roohi, Ronald F. DeMara |
NV-Clustering: Normally-Off Computing Using Non-Volatile Datapaths. |
IEEE Trans. Computers |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Sana Mazahir, Osman Hasan, Muhammad Shafique 0001 |
Adaptive Approximate Computing in Arithmetic Datapaths. |
IEEE Des. Test |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Bruno Miguel Gil Rosa, Henry M. D. Ip, Guang-Zhong Yang |
Wireless Datapaths and Security. |
Implantable Sensors and Systems |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Mohammad Saber Golanbari, Mehdi Baradaran Tahoori |
Optimizing Datapaths for Near Threshold Computing. |
SMACD |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Christopher Leet, Xin Wang, Yang Richard Yang, James Aspnes |
Toward the First SDN Programming Capacity Theorem on Realizing High-Level Programs on Low-Level Datapaths. |
INFOCOM |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Sheikh Ariful Islam, Srinivas Katkoori |
High-level synthesis of key based obfuscated RTL datapaths. |
ISQED |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Amir Sabbagh Molahosseini, Azadeh Alsadat Emrani Zarandi, Paulo Martins 0002, Leonel Sousa |
A Multifunctional Unit for Designing Efficient RNS-Based Datapaths. |
IEEE Access |
2017 |
DBLP DOI BibTeX RDF |
|
21 | Matei Istoan, Florent de Dinechin |
Automating the pipeline of arithmetic datapaths. |
DATE |
2017 |
DBLP DOI BibTeX RDF |
|
21 | Philip Gottschling, Christian Hochberger |
ReEP: A Toolset for Generation and Programming of Reconfigurable Datapaths for Event Processing. |
IPDPS Workshops |
2017 |
DBLP DOI BibTeX RDF |
|
21 | Aurojit Panda, Ori Lahav 0001, Katerina J. Argyraki, Mooly Sagiv, Scott Shenker |
Verifying Reachability in Networks with Mutable Datapaths. |
NSDI |
2017 |
DBLP BibTeX RDF |
|
21 | Aurojit Panda, Ori Lahav 0001, Katerina J. Argyraki, Mooly Sagiv, Scott Shenker |
Verifying Reachability in Networks with Mutable Datapaths. |
CoRR |
2016 |
DBLP BibTeX RDF |
|
21 | Rei Ueno, Sumio Morioka, Naofumi Homma, Takafumi Aoki |
A High Throughput/Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths - Toward Efficient CBC-Mode Implementation. |
IACR Cryptol. ePrint Arch. |
2016 |
DBLP BibTeX RDF |
|
21 | Donghai Li, Xiaochen Zhu, Zhonglei Fan, Xiaojun Yang |
多项式数据通路的优化方法 (Method of Optimization for Polynomial Datapaths). |
计算机科学 |
2016 |
DBLP DOI BibTeX RDF |
|
21 | Xiaobo Yin, Feng Yu 0003, Zhen-guo Ma |
Resource-Efficient Pipelined Architectures for Radix-2 Real-Valued FFT With Real Datapaths. |
IEEE Trans. Circuits Syst. II Express Briefs |
2016 |
DBLP DOI BibTeX RDF |
|
21 | Nachiket Kapre, Deheng Ye |
GPU-Accelerated High-Level Synthesis for Bitwidth Optimization of FPGA Datapaths. |
FPGA |
2016 |
DBLP DOI BibTeX RDF |
|
21 | Rei Ueno, Sumio Morioka, Naofumi Homma, Takafumi Aoki |
A High Throughput/Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths - Toward Efficient CBC-Mode Implementation. |
CHES |
2016 |
DBLP DOI BibTeX RDF |
|