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Publication years (Num. hits)
1989-1995 (21) 1996-1997 (25) 1998-1999 (22) 2000-2001 (21) 2002 (21) 2003 (21) 2004 (17) 2005 (25) 2006 (25) 2007 (25) 2008 (21) 2009-2010 (17) 2011-2012 (18) 2013-2015 (16) 2016-2018 (18) 2019-2022 (15) 2023 (3)
Publication types (Num. hits)
article(80) incollection(1) inproceedings(245) phdthesis(5)
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Found 331 publication records. Showing 331 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
96Sivaram Gopalakrishnan, Priyank Kalla Optimization of polynomial datapaths using finite ring algebra. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF arithmetic datapaths, finite ring algebra, modulo arithmetic, polynomial datapaths, High-level synthesis
58Sivaram Gopalakrishnan, Priyank Kalla, Florian Enescu Optimization of Arithmetic Datapaths with Finite Word-Length Operands. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF arithmetic datapaths, finite word length, operands, polynomial computations, finite integer rings, CAD, area optimization, bit vectors
57Masahiro Fujita Behavior-RTL Equivalence Checking Based on Data Transfer Analysis with Virtual Controllers and Datapaths. Search on Bibsonomy CHARME The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
50Seokjin Kim, Ramalingam Sridhar A local clocking approach for self-timed datapath designs. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF self-timed datapath designs, local clock control circuit, synchronous datapaths, asynchronous environment, locally-clocked multiplier, asynchronous system implementation, timing, logic design, logic design, digital arithmetic, asynchronous circuits, multiplying circuits
49Sabyasachi Das, Sunil P. Khatri An efficient and regular routing methodology for datapath designsusing net regularity extraction. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
45Wei-Sheng Huang, Tay-Jyi Lin, Shih-Hao Ou, Chih-Wei Liu, Chein-Wei Jen Pipelining technique for energy-aware datapaths. Search on Bibsonomy ISCAS (2) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
45Dmitry V. Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose Energy Efficient Comparators for Superscalar Datapaths. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
45Michiko Inoue, Kazuhiro Suzuki, Hiroyuki Okamoto, Hideo Fujiwara Test Synthesis for Datapaths Using Datapath-Controller Functions. Search on Bibsonomy Asian Test Symposium The full citation details ... 2003 DBLP  DOI  BibTeX  RDF hierarchical test generation, non-scan design, design-for-testability, at-speed testing, RTL circuit
45Mehrdad Nourani, Joan Carletta, Christos A. Papachristou Integrated test of interacting controllers and datapaths. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF built-in self-test, register transfer level, synthesis-for-testability
45Laurence Goodby, Alex Orailoglu Redundancy and testability in digital filter datapaths. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
45Margarida F. Jacome, Gustavo de Veciana Lower bound on latency for VLIW ASIP datapaths. Search on Bibsonomy ICCAD The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
37Viktor S. Lapinskii, Margarida F. Jacome, Gustavo de Veciana Cluster assignment for high-performance embedded VLIW processors. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Operation binding, clustered VLIW datapaths, embedded systems, partitioning, embedded processors
37Reiner W. Hartenstein, Jürgen Becker 0001, Michael Herz, Rainer Kress 0002, Ulrich Nageldinger A Synthesis System For Bus-Based Wavefront Array Architectures. Search on Bibsonomy ASAP The full citation details ... 1996 DBLP  DOI  BibTeX  RDF synthesis system, bus-based wavefront array architectures, datapath synthesis system, reconfigurable datapath architecture, internal data bus, automatic mapping, datapath units, high speed datapaths, parallel architectures, rapid prototyping, reconfigurable architectures, software prototyping, fine grained parallelism, data manipulations
37Seong Yong Ohm, Fadi J. Kurdahi, Nikil D. Dutt, Min Xu A comprehensive estimation technique for high-level synthesis. Search on Bibsonomy ISSS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF HLS benchmarks, RT level components, RTL datapaths, estimation technique, delays, high level synthesis, high-level synthesis, timing, design space exploration, granularity, hardware description languages, data flow graphs, registers, system buses, timing model, buses, behavioral description, layout area
37Wei Zhao, Christos A. Papachristou Architectural partitioning of control memory for application specific programmable processors. Search on Bibsonomy ICCAD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF application specific programmable processors, control memory, distributed microcode memory model, microcode memory, repetitive microcodes, distributed memory systems, memory architecture, programmability, microprogram, datapaths, firmware, memory module
37Je-Hoon Lee, Seung-Sook Lee, Kyoung-Rok Cho Asynchronous ARM Processor Employing an Adaptive Pipeline Architecture. Search on Bibsonomy ARC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF adaptive pipeline, processor, Asynchronous design
37Liang Han, Jie Chen 0012, Chaoxian Zhou, Ying Li, Xin Zhang, Zhibi Liu, Xiaoyun Wei, Baofeng Li An Embedded Reconfigurable SIMD DSP with Capability of Dimension-Controllable Vector Processing. Search on Bibsonomy ICCD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
37Tay-Jyi Lin, Chein-Wei Jen CASCADE - configurable and scalable DSP environment. Search on Bibsonomy ISCAS (4) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
33Namrata Shekhar, Priyank Kalla, M. Brandon Meredith, Florian Enescu Simulation Bounds for Equivalence Verification of Polynomial Datapaths Using Finite Ring Algebra. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
33Neal Tew, Priyank Kalla, Namrata Shekhar, Sivaram Gopalakrishnan Verification of arithmetic datapaths using polynomial function models and congruence solving. Search on Bibsonomy ICCAD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
33Namrata Shekhar, Sudhakar Kalla, Florian Enescu Equivalence Verification of Polynomial Datapaths Using Ideal Membership Testing. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
33Vyas Krishnan, Srinivas Katkoori A genetic algorithm for the design space exploration of datapaths during high-level synthesis. Search on Bibsonomy IEEE Trans. Evol. Comput. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
33Namrata Shekhar, Priyank Kalla, Florian Enescu Equivalence verification of arithmetic datapaths with multiple word-length operands. Search on Bibsonomy DATE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
33Namrata Shekhar, Priyank Kalla, M. Brandon Meredith, Florian Enescu Simulation Bounds for Equivalence Verification of Arithmetic Datapaths with Finite Word-Length Operands. Search on Bibsonomy FMCAD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
33Masahiro Fujita Equivalence checking between behavioral and RTL descriptions with virtual controllers and datapaths. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF formal verification, High-level synthesis, equivalence checking, behavior synthesis
33Ranganath Gopalan, Chandramouli Gopalakrishnan, Srinivas Katkoori Leakage Power Driven Behavioral Synthesis of Pipelined Datapaths. Search on Bibsonomy ISVLSI The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
33Manjunath Kudlur, Kevin Fan, Michael L. Chu, Rajiv A. Ravindran, Nathan Clark, Scott A. Mahlke FLASH: Foresighted Latency-Aware Scheduling Heuristic for Processors with Customized Datapaths. Search on Bibsonomy CGO The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
33Chandramouli Gopalakrishnan, Srinivas Katkoori An Architectural Leakage Power Simulator for VHDL Structural Datapaths. Search on Bibsonomy ISVLSI The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
33Chandramouli Gopalakrishnan, Srinivas Katkoori KnapBind: An Area-Efficient Binding Algorithm for Low-leakage Datapaths. Search on Bibsonomy ICCD The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
33Viktor S. Lapinskii, Margarida F. Jacome, Gustavo de Veciana Application-specific clustered VLIW datapaths: early exploration on a parameterized design space. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
33Katarzyna Radecka, Zeljko Zilic Specifying and verifying imprecise sequential datapaths by Arithmetic Transforms. Search on Bibsonomy ICCAD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
33Chandramouli Gopalakrishnan, Srinivas Katkoori Behavioral synthesis of datapaths with low leakage power. Search on Bibsonomy ISCAS (4) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
33Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Mihalis Psarakis, Yervant Zorian An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths. Search on Bibsonomy J. Electron. Test. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF datapath test, shifter, Built-in self-test, accumulator, arithmetic-logic unit, processor test
33Nektarios Kranitis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths. Search on Bibsonomy ISQED The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
33Montek Singh, Steven M. Nowick High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic Datapaths. Search on Bibsonomy ASYNC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF fine-grain pipelining, VLSI, pipelines, asynchronous, dynamic logic, FIFO, high-throughput, digital design
33Mahadevamurty Nemani, Vivek Tiwari Macro-driven circuit design methodology for high-performance datapaths. Search on Bibsonomy DAC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
33David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre BISTing Datapaths under Heterogeneous Test Schemes. Search on Bibsonomy J. Electron. Test. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF RT level, BIST, datapath, test synthesis
33Darren C. Cronquist, Chris Fisher, Miguel E. Figueroa, Paul Franklin, Carl Ebeling Architecture Design of Reconfigurable Pipelined Datapaths. Search on Bibsonomy ARVLSI The full citation details ... 1999 DBLP  DOI  BibTeX  RDF High-speed computation, Pipelining, Signal processing, Reconfigurable architectures, Configurable computing
33Marie-Lise Flottes, R. Pires, Bruno Rouzeyre, Laurent Volpe Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique. Search on Bibsonomy DATE The full citation details ... 1998 DBLP  DOI  BibTeX  RDF Scan chain selection, RT and gate levels, Partial scan, Synthesis for testability
33Saman Adham, Sanjay Gupta DP-BIST: A Built-In Self Test For DSP DataPaths A Low Overhead and High Fault Coverage Technique. Search on Bibsonomy Asian Test Symposium The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
33Baher Haroun, Behzad Sajjadi Synthesis of Signal Processing Structured Datapaths for FPGAs Supporting RAMs and Busses. Search on Bibsonomy FPGA The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
25Juan Carlos López 0001, Fernando Rincón, Francisco Moya, José Manuel Moya Improving Embedded System Design by Means of HW-SW Compilation on Reconfigurable Coprocessors. Search on Bibsonomy ISSS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF reconfigurable datapaths, hardware-software codesign
25H. Fatih Ugurdag, Thomas E. Fuhrman Autocircuit: a clock edge general behavioral synthesis system with a direct path to physical datapath. Search on Bibsonomy ICCD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Autocircuit, clock edge general behavioral synthesis system, physical datapaths, next-generation synthesis tool, behavioral HDL input descriptions, data-flow representations, use-trees, raw-states, word-oriented synthesis, unique parameterized netlist representation, high level synthesis, high-level design
24Yedidya Hilewitz, Ruby B. Lee Fast Bit Gather, Bit Scatter and Bit Permutation Instructions for Commodity Microprocessors. Search on Bibsonomy J. Signal Process. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Bit scatter, Bit gather, Parallel deposit, Unpack, Algorithm acceleration, Bioinformatics, Compression, Pattern matching, Steganography, Microprocessors, Permutations, Pack, Instruction set architecture, Cryptology, ISA, Parallel extract, Bit manipulations
24Omkar Dandekar, William Plishker, Shuvra S. Bhattacharyya, Raj Shekhar Multiobjective Optimization of FPGA-Based Medical Image Registration. Search on Bibsonomy FCCM The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
24Yee Jern Chong, Sri Parameswaran Rapid application specific floating-point unit generation with bit-alignment. Search on Bibsonomy DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF bit-alignment, datapath merging, floating-point
24Peter A. Milder, Franz Franchetti, James C. Hoe, Markus Püschel Formal datapath representation and manipulation for implementing DSP transforms. Search on Bibsonomy DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF high-level synthesis, streaming, discrete Fourier transform, linear transform
24Harmander Singh, Kanak Agarwal, Dennis Sylvester, Kevin J. Nowka Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
24Sotirios Xydis, George Economakos, Kiamal Z. Pekmestzi Flexibility Inlining into Arithmetic Data-paths Exploiting A Regular Interconnection Scheme. Search on Bibsonomy ICSAMOS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
24Kristopher D. Peterson, Justin L. Tripp Effective Automatic Memory Allocation Algorithm Based on Schedule Length in Cycles in a Novel C to FPGA Compiler. Search on Bibsonomy FPL The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
24Kaushal R. Gandhi, Nihar R. Mahapatra Exploiting data-dependent slack using dynamic multi-VDD to minimize energy consumption in datapath circuits. Search on Bibsonomy DATE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
24William B. Toms, David A. Edwards, Andrew Bardsley Synthesising Heterogeneously Encoded Systems. Search on Bibsonomy ASYNC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
24Xun Liu, Marios C. Papaefthymiou HyPE: hybrid power estimation for IP-based systems-on-chip. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
24Nahri Moreano, Edson Borin, Cid C. de Souza, Guido Araujo Efficient datapath merging for partially reconfigurable architectures. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
24Abdelhalim Alsharqawi, Abdel Ejnioui Synthesis of Self-Resetting Stage Logic Pipelines. Search on Bibsonomy ISVLSI The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
24Dara Kusic, Raymond Hoare, Alex K. Jones, Joshua Fazekas, John Foster 0001 Extracting Speedup From C-Code With Poor Instruction-Level Parallelism. Search on Bibsonomy IPDPS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
24Philip Brisk, Adam Kaplan, Majid Sarrafzadeh Area-efficient instruction set synthesis for reconfigurable system-on-chip designs. Search on Bibsonomy DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF field-programmable gate array (FPGA), compiler, resource sharing, integer linear programming (ILP)
24Jürgen Becker 0001, Alexander Thomas, Maik Scheer Efficient Processor Instruction Set Extension by Asynchronous Reconfigurable Datapath Integration. Search on Bibsonomy SBCCI The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
24Amitabh Menon, S. K. Nandy 0001, Mahesh Mehendale Multivoltage scheduling with voltage-partitioned variable storage. Search on Bibsonomy ISLPED The full citation details ... 2003 DBLP  DOI  BibTeX  RDF multivoltage, high level synthesis, datapath synthesis
24Recep O. Ozdag, Peter A. Beerel, Montek Singh, Steven M. Nowick High-Speed Non-Linear Asynchronous Pipelines. Search on Bibsonomy DATE The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
24María C. Molina, José M. Mendías, Román Hermida Bit-level scheduling of heterogeneous behavioural specifications. Search on Bibsonomy ICCAD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
24Leilei Song, Keshab K. Parhi, Ichiro Kuroda, Takao Nishitani Hardware/software codesign of finite field datapath for low-energy Reed-Solomon codecs. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
24Joan Carletta, Christos A. Papachristou, Mehrdad Nourani Detecting Undetectable Controller Faults Using Power Analysis. Search on Bibsonomy DATE The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
24Kenneth Y. Yun Recent Advances in Asynchronous Design Methodologies. Search on Bibsonomy ASP-DAC The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
24Mehrdad Nourani, Joan Carletta, Christos A. Papachristou A Scheme for Integrated Controller-Datapath Fault Testing. Search on Bibsonomy DAC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
24Hong-Shin Jun, Sun-Young Hwang Design of a pipelined datapath synthesis system for digital signal processing. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
21Yongqiang Zhang 0006, Siting Liu 0001, Jie Han 0001, Zhendong Lin, Shaowei Wang, Xin Cheng 0001, Guangjun Xie An Energy-Efficient Binary-Interfaced Stochastic Multiplier Using Parallel Datapaths. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
21Tomasz Osinski, Halina Tarasiuk New approaches to data plane programmability for software datapaths in the NFV infrastructure. Search on Bibsonomy NetSoft The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
21Nusa Zidaric, Mark D. Aagaard Tower field support for synthesis of datapaths. Search on Bibsonomy CF The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
21Ahsen Ejaz, Ioannis Sourdis FastTrackNoC: A NoC with FastTrack Router Datapaths. Search on Bibsonomy HPCA The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
21Samira Ait Bensaid, Mihail Asavoae, Farhat Thabet, Mathieu Jan Work in Progress: Automatic Construction of Pipeline Datapaths from High-Level HDL Code. Search on Bibsonomy RTAS The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
21Daniel Vázquez, Alfonso Rodríguez 0002, Andrés Otero, Eduardo de la Torre Extending RISC-V Processor Datapaths with Multi-Grain Reconfigurable Overlays. Search on Bibsonomy DCIS The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
21Yoshiya Shikama, Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto, Michihiro Koibuchi Low-Latency Low-Energy Memory-Cube Networks using Dual-Voltage Datapaths. Search on Bibsonomy PDP The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
21Inbal Stanger, Netanel Shavit, Ramiro Taco, Marco Lanuzza, Alexander Fish Live Demo: Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths. Search on Bibsonomy ISCAS The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
21Yiming Qiu, Hongyi Liu, Thomas E. Anderson, Yingyan Lin, Ang Chen 0001 Toward reconfigurable kernel datapaths with learned optimizations. Search on Bibsonomy HotOS The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
21Philip Rohde Merging Datapaths using Data Processing Graphs. Search on Bibsonomy 2021   RDF
21Mohammad Reza Esmaeili, Seyed Hamid Zahiri, Seyed Mohammad Razavi A novel method for high-level synthesis of datapaths in digital filters using a moth-flame optimization algorithm. Search on Bibsonomy Evol. Intell. The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
21Inbal Stanger, Netanel Shavit, Ramiro Taco, Marco Lanuzza, Alexander Fish Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths. Search on Bibsonomy IEEE Trans. Circuits Syst. II Express Briefs The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
21Vasileios Kokkinos, Athanasios Kakarountas Design of Reconfigurable Fault-Tolerant Datapaths. Search on Bibsonomy SEEDA-CECNSM The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
21Loris Duch, Soumya Basu 0002, Miguel Peón Quirós, Giovanni Ansaloni, Laura Pozzi, David Atienza i-DPs CGRA: An Interleaved-Datapaths Reconfigurable Accelerator for Embedded Bio-Signal Processing. Search on Bibsonomy IEEE Embed. Syst. Lett. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
21Keith A. Campbell, Chen-Hsuan Lin, Deming Chen Cost-Effective Error Detection Through Mersenne Modulo Shadow Datapaths. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
21Alberto A. Del Barrio, Román Hermida, Seda Ogrenci Memik A Combined Arithmetic-High-Level Synthesis Solution to Deploy Partial Carry-Save Radix-8 Booth Multipliers in Datapaths. Search on Bibsonomy IEEE Trans. Circuits Syst. I Regul. Pap. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
21Alexander J. Groszewski, Travis Lenz Deterministic Stochastic Computation Using Parallel Datapaths. Search on Bibsonomy ISQED The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
21Paul Chaignon Software Datapaths for Multi-Tenant Packet Processing. (Plans de données logiciels pour les traitements réseaux en environnements partagés). Search on Bibsonomy 2019   RDF
21Arman Roohi, Ronald F. DeMara NV-Clustering: Normally-Off Computing Using Non-Volatile Datapaths. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
21Sana Mazahir, Osman Hasan, Muhammad Shafique 0001 Adaptive Approximate Computing in Arithmetic Datapaths. Search on Bibsonomy IEEE Des. Test The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
21Bruno Miguel Gil Rosa, Henry M. D. Ip, Guang-Zhong Yang Wireless Datapaths and Security. Search on Bibsonomy Implantable Sensors and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
21Mohammad Saber Golanbari, Mehdi Baradaran Tahoori Optimizing Datapaths for Near Threshold Computing. Search on Bibsonomy SMACD The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
21Christopher Leet, Xin Wang, Yang Richard Yang, James Aspnes Toward the First SDN Programming Capacity Theorem on Realizing High-Level Programs on Low-Level Datapaths. Search on Bibsonomy INFOCOM The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
21Sheikh Ariful Islam, Srinivas Katkoori High-level synthesis of key based obfuscated RTL datapaths. Search on Bibsonomy ISQED The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
21Amir Sabbagh Molahosseini, Azadeh Alsadat Emrani Zarandi, Paulo Martins 0002, Leonel Sousa A Multifunctional Unit for Designing Efficient RNS-Based Datapaths. Search on Bibsonomy IEEE Access The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
21Matei Istoan, Florent de Dinechin Automating the pipeline of arithmetic datapaths. Search on Bibsonomy DATE The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
21Philip Gottschling, Christian Hochberger ReEP: A Toolset for Generation and Programming of Reconfigurable Datapaths for Event Processing. Search on Bibsonomy IPDPS Workshops The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
21Aurojit Panda, Ori Lahav 0001, Katerina J. Argyraki, Mooly Sagiv, Scott Shenker Verifying Reachability in Networks with Mutable Datapaths. Search on Bibsonomy NSDI The full citation details ... 2017 DBLP  BibTeX  RDF
21Aurojit Panda, Ori Lahav 0001, Katerina J. Argyraki, Mooly Sagiv, Scott Shenker Verifying Reachability in Networks with Mutable Datapaths. Search on Bibsonomy CoRR The full citation details ... 2016 DBLP  BibTeX  RDF
21Rei Ueno, Sumio Morioka, Naofumi Homma, Takafumi Aoki A High Throughput/Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths - Toward Efficient CBC-Mode Implementation. Search on Bibsonomy IACR Cryptol. ePrint Arch. The full citation details ... 2016 DBLP  BibTeX  RDF
21Donghai Li, Xiaochen Zhu, Zhonglei Fan, Xiaojun Yang 多项式数据通路的优化方法 (Method of Optimization for Polynomial Datapaths). Search on Bibsonomy 计算机科学 The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
21Xiaobo Yin, Feng Yu 0003, Zhen-guo Ma Resource-Efficient Pipelined Architectures for Radix-2 Real-Valued FFT With Real Datapaths. Search on Bibsonomy IEEE Trans. Circuits Syst. II Express Briefs The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
21Nachiket Kapre, Deheng Ye GPU-Accelerated High-Level Synthesis for Bitwidth Optimization of FPGA Datapaths. Search on Bibsonomy FPGA The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
21Rei Ueno, Sumio Morioka, Naofumi Homma, Takafumi Aoki A High Throughput/Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths - Toward Efficient CBC-Mode Implementation. Search on Bibsonomy CHES The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
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