Search results for "design-for-yield"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
42	Markus Bühler, Jürgen Koehl, Jeanne Bickford, Jason Hibbeler, Ulf Schlichtmann, Ralf Sommer, Michael Pronath, Andreas Ripp	DFM/DFY design for manufacturability and yield - influence of process variations in digital, analog and mixed-signal circuit design.	DATE	2006	DBLP DOI BibTeX RDF
35	Yu-Tsao Hsing, Chih-Wea Wang, Ching-Wei Wu, Chih-Tsun Huang, Cheng-Wen Wu	Failure Factor Based Yield Enhancement for SRAM Designs.	DFT	2004	DBLP DOI BibTeX RDF
28	Giuseppe Nicosia, Giovanni Stracquadanio	A Design-for-Yield Algorithm to Assess and Improve the Structural and Energetic Robustness of Proteins and Drugs.	SEA	2009	DBLP DOI BibTeX RDF
26	Shi-Hao Chen, Ke-Cheng Chu, Jiing-Yuan Lin, Cheng-Hong Tsai	DFM/DFY practices during physical designs for timing, signal integrity, and power.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.13 micron, DFY, dynamic IR drop, process variation, physical designs, DFM, design for manufacturability, signal integrity, timing integrity, yield analysis, design for yield
23	Thomas W. Williams	Design for Testability: The Path to Deep Submicron.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
16	YuHua Cheng	A glance of technology efforts for design-for-manufacturing in nano-scale CMOS processes.	Sci. China Ser. F Inf. Sci.	2008	DBLP DOI BibTeX RDF	nano-CMOS IC design, IC design methodology, CMOS design technology platform, design-for-manufacturing (DFM), design-for-yield
16	Qiang Zhou 0001, Yici Cai, Duo Li, Xianlong Hong	A Yield-Driven Gridless Router.	J. Comput. Sci. Technol.	2007	DBLP DOI BibTeX RDF	gridless routing, integrated circuit layout, critical area, design for yield
16	Philipp V. Panitz, Markus Olbrich, Erich Barke, Jürgen Koehl	Robust wiring networks for DfY considering timing constraints.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	redundant wiring, timing constraint aware, open defects, design for yield
16	Shishpal Rawat, Raul Camposano, Andrew B. Kahng, Joseph Sawicki, Mike Gianfagna, Naeem Zafar, Atul Sharan	DFM: where's the proof of value?	DAC	2006	DBLP DOI BibTeX RDF	ROI, DFM, design for manufacture, OPC, RET, yield optimization, design for yield
15	Srikanth Venkataraman, Pongpachara Limpisathian, Pascal Meinerzhagen, Suriyaprakash Natarajan, Eric Yang	Automating Design For Yield: Silicon Learning to Predictive Models and Design Optimization.	ITC	2020	DBLP DOI BibTeX RDF
15	Johanna Sepúlveda	T1B: Special session: Data analytics driven design for yield, manufacturability and reliability: Where machine learning meets design automation.	SoCC	2017	DBLP DOI BibTeX RDF
15	Marc E. Levitt	Design for Manufacturing? Design for Yield!!!	ISQED	2004	DBLP DOI BibTeX RDF
15	David M. Wu	DFT is all I can afford, who cares about Design for Yield or Design for Reliability!	ITC	1999	DBLP DOI BibTeX RDF
14	Song Peng, Rajit Manohar	Yield enhancement of asynchronous logic circuits through 3-dimensional integration technology.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	asynchronous circuits, yield, defect tolerance, 3D integration, self-reconfiguration
13	Suriyaprakash Natarajan, Andres F. Malavasi, Pascal Andreas Meinerzhagen	Automated Design For Yield Through Defect Tolerance.	VTS	2020	DBLP DOI BibTeX RDF
13	Soowang Park, Sandeep K. Gupta 0001	Cache Design for Yield-per-Area Maximization: Switchable Spare Columns with Disabling (SSC-Disable).	VTS	2019	DBLP DOI BibTeX RDF
13	R. Lajmi, Florian Cacho, Estelle Lauga-Larroze, Sylvain Bourdel, Ph. Benech, Vincent Huard, X. Federspiel	Characterization of Low Drop-Out during ageing and design for yield.	Microelectron. Reliab.	2017	DBLP DOI BibTeX RDF
13	Nishant Patil, Subhasish Mitra, Steven S. Lumetta	Signature Analyzer Design for Yield Learning Support.	ITC	2006	DBLP DOI BibTeX RDF
13	Saibal Mukhopadhyay, Arijit Raychowdhury, Hamid Mahmoodi-Meimand, Kaushik Roy 0001	Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
13	Yervant Zorian, Dimitris Gizopoulos, Cary Vandenberg, Philippe Magarshack	Guest Editors' Introduction: Design for Yield and Reliability.	IEEE Des. Test Comput.	2004	DBLP DOI BibTeX RDF
13	D. M. H. Walker	Design for Yield and Reliability is MORE Important Than DFT.	ITC	1999	DBLP DOI BibTeX RDF
13	M. Eisele, Jörg Berthold, Doris Schmitt-Landsiedel, R. Mahnkopf	The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
13	M. Eisele, Jörg Berthold, Doris Schmitt-Landsiedel, R. Mahnkopf	The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits.	ISLPED	1996	DBLP DOI BibTeX RDF
9	Robert C. Aitken, Sachin Idgunji	Worst-case design and margin for embedded SRAM.	DATE	2007	DBLP DOI BibTeX RDF
9	Sy-Yen Kuo, W. Kent Fuchs	Spare Allocation and Reconfiguration in Large Area VLSI.	DAC	1988	DBLP BibTeX RDF
7	Jamil Kawa, Charles C. Chiang	DFM issues for 65nm and beyond.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	DFY, DFM
7	Vladimir Hahanov	2005 IEEE East-West Design and Test Workshop.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	EWDTW 2005, formal verification, fault diagnosis, debug, BIST, EDA, system-level modeling
7	Shyue-Kung Lu, Jen-Sheng Shih, Shih-Chang Huang	Design-for-testability and fault-tolerant techniques for FFT processors.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF