Search results for "dual-VT"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
76	Fei Li 0003, Yan Lin 0001, Lei He 0001, Jason Cong	Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics.	FPGA	2004	DBLP DOI BibTeX RDF	FPGA, low power, power efficient, dual-Vdd, dual-Vt
49	Qi Wang, Sarma B. K. Vrudhula	An Investigation of Power Delay Tradeoffs for Dual Vt CMOS Circuits.	ICCD	1999	DBLP DOI BibTeX RDF	low power, CMOS circuits, dual Vt
35	Amit Agarwal 0001, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy 0001	Device-Aware Yield-Centric Dual-Vt Design Under Parameter Variations in Nanoscale Technologies.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
35	Akhilesh Kumar, Mohab Anis	Dual-Vt Design of FPGAs for Subthreshold Leakage Tolerance.	ISQED	2006	DBLP DOI BibTeX RDF
32	Amit Agarwal 0001, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy 0001	Effectiveness of low power dual-Vt designs in nano-scale technologies under process parameter variations.	ISLPED	2005	DBLP DOI BibTeX RDF	process variation, yield, leakage, dual-Vt, metal gate
26	Jungseob Lee, Azadeh Davoodi	Comparison of Dual-Vt Configurations of SRAM Cell Considering Process-Induced Vt Variations.	ISCAS	2007	DBLP DOI BibTeX RDF
25	Akhilesh Kumar, Mohab Anis	Dual-Threshold CAD Framework for Subthreshold Leakage Power Aware FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
24	Debasis Samanta, Ajit Pal	Synthesis of Dual-VT Dynamic CMOS Circuits.	VLSI Design	2003	DBLP DOI BibTeX RDF	nora logic, unate decomposition, low power, Logic synthesis, high performance, leakage power, domino logic, dynamic circuits, dual-VT
24	Tanay Karnik, Yibin Ye, James W. Tschanz, Liqiong Wei, Steven M. Burns, Venkatesh Govindarajulu, Vivek De, Shekhar Borkar	Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors.	DAC	2002	DBLP DOI BibTeX RDF	Dual-Vt design, multiple threshold, optimization, sizing
21	Jaehyun Kim, Youngsoo Shin	Minimizing leakage power in sequential circuits by using mixed Vt flip-flops.	ICCAD	2007	DBLP DOI BibTeX RDF
19	Behnam Amelifard, Farzan Fallah, Massoud Pedram	Reducing the sub-threshold and gate-tunneling leakage of SRAM cells using Dual-Vt and Dual-Tox assignment.	DATE	2006	DBLP DOI BibTeX RDF
18	Aditya Bansal, Jae-Joon Kim, Keunwoo Kim, Saibal Mukhopadhyay, Ching-Te Chuang, Kaushik Roy 0001	Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies.	VLSI Design	2008	DBLP DOI BibTeX RDF
18	Lara D. Oliver, Krishnendu Chakrabarty, Hisham Z. Massoud	An evaluation of the impact of gate oxide tunneling on dual-Vt-based leakage reduction techniques.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	gate oxide tunneling, low power circuit design, subthreshold leakage, dual threshold voltage
18	Debasis Samanta, Ajit Pal	Synthesis of Low Power High Performance Dual-VT PTL Circuits.	VLSI Design	2004	DBLP DOI BibTeX RDF
18	Fatih Hamzaoglu, Yibin Ye, Ali Keshavarzi, Kevin Zhang 0001, Siva G. Narendra, Shekhar Borkar, Mircea R. Stan, Vivek De	Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
18	Debasis Samanta, Ajit Pal	Optimal Dual -VT Assignment for Low-Voltage Energy-Constrained CMOS Circuits.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
17	Muhammad E. S. Elrabaa, Mohamed I. Elmasry	Split-Gate Logic circuits for multi-threshold technologies.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
15	Navid Azizi, Andreas Moshovos, Farid N. Najm	Low-leakage asymmetric-cell SRAM.	ISLPED	2002	DBLP DOI BibTeX RDF	low-leakage, low-power, SRAM, dual-Vt
14	Jungseob Lee, Lin Xie, Azadeh Davoodi	A Dual-Vt low leakage SRAM array robust to process variations.	ISCAS	2008	DBLP DOI BibTeX RDF
14	Chulwoo Kim, Ki-Wook Kim, Sung-Mo Kang	Energy-efficient skewed static logic with dual Vt: design and synthesis.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
13	Chua-Chin Wang, Chi-Chun Huang, Ching-Li Lee, Tsai-Wen Cheng	A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
13	Vivek De	Leakage-tolerant design techniques for high performance processors.	ISPD	2002	DBLP DOI BibTeX RDF
13	Volkan Kursun, Eby G. Friedman	Low swing dual threshold voltage domino logic.	ACM Great Lakes Symposium on VLSI	2002	DBLP DOI BibTeX RDF
10	Behnam Amelifard, Farzan Fallah, Massoud Pedram	Leakage Minimization of SRAM Cells in a Dual-Vt and Dual-Tox Technology.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
10	Dongwoo Lee, David T. Blaauw, Dennis Sylvester	Runtime leakage minimization through probability-aware dual-Vt or dual-tox assignment.	ASP-DAC	2005	DBLP DOI BibTeX RDF
10	Sandeep Gupta, Jaya Singh, Abhijit Roy	A Novel Cell-Based Heuristic Method for Leakage Reduction in Multi-Million Gate VLSI Designs.	ISQED	2008	DBLP DOI BibTeX RDF	Dual-Vt Technology, Cell-Based Approach, Cell-swapping, Leakage Power
10	Steven Hsu, Amit Agarwal 0001, Kaushik Roy 0001, Ram Krishnamurthy 0001, Shekhar Borkar	An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS.	ISLPED	2005	DBLP DOI BibTeX RDF	dual-Vt/Vcc, flip-flop, hot spot, level converter
10	Feng Gao 0017, John P. Hayes	Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages.	DAC	2005	DBLP DOI BibTeX RDF	low power, linear programming, gate sizing, dual Vt
10	Robert Bai, Sarvesh H. Kulkarni, Wesley Kwong, Ashish Srivastava, Dennis Sylvester, David T. Blaauw	An Implementation of a 32-bit ARM Processor Using Dual Power Supplies and Dual Threshold Voltages.	ISVLSI	2003	DBLP DOI BibTeX RDF	ARM processor, Low power design, CVS, Dual-Vt
10	Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Jingyan Zuo, Abhijit Dharchoudhury, Rajendran Panda, David T. Blaauw	Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing.	DAC	1999	DBLP DOI BibTeX RDF	low-power-design, leakage, dual-Vt
9	Kanak Agarwal, Dennis Sylvester, David T. Blaauw, Anirudh Devgan	Achieving continuous VT performance in a dual VT process.	ASP-DAC	2005	DBLP DOI BibTeX RDF
9	Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Rajendran Panda, David T. Blaauw	Duet: an accurate leakage estimation and optimization tool for dual-Vt circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
9	Qi Wang, Sarma B. K. Vrudhula	Algorithms for minimizing standby power in deep submicrometer, dual-Vt CMOS circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
9	Chulwoo Kim, Ki-Wook Kim, Sung-Mo Kang	Energy-efficient skewed static logic design with dual Vt.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
8	Kiyoo Itoh 0001	Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era.	ISLPED	2009	DBLP DOI BibTeX RDF	0.5-v nanoscale cmos lsis, conventional mosfet, minimum vdd, speed variation, vt variation, leakage, sram, dram, finfet
8	Lin Yuan, Gang Qu 0001	Simultaneous input vector selection and dual threshold voltage assignment for static leakage minimization.	ICCAD	2007	DBLP DOI BibTeX RDF
8	Somsubhra Mondal, Seda Ogrenci Memik	Power Optimization Techniques for SRAM-Based FPGAs.	FPL	2006	DBLP DOI BibTeX RDF
8	Dongwoo Lee, Harmander Deogun, David T. Blaauw, Dennis Sylvester	Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization.	DATE	2004	DBLP DOI BibTeX RDF
8	Ge Yang 0004, Zhongda Wang, Sung-Mo Kang	Leakage-Proof Domino Circuit Design for Deep Sub-100nm Technologies.	VLSI Design	2004	DBLP DOI BibTeX RDF
8	Ashish Srivastava, Dennis Sylvester, David T. Blaauw	Statistical optimization of leakage power considering process variations using dual-Vth and sizing.	DAC	2004	DBLP DOI BibTeX RDF	optimization, variability, leakage
8	Li Yang, J. S. Yuan	Enhanced Techniques for Current Balanced Logic in Mixed-Signal ICs.	ISVLSI	2003	DBLP DOI BibTeX RDF
8	Chulwoo Kim, Jaesik Lee, Kwang-Hyun Baek, Eric Martina, Sung-Mo Kang	High-Performance, Low-Power Skewed Static Logic in Very Deep-Submicron (VDSM) Technology.	ICCD	2000	DBLP DOI BibTeX RDF
8	Kamal S. Khouri, Niraj K. Jha	Leakage Power Analysis and Reduction during Behavioral Synthesis.	ICCD	2000	DBLP DOI BibTeX RDF
5	Alireza Shafaei, Massoud Pedram	Energy-efficient cache memories using a dual-Vt 4T SRAM cell with read-assist techniques.	DATE	2016	DBLP BibTeX RDF
5	Hong Zhu 0009, Volkan Kursun	2-Phase high-frequency clock distribution with SPLIT-IO dual-Vt repeaters for suppressed leakage currents.	ISCAS	2015	DBLP DOI BibTeX RDF
5	Na Gong, Jinhui Wang, Ramalingam Sridhar	Variation Aware Sleep Vector Selection in Dual Vt Dynamic OR Circuits for Low Leakage Register File Design.	IEEE Trans. Circuits Syst. I Regul. Pap.	2014	DBLP DOI BibTeX RDF
5	S. M. Yasser Sherazi, Joachim Neves Rodrigues, Omer Can Akgun, Henrik Sjöland, Peter Nilsson 0001	Ultra low energy design exploration of digital decimation filters in 65 nm dual-VT CMOS in the sub-VT domain.	Microprocess. Microsystems	2013	DBLP DOI BibTeX RDF
5	Oskar Andersson, Babak Mohammadi, Pascal Meinerzhagen, Andreas Burg, Joachim Neves Rodrigues	Dual-VT 4kb sub-VT memories with <1 pW/bit leakage in 65 nm CMOS.	ESSCIRC	2013	DBLP DOI BibTeX RDF
5	Wei Ting Loke, Yajun Ha, Wenfeng Zhao	A Power and Cluster-Aware Technology Mapping and Clustering Scheme for Dual-VT FPGAs.	IPDPS Workshops	2012	DBLP DOI BibTeX RDF
5	Wei Ting Loke, Yajun Ha	A Routing Architecture for FPGAs with Dual-VT Switch Box and Logic Clusters.	ARC	2012	DBLP DOI BibTeX RDF
5	Jinhui Wang, Na Gong, Ligang Hou, Xiaohong Peng, Ramalingam Sridhar, Wuchen Wu	Leakage current, active power, and delay analysis of dynamic dual Vt CMOS circuits under P-V-T fluctuations.	Microelectron. Reliab.	2011	DBLP DOI BibTeX RDF
5	Junjun Gu, Gang Qu 0001, Lin Yuan, Cheng Zhuo	Improving dual Vt technology by simultaneous gate sizing and mechanical stress optimization.	ICCAD	2011	DBLP DOI BibTeX RDF
5	Na Gong, Jinhui Wang, Ramalingam Sridhar	PVT variations aware optimal sleep vector determination of dual VT domino OR circuits.	SoCC	2011	DBLP DOI BibTeX RDF
5	Wenbin Liu, Jinhui Wang, Wuchen Wu, Xiaohong Peng, Ligang Hou	A study of dual-Vt configurations of an 8T SRAM cell in 45nm.	ASICON	2011	DBLP DOI BibTeX RDF
5	Andrea Calimera, R. Iris Bahar, Enrico Macii, Massimo Poncino	Dual-Vt assignment policies in ITD-aware synthesis.	Microelectron. J.	2010	DBLP DOI BibTeX RDF
5	Jun Seomun, Seungwhun Paik, Youngsoo Shin	Bounded potential slack: enabling time budgeting for dual-Vt allocation of hierarchical design.	ASP-DAC	2010	DBLP DOI BibTeX RDF
5	Junjun Gu, Gang Qu 0001, Lin Yuan	Enhancing dual-Vt design with consideration of on-chip temperature variation.	ICCD	2010	DBLP DOI BibTeX RDF
5	Keiichiro Hirai, Masaru Kato, Yoshiki Saito, Hideharu Amano	Leakage power reduction for coarse-grained dynamically reconfigurable processor arrays using Dual Vt cells.	FPT	2009	DBLP DOI BibTeX RDF
5	Na Gong, Baozeng Guo, Jianzhong Lou, Jinhui Wang	Analysis and optimization of leakage current characteristics in sub-65 nm dual Vt footed domino circuits.	Microelectron. J.	2008	DBLP DOI BibTeX RDF
5	Tai-Hsuan Wu, Lin Xie, Azadeh Davoodi	A Parallel and Randomized Algorithm for Large-Scale Discrete Dual-Vt Assignment and Continuous Gate Sizing.	J. Low Power Electron.	2008	DBLP DOI BibTeX RDF
5	Sudip Roy 0001, Ajit Pal	Why to Use Dual-Vt, If Single-Vt Serves the Purpose Better under Process Parameter Variations?	DSD	2008	DBLP DOI BibTeX RDF
5	Tai-Hsuan Wu, Lin Xie, Azadeh Davoodi	A parallel and randomized algorithm for large-scale discrete dual-Vt assignment and continuous gate sizing.	ISLPED	2008	DBLP DOI BibTeX RDF
5	Andrea Calimera, R. Iris Bahar, Enrico Macii, Massimo Poncino	Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits.	ISLPED	2008	DBLP DOI BibTeX RDF
5	Sherif A. Tawfik, Volkan Kursun	Low power and robust 7T dual-Vt SRAM circuit.	ISCAS	2008	DBLP DOI BibTeX RDF
5	Yu Wang 0002, Huazhong Yang, Hui Wang 0004	Signal-Path-Level Dual-VT Assignment for Leakage Power Reduction.	J. Circuits Syst. Comput.	2006	DBLP DOI BibTeX RDF
5	Akhilesh Kumar, Mohab Anis	Dual-Vt FPGA design for leakage power reduction (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
5	Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De	A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOS.	ICCD	2005	DBLP DOI BibTeX RDF
5	Peter Hazucha, Tanay Karnik, Steven Walstra, Bradley A. Bloechel, James W. Tschanz, Jose Maiz, Krishnamurthy Soumyanath, Gregory E. Dermer, Siva G. Narendra, Vivek De, Shekhar Borkar	Measurements and analysis of SER-tolerant latch in a 90-nm dual-VT CMOS process.	IEEE J. Solid State Circuits	2004	DBLP DOI BibTeX RDF
5	Yibin Ye, Muhammad M. Khellah, Dinesh Somasekhar, Ali Farhang, Vivek De	A 6-GHz 16-kB L1 cache in a 100-nm dual-VT technology using a bitline leakage reduction (BLR) technique.	IEEE J. Solid State Circuits	2003	DBLP DOI BibTeX RDF
5	Peter Hazucha, Tanay Kamik, Steven Walstra, Bradley A. Bloechel, James W. Tschanz, Jose Maiz, Krishnamurthy Soumyanath, Greg Dermer, Siva G. Narendra, Vivek De, Shekhar Borkar	Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process.	CICC	2003	DBLP DOI BibTeX RDF
5	Sriram R. Vangal, Mark A. Anders 0001, Nitin Borkar, Erik Seligman, Venkatesh Govindarajulu, Vasantha Erraguntla, Howard Wilson, Amaresh Pangal, Venkat Veeramachaneni, James W. Tschanz, Yibin Ye, Dinesh Somasekhar, Bradley A. Bloechel, Gregory E. Dermer, Ram K. Krishnamurthy, Krishnamurthy Soumyanath, Sanu Mathew, Siva G. Narendra, Mircea R. Stan, Scott Thompson, Vivek De, Shekhar Borkar	5-GHz 32-bit integer execution core in 130-nm dual-VT CMOS.	IEEE J. Solid State Circuits	2002	DBLP DOI BibTeX RDF
5	Ali Keshavarzi, Sean Ma, Siva G. Narendra, Brad Bloechel, K. Mistry, Tahir Ghani, Shekhar Borkar, Vivek De	Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs.	ISLPED	2001	DBLP DOI BibTeX RDF
5	Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang	Noise constrained power optimization for dual VT domino logic.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
5	Qi Wang, Sarma B. K. Vrudhula	Static power optimization of deep submicron CMOS circuits for dual VT technology.	ICCAD	1998	DBLP DOI BibTeX RDF
4	David Bol, Denis Flandre, Jean-Didier Legat	Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits.	ISLPED	2009	DBLP DOI BibTeX RDF	adaptive circuits, subthreshold logic, variability, CMOS digital integrated circuits, ultra-low power
4	Bruno Bougard, Bjorn De Sutter, Sebastien Rabou, David Novo, Osman Allam, Steven Dupont, Liesbet Van der Perre	A Coarse-Grained Array based Baseband Processor for 100Mbps+ Software Defined Radio.	DATE	2008	DBLP DOI BibTeX RDF
4	Mu-Tien Chang, Po-Tsang Huang, Wei Hwang	A robust ultra-low power asynchronous FIFO memory with self-adaptive power control.	SoCC	2008	DBLP DOI BibTeX RDF
4	Soheil Ghiasi	Efficient Implementation Selection via Time Budgeting Complexity Analysis and Leakage Optimization Case Study.	ICCD	2005	DBLP DOI BibTeX RDF
4	Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny	Low-leakage repeaters for NoC interconnects.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
4	Chris H. Kim, Steven Hsu, Ram Krishnamurthy 0001, Shekhar Borkar, Kaushik Roy 0001	Self Calibrating Circuit Design for Variation Tolerant VLSI Systems.	IOLTS	2005	DBLP DOI BibTeX RDF
4	Akihito Sakanaka, Seiichirou Fujii, Toshinori Sato	A leakage-energy-reduction technique for highly-associative caches in embedded systems.	SIGARCH Comput. Archit. News	2004	DBLP DOI BibTeX RDF	cache memories, embedded processors, leakage current
4	Seiichiro Fujii, Toshinori Sato	Non-uniform Set-Associative Caches for Power-Aware Embedded Processors.	EUC	2004	DBLP DOI BibTeX RDF
4	Navid Azizi, Farid N. Najm	An Asymmetric SRAM Cell to Lower Gate Leakage.	ISQED	2004	DBLP DOI BibTeX RDF
4	Seoksoo Yoon, Seok-Ryong Yoon, Seon Wook Kim, Chulwoo Kim	Charge-Sharing-Problem Reduced Split-Path Domino Logic.	VLSI Design	2004	DBLP DOI BibTeX RDF
4	Per Larsson-Edefors, Daniel Eckerbert, Henrik Eriksson, Lars J. Svensson	Dual Threshold Voltage Circuits in the Presence of Resistive Interconnects.	ISVLSI	2003	DBLP DOI BibTeX RDF
4	Dongwoo Lee, David T. Blaauw	Static leakage reduction through simultaneous threshold voltage and state assignment.	DAC	2003	DBLP DOI BibTeX RDF
4	Jason Stinson, Stefan Rusu	A 1.5GHz third generation itanium® 2 processor.	DAC	2003	DBLP DOI BibTeX RDF	on-die cache, reliability, test, design methodology, processor
4	James T. Kao, Siva G. Narendra, Anantha P. Chandrakasan	Subthreshold leakage modeling and reduction techniques.	ICCAD	2002	DBLP DOI BibTeX RDF
4	Michael D. Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy 0001, T. N. Vijaykumar	Reducing leakage in a high-performance deep-submicron instruction cache.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
4	Ashutosh S. Dhodapkar, Chee How Lim, George Cai, W. Robert Daasch	TEM2P2EST: A Thermal Enabled Multi-model Power/Performance ESTimator.	PACS	2000	DBLP DOI BibTeX RDF
4	Martin Margala	Low-Power SRAM Circuit Design.	MTDT	1999	DBLP DOI BibTeX RDF	design, VLSI, low-power, SRAM, low-voltage
4	David T. Blaauw, Abhijit Dharchoudhury, Rajendran Panda, Supamas Sirichotiyakul, Chanhee Oh, Tim Edwards	Emerging power management tools for processor design.	ISLPED	1998	DBLP DOI BibTeX RDF	low power CAD, standby leakage, power distribution