Search results for "dual-Vdd"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
215	Fei Li 0003, Yan Lin 0001, Lei He 0001, Jason Cong	Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics.	FPGA	2004	DBLP DOI BibTeX RDF	FPGA, low power, power efficient, dual-Vdd, dual-Vt
148	Yan Lin 0001, Lei He 0001	Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction.	DAC	2005	DBLP DOI BibTeX RDF	programmable-Vdd, time slack, FPGA, low power
146	Yan Lin 0001, Lei He 0001	Dual-Vdd Interconnect With Chip-Level Time Slack Allocation for FPGA Power Reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
139	Fei Li 0003, Yan Lin 0001, Lei He 0001	FPGA power reduction using configurable dual-Vdd.	DAC	2004	DBLP DOI BibTeX RDF	FPGA, low power, configurable, power efficient, dual-Vdd
130	Harmander Deogun, Robert M. Senger, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka	A dual-VDD boosted pulsed bus technique for low power and low leakage operation.	ISLPED	2006	DBLP DOI BibTeX RDF	pulsed bus, leakage, repeaters, Dual-VDD
117	Himanshu Kaul, Dennis Sylvester	A novel buffer circuit for energy efficient signaling in dual-VDD systems.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	on-chip signaling, low-power, repeaters, dual-VDD
111	Sarvesh H. Kulkarni, Dennis Sylvester	Power distribution techniques for dual VDD circuits.	ASP-DAC	2006	DBLP DOI BibTeX RDF
111	Yu Hu 0002, Yan Lin 0001, Lei He 0001, Tim Tuan	Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction.	DAC	2006	DBLP DOI BibTeX RDF	FPGA, low power, retiming
106	Kiyoo Itoh 0001	Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era.	ISLPED	2009	DBLP DOI BibTeX RDF	0.5-v nanoscale cmos lsis, conventional mosfet, minimum vdd, speed variation, vt variation, leakage, sram, dram, finfet
104	Deming Chen, Jason Cong, Fei Li 0003, Lei He 0001	Low-power technology mapping for FPGA architectures with dual supply voltages.	FPGA	2004	DBLP DOI BibTeX RDF	low-power FPGA, technology mapping, dual supply voltage
103	King Ho Tam, Lei He 0001	Power optimal dual-Vdd buffered tree considering buffer stations and blockages.	DAC	2005	DBLP DOI BibTeX RDF	low power, buffer insertion, detail routing
102	Yu Hu 0002, King Ho Tam, Tong Jing, Lei He 0001	Fast dual-vdd buffering based on interconnect prediction and sampling.	SLIP	2007	DBLP DOI BibTeX RDF	routing, low power, interconnect, buffer insertion, dual-Vdd
95	Deming Chen, Jason Cong	Delay optimal low-power circuit clustering for FPGAs with dual supply voltages.	ISLPED	2004	DBLP DOI BibTeX RDF	circuit clustering, low-power FPGA, dual supply voltage
90	Aswath Oruganti, Nagarajan Ranganathan	Leakage Power Reduction in Dual-Vdd and Dual-Vth Designs through Probabilistic Analysis of Vth Variation.	VLSI Design	2006	DBLP DOI BibTeX RDF
89	Fei Li 0003, Yan Lin 0001, Lei He 0001	Field Programmability of Supply Voltages for FPGA Power Reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
87	Rajarshi Mukherjee, Song Liu, Seda Ogrenci Memik, Somsubhra Mondal	A high-level clustering algorithm targeting dual Vdd FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	clustering, field programmable gate arrays, partitioning, placement, voltage scaling, Dynamic power
83	Aman Gayasen, K. Lee, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Tim Tuan	A Dual-VDD Low Power FPGA Architecture.	FPL	2004	DBLP DOI BibTeX RDF
82	Yu Ching Chang, King Ho Tam, Lei He 0001	Power-optimal repeater insertion considering Vdd and Vth as design freedoms.	ISLPED	2005	DBLP DOI BibTeX RDF	low power, buffer insertion
81	Yu Hu 0002, Yan Lin 0001, Lei He 0001, Tim Tuan	Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	FPGA, Low power, retiming
76	Sarvesh H. Kulkarni, Ashish Srivastava, Dennis Sylvester	A new algorithm for improved VDD assignment in low power dual VDD systems.	ISLPED	2004	DBLP DOI BibTeX RDF	ECVS, dual VDD design, low power design algorithms, CVS, level converters
76	Insup Shin, Seungwhun Paik, Youngsoo Shin	Register allocation for high-level synthesis using dual supply voltages.	DAC	2009	DBLP DOI BibTeX RDF	low power, high-level synthesis, register allocation, dual supply voltage
75	Ashish Srivastava, Dennis Sylvester, David T. Blaauw	Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment.	DAC	2004	DBLP DOI BibTeX RDF	optimization, power dissipation, multiple voltages
73	Mohammad Reza Kakoee, Ashoka Visweswara Sathanur, Antonio Pullini, Jos Huisken, Luca Benini	Automatic synthesis of near-threshold circuits with fine-grained performance tunability.	ISLPED	2010	DBLP DOI BibTeX RDF	near threshold, sub-threshold performance, variability compensation, low power, ultra low power, dual VDD, sub-threshold
72	Yan Lin 0001, Lei He 0001	Interactive presentation: Statistical dual-Vdd assignment for FPGA interconnect power reduction.	DATE	2007	DBLP DOI BibTeX RDF
69	Xiaoming Chen 0003, Yu Wang 0002, Yu Cao 0001, Yuchun Ma, Huazhong Yang	Variation-aware supply voltage assignment for minimizing circuit degradation and leakage.	ISLPED	2009	DBLP DOI BibTeX RDF	dynamic vdd scaling, leakage power, negative bias temperature instability (NBTI), dual vdd
61	Stephen Bijansky, Sae Kyu Lee, Adnan Aziz	TuneLogic: Post-silicon tuning of dual-Vdd designs.	ISQED	2009	DBLP DOI BibTeX RDF
59	Stephen Bijansky, Adnan Aziz	TuneFPGA: post-silicon tuning of dual-Vdd FPGAs.	DAC	2008	DBLP DOI BibTeX RDF	FPGA, delay, process variation, yield, tuning
59	Deming Chen, Jason Cong, Junjuan Xu	Optimal module and voltage assignment for low-power.	ASP-DAC	2005	DBLP DOI BibTeX RDF
56	Sherif A. Tawfik, Volkan Kursun	Dual signal frequencies and voltage levels for low power and temperature-gradient tolerant clock distribution.	ISLPED	2007	DBLP DOI BibTeX RDF	dual-Vth, supply voltage scaling, temperature variations, clock skew, frequency scaling, dual-VDD
51	Bruce Tseng, Hung-Ming Chen	Blockage and voltage island-aware dual-vdd buffered tree construction under fixed buffer locations.	ISPD	2008	DBLP DOI BibTeX RDF	voltage island architecture, low power, buffer insertion
44	Shouyi Yin, Jiangyuan Gu, Dajiang Liu, Leibo Liu, Shaojun Wei	Joint Modulo Scheduling and Vdd Assignment for Loop Mapping on Dual- Vdd CGRAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2016	DBLP DOI BibTeX RDF
44	Bin Liu 0007, Yici Cai, Qiang Zhou 0001, Xianlong Hong	Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs.	ASP-DAC	2006	DBLP DOI BibTeX RDF
40	Saihua Lin, Huazhong Yang, Rong Luo	A New Family of Sequential Elements With Built-in Soft Error Tolerance for Dual-VDD Systems.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
40	Mihir R. Choudhury, Quming Zhou, Kartik Mohanram	Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques.	ICCAD	2006	DBLP DOI BibTeX RDF
40	Jinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh, Yuan-Hua Chu	Design of STR level converters for SoCs using the multi-island dual-VDD design technique.	ISCAS	2006	DBLP DOI BibTeX RDF
34	Sherif A. Tawfik, Volkan Kursun	Low-Power Low-Voltage Hot-Spot Tolerant Clocking with Suppressed Skew.	ISCAS	2007	DBLP DOI BibTeX RDF
34	Sherif A. Tawfik, Volkan Kursun	Dual-V_DD Clock Distribution for Low Power and Minimum Temperature Fluctuations Induced Skew.	ISQED	2007	DBLP DOI BibTeX RDF
32	Yan Lin 0001, Fei Li 0003, Lei He 0001	Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability.	FPGA	2005	DBLP DOI BibTeX RDF	FPGA power model, Vdd programmability, low power, FPGA architecture, dual-Vdd
30	Somsubhra Mondal, Seda Ogrenci Memik	Power Optimization Techniques for SRAM-Based FPGAs.	FPL	2006	DBLP DOI BibTeX RDF
30	Kazuei Hironaka, Hideharu Amano	Power Centric Application Mapping for Dynamically Reconfigurable Processor Array with Dual Vdd and Dual Vth.	ReConFig	2011	DBLP DOI BibTeX RDF
30	Kun-Lin Tsai, Szu-Wei Chaung, Feipei Lai, Shanq-Jang Ruan	A low power scheduling method using dual Vdd and dual Vth.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
30	Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh	Low-power dual Vth pseudo dual Vdd domino circuits.	SBCCI	2004	DBLP DOI BibTeX RDF	NMOS pull-up, low power, domino logic, dual supply voltages, dual threshold voltages
25	Bo Liu 0019, Anfeng Xue, Ziyu Wang, Na Xie, Xuetao Wang, Zhen Wang 0019, Hao Cai	A Reconfigurable Approximate Computing Architecture With Dual-VDD for Low-Power Binarized Weight Network Deployment.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
25	Abhay S. Vidhyadharan, Kasthuri Bha, Sanjay Vidhyadharan	CNFET-Based Ultra-Low-Power Dual-VDD Ternary Half Adder.	Circuits Syst. Signal Process.	2021	DBLP DOI BibTeX RDF
25	Abhay S. Vidhyadharan, Sanjay Vidhyadharan	An ultra-low-power CNFET based dual VDD ternary dynamic Half Adder.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
25	Ching-Hwa Cheng, Tang-Chieh Liu	Digitalized-Management Voltage-Domain Programmable Mechanisms for Dual-Vdd Low-Power Embedded Digital Systems.	DDECS	2019	DBLP DOI BibTeX RDF
25	François Stas, David Bol	Integration of level shifting in a TSPC flip-flop for low-power robust timing closure in dual-Vdd ULV circuits.	ISCAS	2017	DBLP DOI BibTeX RDF
25	Kaijian Yuan, Xingming Zhang 0002	Low power mapping optimization of loops for dual-Vdd CGRAs.	ASICON	2017	DBLP DOI BibTeX RDF
25	Ming Chen, Po-Tsang Huang, Shang-Lin Wu, Wei Hwang, Ching-Te Chuang	Area-power-efficient 11-bit hybrid dual-Vdd ADC with self-calibration for neural sensing application.	SoCC	2016	DBLP DOI BibTeX RDF
25	Hua Xiang 0001, Lakshmi N. Reddy, Haifeng Qian, Ching Zhou, Yu-Shiang Lin, Fanchieh Yee, Andrew Sullivan, Pong-Fei Lu	Gate movement for timing improvement on row based Dual-VDD designs.	ISQED	2016	DBLP DOI BibTeX RDF
25	Bing Xu, Shouyi Yin, Leibo Liu, Shaojun Wei	Low-Power Loop Parallelization onto CGRA Utilizing Variable Dual VDD.	IEICE Trans. Inf. Syst.	2015	DBLP DOI BibTeX RDF
25	Bing Xu, Shouyi Yin, Leibo Liu, Shaojun Wei	Low-power loop pipelining mapping onto CGRA utilizing variable dual VDD.	MWSCAS	2014	DBLP DOI BibTeX RDF
25	Hua Xiang 0001, Haifeng Qian, Ching Zhou, Yu-Shiang Lin, Fanchieh Yee, Andrew Sullivan, Pong-Fei Lu	Row Based Dual-VDD Island Generation and Placement.	DAC	2014	DBLP DOI BibTeX RDF
25		Row-Based Dual Vdd Assignment, for a Level Converter Free CSA Design and Its Near-Threshold Operation.	CoRR	2013	DBLP BibTeX RDF
25	Jianfeng Zhu 0001, Leibo Liu, Shouyi Yin, Shaojun Wei	Low-Power Reconfigurable Processor Utilizing Variable Dual VDD.	IEEE Trans. Circuits Syst. II Express Briefs	2013	DBLP DOI BibTeX RDF
25	Insup Shin, Seungwhun Paik, Dongwan Shin, Youngsoo Shin	HLS-dv: A High-Level Synthesis Framework for Dual-Vdd Architectures.	IEEE Trans. Very Large Scale Integr. Syst.	2012	DBLP DOI BibTeX RDF
25	Haiqi Wang, Sheqin Dong, Tao Lin, Song Chen 0001, Satoshi Goto	Novel Voltage Choice and Min-Cut Based Assignment for Dual-VDD System.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2012	DBLP DOI BibTeX RDF
25	Jianfeng Zhu 0001, Dong Wu, Yaru Yan, Xiao Yu, Hu He 0001, Liyang Pan	A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only).	FPGA	2011	DBLP DOI BibTeX RDF
25	Qing Gao, Orly Yadid-Pecht	Dual VDD block based CMOS image sensor - preliminary evaluation.	ISCAS	2011	DBLP DOI BibTeX RDF
25	Joseph F. Ryan 0002, Benton H. Calhoun	A sub-threshold FPGA with low-swing dual-VDD interconnect in 90nm CMOS.	CICC	2010	DBLP DOI BibTeX RDF
25	Thomas Schweizer, Julio A. de Oliveira Filho, Tommy Kuhn, Wolfgang Rosenstiel	Low Energy Voltage Dithering in Dual VDD Circuits.	PATMOS	2009	DBLP DOI BibTeX RDF
25	Prasanth Mangalagiri, Vijaykrishnan Narayanan	Lifetime Reliability Aware Design Flow Techniques for Dual-Vdd Based Platform FPGAs.	ISVLSI	2009	DBLP DOI BibTeX RDF
25	King Ho Tam, Yu Hu 0002, Lei He 0001, Tom Tong Jing, Xinyi Zhang	Dual-Vdd Buffer Insertion for Power Reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
25	Yici Cai, Bin Liu 0007, Qiang Zhou 0001, Xianlong Hong	Voltage Island Generation in Cell Based Dual-Vdd Design.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2007	DBLP DOI BibTeX RDF
25	Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi, Koji Nii, Hiroshi Kawaguchi 0001, Masahiko Yoshimoto	Area Comparison between 6T and 8T SRAM Cells in Dual-Vdd Scheme and DVS Scheme.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2007	DBLP DOI BibTeX RDF
25	Sarvesh H. Kulkarni, Dennis Sylvester	Power Distribution Techniques for Dual VDD Circuits.	J. Low Power Electron.	2006	DBLP DOI BibTeX RDF
25	Yan Lin 0001, Yu Hu 0002, Lei He 0001, Vijay Raghunat	An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction.	ISLPED	2006	DBLP DOI BibTeX RDF	time slack, FPGA, low power
25	Rajarshi Mukherjee, Seda Ogrenci Memik	Evaluation of dual VDD fabrics for low power FPGAs.	ASP-DAC	2005	DBLP DOI BibTeX RDF
25	Sarvesh H. Kulkarni, Dennis Sylvester	High performance level conversion for dual VDD design.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
25	Robert Bai, Dennis Sylvester	Analysis and design of level-converting flip-flops for dual-Vdd/Vth integrated circuits.	SoC	2003	DBLP DOI BibTeX RDF
19	Behnam Ghavami, Mehrshad Khosraviani, Hossein Pedram	Power Optimization of Asynchronous Circuits through Simultaneous Vdd and Vth Assignment and Template Sizing.	DSD	2008	DBLP DOI BibTeX RDF
15	Prateek Mishra, Anish Muttreja, Niraj K. Jha	Low-power FinFET circuit synthesis using multiple supply and threshold voltages.	ACM J. Emerg. Technol. Comput. Syst.	2009	DBLP DOI BibTeX RDF	Low-power, linear programming, synthesis, TCMS
15	Anish Muttreja, Prateek Mishra, Niraj K. Jha	Threshold Voltage Control through Multiple Supply Voltages for Power-Efficient FinFET Interconnects.	VLSI Design	2008	DBLP DOI BibTeX RDF
15	Liangpeng Guo, Yici Cai, Qiang Zhou 0001, Xianlong Hong	Logic and Layout Aware Voltage Island Generation for Low Power Design.	ASP-DAC	2007	DBLP DOI BibTeX RDF