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Publication years (Num. hits)
1973-1986 (15) 1987-1991 (19) 1992-1993 (15) 1994-1995 (15) 1996-1998 (32) 1999 (17) 2000-2001 (24) 2002 (18) 2003-2004 (35) 2005 (18) 2006 (16) 2007 (15) 2008-2009 (20) 2010-2017 (15) 2018-2023 (18) 2024 (2)
Publication types (Num. hits)
article(96) inproceedings(198)
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The graphs summarize 300 occurrences of 223 keywords

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Found 294 publication records. Showing 294 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
128Robert J. Carragher, Masahiro Fujita, Chung-Kuan Cheng Simple tree-construction heuristics for the fanout problem . Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF tree-construction heuristics, fanout problem, fanout delay, buffer fanout trees, technology mapped network, gate-transformation, LT-tree construction technique, delays, combinational circuits, trees (mathematics), critical paths, logical functions
121Behnam Amelifard, Farzan Fallah, Massoud Pedram Low-power fanout optimization using MTCMOS and multi-Vt techniques. Search on Bibsonomy ISLPED The full citation details ... 2006 DBLP  DOI  BibTeX  RDF buffer chain, fanout tree, low-power design, fanout optimization
121Irith Pomeranz, Zvi Kohavi The minimum test set problem for circuits with nonreconvergent fanout. Search on Bibsonomy J. Electron. Test. The full citation details ... 1991 DBLP  DOI  BibTeX  RDF minimum test set size problem, nonreconvergent fanout circuits, restricted fanout circuits, Labeling algorithms
117Kanwar Jit Singh, Alberto L. Sangiovanni-Vincentelli A Heuristic Algorithm for the Fanout Problem. Search on Bibsonomy DAC The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
113David S. Kung 0001 A Fast Fanout Optimization Algorithm for Near-Continuous Buffer Libraries. Search on Bibsonomy DAC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF logic synthesis, gate-sizing, fanout optimization
109Shiy Xu, E. Edirisuriya A New Way of Detecting Reconvergent Fanout Branch Pairs in Logic Circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 2004 DBLP  DOI  BibTeX  RDF Fanout branch, Reconvergence, Testability, Testable Design, Fanout
106John P. Hayes Enumeration of Fanout-Free Boolean Functions. Search on Bibsonomy J. ACM The full citation details ... 1976 DBLP  DOI  BibTeX  RDF
97Behnam Amelifard, Farzan Fallah, Massoud Pedram Low-power fanout optimization using multiple threshold voltage inverters. Search on Bibsonomy ISLPED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF buffer chain, fanout tree, low-power design, fanout optimization
94Behnam Amelifard, Farzan Fallah, Massoud Pedram Low-Power Fanout Optimization Using Multi Threshold Voltages and Multi Channel Lengths. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
82Satish Verma, Wei Tsang Ooi Controlling Gossip Protocol Infection Pattern Using Adaptive Fanout. Search on Bibsonomy ICDCS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
82Rajeev Murgai Efficient global fanout optimization algorithms. Search on Bibsonomy ASP-DAC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
82Pasquale Cocchini, Massoud Pedram Fanout optimization using bipolar LT-trees. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
82Rajeev Murgai On the global fanout optimization problem. Search on Bibsonomy ICCAD The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
78Tsung-Lin Lee, Chun-Yao Wang Recognition of Fanout-free Functions. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF state of the art method, fanout free functions, equivalent function, Boolean function, factoring, logic minimization
70Zaifu Zhang, Robert D. McLeod, Gregory E. Bridges Statistical estimation of delay fault detectabilities and fault grading. Search on Bibsonomy J. Electron. Test. The full citation details ... 1996 DBLP  DOI  BibTeX  RDF transition delay and path delay faults, statistical delay fault analysis, fault detectabilities, fault coverage, random patterns
70Yang Wang 0014, Hung Q. Ngo 0001, Xiaohong Jiang 0001 Strictly Nonblocking Function-Cast d-Ary Multi-Log Networks under Fanout and Crosstalk Constraints. Search on Bibsonomy ICC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
70Peyman Rezvani, Massoud Pedram A fanout optimization algorithm based on the effort delay model. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
66Jwu E. Chen, Chung-Len Lee 0001, Wen-Zen Shen, Beyin Chen Fanout fault analysis for digital logic circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF fanout fault analysis, digital logic circuits, combinational benchmark circuits, sequential benchmark circuits, target faults, fault diagnosis, logic testing, test generation, sequential circuits, combinational circuits, fault simulation, fault collapsing
62Zaifu Zhang, Robert D. McLeod, Gregory E. Bridges Statistical estimation of delay fault detectabilities and fault grading. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF delay fault detectabilities, fault grading, STAFAN, transition observabilities, fanout stems, fanout free region, gate line transition controllabilities, VLSI, fault diagnosis, logic testing, logic testing, statistical analysis, fault coverage, benchmark circuits, statistical estimation
59Qiushuang Zhang, Ian G. Harris Partial BIST insertion to eliminate data correlation. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
59Qiushuang Zhang, Ian G. Harris Partial BIST insertion to eliminate data correlation. Search on Bibsonomy ICCAD The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
59Qinghua Liu, Malgorzata Marek-Sadowska Wire length prediction-based technology mapping and fanout optimization. Search on Bibsonomy ISPD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF prediction, congestion, wire length
59Sudhakar M. Reddy, Irith Pomeranz, Huaxing Tang, Seiji Kajihara, Kozo Kinoshita On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout. Search on Bibsonomy ITC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
59Matthew M. Ziegler, Mircea Stan Optimal logarithmic adder structures with a fanout of two for minimizing the area-delay product. Search on Bibsonomy ISCAS (2) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
59Abdel Aziz Farrag, Robert J. Dawson, Qi Yao On Designing Fault-Tolerant Extensions With Optimal Fanout For Complete Bipartite Networks. Search on Bibsonomy PARLE The full citation details ... 1992 DBLP  DOI  BibTeX  RDF
55Xinmiao Zhang, Keshab K. Parhi High-speed architectures for parallel long BCH encoders. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF BCH, critical loop, iteration bound, parallel processing, encoder, linear feedback shift register, retiming, unfolding, fanout, generator polynomial
54Haikun Zhu, Yi Zhu 0002, Chung-Kuan Cheng, David M. Harris An Interconnect-Centric Approach to Cyclic Shifter Design Using Fanout Splitting and Cell Order Optimization. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF 64 bit, interconnect-centric approach, fanout splitting, cell order optimization, logarithmic cyclic shifter design, demultiplexers, shifting path, nonshifting paths, accumulated wire load, switching probabilities, integer linear programming
54Man-Fai Yu, Wayne Wei-Ming Dai Single-layer fanout routing and routability analysis for Ball Grid Arrays. Search on Bibsonomy ICCAD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF package routing, ball grid array, pin grid array, planar routing, even wiring, fanout routing, routability
47Balakrishnan Krishnamurthy A Dynamic Programming Approach to the Test Point Insertion Problem. Search on Bibsonomy DAC The full citation details ... 1987 DBLP  DOI  BibTeX  RDF
47Anand Pappu, Alyssa B. Apsel Demonstration of latency reduction in electrical interconnections using optical fanout. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
43Nikolai Ryzhenko, Oleg Venger A practical repeater insertion flow. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2008 DBLP  DOI  BibTeX  RDF physical design, buffer insertion, fanout optimization, topology generation
43Tsutomu Sasao, Kozo Kinoshita On the Number of Fanout-Free Functions and Unate Cascade Functions. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1979 DBLP  DOI  BibTeX  RDF disjunctive networks, enumeration of equivalence classes, enumeration of switching functions, fanout-free function, Cascade, threshold function, unate function
43Edward A. Bender, Jon T. Butler Asymptotic Aproximations for the Number of Fanout-Free Functions. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1978 DBLP  DOI  BibTeX  RDF fanout-free networks, function enumeration, switching functions, cascades, Asymptotic approximations, combinatorial logic
35Rajesh Garg, Sunil P. Khatri A novel, highly SEU tolerant digital circuit design approach. Search on Bibsonomy ICCD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
35Zhong-Zhen Wu, Shih-Chieh Chang Multiple wire reconnections based on implication flow graph. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF global flow optimization (GFO), implication flow graph (IFG), mandatory assignment, multiple wire reconnection, redundant wire, Automatic test pattern generation (ATPG)
35H. V. Jagadish, Beng Chin Ooi, Kian-Lee Tan, Quang Hieu Vu, Rong Zhang 0002 Speeding up search in peer-to-peer networks with a multi-way tree structure. Search on Bibsonomy SIGMOD Conference The full citation details ... 2006 DBLP  DOI  BibTeX  RDF multi-way tree structure, peer-to-peer, system architecture
35Xinmiao Zhang, Keshab K. Parhi High-Speed Architectures for Parallel Long BCH Encoders. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
35Miroslav N. Velev Exploiting Signal Unobservability for Efficient Translation to CNF in Formal Verification of Microprocessors. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
35Aiguo Lu, Guenter Stenz, Frank M. Johannes Technology Mapping for Minimizing Gate and Routing Area. Search on Bibsonomy DATE The full citation details ... 1998 DBLP  DOI  BibTeX  RDF Routing, Technology Mapping, Area Optimization
35Michael G. McNamer, H. Troy Nagle ITA: An algorithm for IDDQ testability analysis. Search on Bibsonomy J. Electron. Test. The full citation details ... 1996 DBLP  DOI  BibTeX  RDF integrated circuit testing, testability analysis, I DDQ testing, leakage faults
35Rajendra V. Boppana, Rajesh Boppana, Suresh Chalasani Designing SANs to Support Low-Fanout Multicasts. Search on Bibsonomy HiPC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
35I-Min Liu, Adnan Aziz Delay Constrained Optimization by Simultaneous Fanout Tree Construction, Buffer Insertion/Sizing and Gate Sizing. Search on Bibsonomy ICCD The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
35Wen-Ben Jone, Patrick H. Madden Multiple fault testing using minimal single fault test set for fanout-free circuits. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
35Uwe Hinsberger, Reiner Kolla A cell-based approach to performance optimization of fanout-free circuits. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1992 DBLP  DOI  BibTeX  RDF
31Narendra K. Singhal, Laxman H. Sahasrabuddhe, Biswanath Mukherjee Optimal multicasting of multiple light-trees of different bandwidth granularities in a WDM mesh network with sparse splitting capabilities. Search on Bibsonomy IEEE/ACM Trans. Netw. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF light-tree, mixed integar linear program (MILP), optical crossconnect, optical crossconnect (OXC), splitter fanout, optimization, multicasting, optical network, mesh network, wavelength-division multiplexing (WDM), lightpath, grooming
31Glenn Jennings Accurate ternary-valued compiled logic simulation of complex logic networks by OTDD composition. Search on Bibsonomy Annual Simulation Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF circuit diagrams, ternary-valued compiled logic simulation, complex logic networks, OTDD composition, combinational U inaccuracies, reconvergent fanout, Kleenean strong ternary logic, Ordered Ternary Decision Diagram, standard ISCAS 85 benchmarks, performance evaluation, logic CAD, digital simulation, circuit analysis computing, ternary logic, incompletely-specified functions
31Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell Statistical methods for delay fault coverage analysis. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF delay fault coverage analysis, true value simulation, multi-value logic system, implicit random path sampling procedure, linear-time estimate, fault coverage estimates, longest path theorem, fanout branches, fault diagnosis, logic testing, delays, probability, statistical analysis, observabilities, multivalued logic, propagation delay, detection probabilities, statistical techniques, transition probabilities
31Joydeep Ghosh, Sajal K. Das 0001, Ajita John Concurrent Processing of Linearly Ordered Data Structures on Hypercube Multicomputers. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF concurrentprocessing, linearly ordered data structures, concurrentmanipulation, augmented binomial search tree, pruned binomial tree, arbitrary processor node, consecutive nodes, nonoverlappingprocessor lists, intermediate-levelimage processing algorithms, dictionary operations, low-level image processingalgorithms, Gray code embedding, distributed memorymulticomputers, parallel algorithms, parallel programming, broadcast, hypercube networks, trees (mathematics), distributed memory systems, search problems, merge, tree data structures, search trees, k-ary n-cubes, concurrent data structure, hypercube multicomputers, local information, fanout, hypercube systems
23Adam Silberstein, Jeff Terrace, Brian F. Cooper, Raghu Ramakrishnan 0001 Feeding frenzy: selectively materializing users' event feeds. Search on Bibsonomy SIGMOD Conference The full citation details ... 2010 DBLP  DOI  BibTeX  RDF social networks, view maintenance
23Michael Scheutzow, Martin Reisslein, Martin Maier 0001, Patrick Seeling Multicast Capacity of Packet-Switched Ring WDM Networks. Search on Bibsonomy IEEE Trans. Inf. Theory The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
23Gregory V. Chockler, Roie Melamed, Yoav Tock, Roman Vitenberg Constructing scalable overlays for pub-sub with many topics. Search on Bibsonomy PODC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF peer-to-peer, overlay networks, optimization problems, application-level multicast, pub/sub
23Stephen J. Hegner The complexity of embedded axiomatization for a class of closed database views. Search on Bibsonomy Ann. Math. Artif. Intell. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF complexity, database, view
23Michael Scheutzow, Patrick Seeling, Martin Maier 0001, Martin Reisslein Multicast capacity of packet-switched ring WDM networks. Search on Bibsonomy INFOCOM The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
23Miroslav N. Velev Efficient translation of boolean formulas to CNF in formal verification of microprocessors. Search on Bibsonomy ASP-DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
23Yuichi Sato, Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu Failure Analysis of Open Faults by Using Detecting/Un-detecting Information on Tests. Search on Bibsonomy Asian Test Symposium The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
23Xiaoqing Wen, Tokiharu Miyoshi, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita On per-test fault diagnosis using the X-fault model. Search on Bibsonomy ICCAD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
23Shrirang K. Karandikar, Sachin S. Sapatnekar Logical effort based technology mapping. Search on Bibsonomy ICCAD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
23Bassam Shaer, Kailash Aurangabadkar, Nitin Agarwal Testable Sequential Circuit Design: Partitioning for Pseudoexhaustive Test. Search on Bibsonomy ISVLSI The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
23Randy Huang, John Wawrzynek, André DeHon Stochastic, spatial routing for hypergraphs, trees, and meshes. Search on Bibsonomy FPGA The full citation details ... 2003 DBLP  DOI  BibTeX  RDF spatial routing, FPGA, reconfigurable computing, detail routing
23Guy G. Lemieux, David M. Lewis Circuit design of routing switches. Search on Bibsonomy FPGA The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
23Alexandre F. Tenca, Syed Ubaid Hussaini A Design of Radix-2 On-line Division Using LSA Organization. Search on Bibsonomy IEEE Symposium on Computer Arithmetic The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
23Jason Cong, Kenneth Yan Synthesis for FPGAs with embedded memory blocks. Search on Bibsonomy FPGA The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
23Haluk Konuk Voltage- and current-based fault simulation for interconnect open defects. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
23Ki-Wook Kim, Sung-Mo Kang, TingTing Hwang, C. L. Liu 0001 Logic Transformation for Low Power Synthesis. Search on Bibsonomy DATE The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
23Priyank Kalla, Maciej J. Ciesielski Performance Driven Resynthesis by Exploiting Retiming-Induced State Register Equivalence. Search on Bibsonomy DATE The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
23Anurag Acharya 0001, Huican Zhu, Kai Shen Adaptive Algorithms for Cache-Efficient Trie Search. Search on Bibsonomy ALENEX The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
23Savithri Sundareswaran, David T. Blaauw, Abhijit Dharchoudhury A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing Analysis. Search on Bibsonomy VLSI Design The full citation details ... 1999 DBLP  DOI  BibTeX  RDF spice verification, primary-path, secondary-path, timing analysis, assertion, assertibility
23Subhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell A Complete Characterization of Path Delay Faults through Stuck-at Faults. Search on Bibsonomy VLSI Design The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
23S. Turgis, Daniel Auvergne A novel macromodel for power estimation in CMOS structures. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
23Daniel R. Brasen, Gabriele Saucier Using cone structures for circuit partitioning into FPGA packages. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
23Emil S. Ochotta, Patrick J. Crotty, Charles R. Erickson, Chih-Tsung Huang, Rajeev Jayaraman, Richard C. Li, Joseph D. Linoff, Luan Ngo, Hy V. Nguyen, Kerry M. Pierce, Douglas P. Wieland, Jennifer Zhuang, Scott S. Nance A Novel Predictable Segmented FPGA Routing Architecture. Search on Bibsonomy FPGA The full citation details ... 1998 DBLP  DOI  BibTeX  RDF FPGA, routing, programmable logic
23Jason Cong, Songjie Xu Technology Mapping for FPGAs with Embedded Memory Blocks. Search on Bibsonomy FPGA The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
23Dirk Stroobandt, Jan Van Campenhout Hierarchical Test Generation with Built-In Fault Diagnosis. Search on Bibsonomy Asian Test Symposium The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Hierarchical Test Pattern Generation, Fault Diagnosis, Test Compaction
23Noel Menezes, Satyamurthy Pullela, Florentin Dartu, Lawrence T. Pillage RC interconnect synthesis-a moment fitting approach. Search on Bibsonomy ICCAD The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
23Fadi Maamari, Janusz Rajski The dynamic reduction of fault simulation. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
23Andrew T. Yang, Yu-Hsu Chang, Daniel G. Saab, Ibrahim N. Hajj Switch-level timing simulation of bipolar ECL circuits. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
23Warren H. Debany Jr., Carlos R. P. Hartmann Bounds on the sizes of irredundant test sets and sequences for combinational logic networks. Search on Bibsonomy J. Electron. Test. The full citation details ... 1991 DBLP  DOI  BibTeX  RDF Digital logic testing, irredundant tests, test complexity, test counting
23Jwu E. Chen, Chung-Len Lee 0001, Wen-Zen Shen Checkpoints in irredundant two-level combinational circuits. Search on Bibsonomy J. Electron. Test. The full citation details ... 1991 DBLP  DOI  BibTeX  RDF
23Sujit Dey, Franc Brglez, Gershon Kedem Corolla Based Circuit Partitioning and Resynthesis. Search on Bibsonomy DAC The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
23Sreejit Chakravarty On the complexity of computing tests for CMOS gates. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1989 DBLP  DOI  BibTeX  RDF
23Danny C. C. Ko, Melvin A. Breuer The design of self-checking multi-output combinational circuits. Search on Bibsonomy AFIPS National Computer Conference The full citation details ... 1977 DBLP  DOI  BibTeX  RDF
23Esfandiar Esmaieli, Ali Peiravi, Yasser Sedaghat An Effective Fanout-Based Method for Improving Error Propagation Probability Estimation in Combinational Circuits. Search on Bibsonomy IEEE Access The full citation details ... 2024 DBLP  DOI  BibTeX  RDF
23Dewmini Sudara Marakkalage, Giovanni De Micheli Fanout-Bounded Logic Synthesis for Emerging Technologies. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2024 DBLP  DOI  BibTeX  RDF
23Stephen A. Fenner, Rabins Wosti Implementing the quantum fanout operation with simple pairwise interactions. Search on Bibsonomy Quantum Inf. Comput. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
23Dewmini Sudara Marakkalage, Giovanni De Micheli Fanout-Bounded Logic Synthesis for Emerging Technologies - A Top-Down Approach. Search on Bibsonomy DATE The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
23Haiyun Li, Jixin Zhang, Ning Xu 0006, Mingyu Liu FanoutNet: A Neuralized PCB Fanout Automation Method Using Deep Reinforcement Learning. Search on Bibsonomy AAAI The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
23Raja Swaminathan, Michael J. Schulte, Brett Wilkerson, Gabriel H. Loh, Alan Smith, Norman James AMD InstinctTM MI250X Accelerator enabled by Elevated Fanout Bridge Advanced Packaging Architecture. Search on Bibsonomy VLSI Technology and Circuits The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
23Masanori Takahashi, Tsubasa Sasaki, Ryuichi Sugizaki, Yoshihiro Arashitani 4-Core Fiber Narrow Pitch Fanout Comprised of Tapered High-Δ MCF. Search on Bibsonomy OFC The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
23Xuliang Zhu, Ruofei Tang, Lei Chen 0002, Xing Li, Xin Huang, Mingxuan Yuan, Weihua Sheng, Jianliang Xu A Database Dependent Framework for K-Input Maximum Fanout-Free Window Rewriting. Search on Bibsonomy DAC The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
23Jim Plusquellic Shift Register, Reconvergent-Fanout (SiRF) PUF Implementation on an FPGA. Search on Bibsonomy Cryptogr. The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
23Stephen A. Fenner, Rabins Wosti Implementing the fanout operation with simple pairwise interactions. Search on Bibsonomy CoRR The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
23Nafis Irtija, Eirini-Eleni Tsiropoulou, Cyrus Minwalla, Jim Plusquellic True Random Number Generation with the Shift-register Reconvergent-Fanout (SiRF) PUF. Search on Bibsonomy HOST The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
23M. Rahimi, M. B. Ghaznavi-Ghoushchi A fanout-improved Parallel Prefix Adder with full-swing PTL cells and Graded Bit Efficiency. Search on Bibsonomy Microelectron. J. The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
23Andrew Y. Guo, Abhinav Deshpande, Su-Kuan Chu, Zachary Eldredge, Przemyslaw Bienias, Dhruv Devulapalli, Yuan Su, Andrew M. Childs, Alexey V. Gorshkov Implementing a Fast Unbounded Quantum Fanout Gate Using Power-Law Interactions. Search on Bibsonomy CoRR The full citation details ... 2020 DBLP  BibTeX  RDF
23V. I. Kopp, J. Park, J. Singer, Dan Neugroschl, Andy Gillooly Low Return Loss Multicore Fiber-Fanout Assembly for SDM and Sensing Applications. Search on Bibsonomy OFC The full citation details ... 2020 DBLP  BibTeX  RDF
23Maxim Ladnushkin Flip-flops fanout splitting in scan designs. Search on Bibsonomy ITC The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
23Shungeng Zhang, Qingyang Wang 0001, Yasuhiko Kanemasa, Jianshu Liu, Calton Pu DoubleFaceAD: A New Datastore Driver Architecture to Optimize Fanout Query Performance. Search on Bibsonomy Middleware The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
23He-Teng Zhang, Jie-Hong R. Jiang SFO: A Scalable Approach to Fanout-Bounded Logic Synthesis for Emerging Technologies. Search on Bibsonomy DAC The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
23Md. Adnan Zaman, Srinivas Katkoori Minimizing Performance and Energy Overheads Due to Fanout In Memristor based Logic Implementations. Search on Bibsonomy VLSI-SoC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
23Md. Adnan Zaman, Rajeev Joshi, Srinivas Katkoori Optimizing Performance and Energy Overheads Due to Fanout in In-Memory Computing Systems. Search on Bibsonomy VLSI-SoC (Selected Papers) The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
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