Search results for "fanouts"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
52	Ming-Syan Chen, Kun-Lung Wu, Philip S. Yu	Optimizing Index Allocation for Sequential Data Broadcasting in Wireless Mobile Computing.	IEEE Trans. Knowl. Data Eng.	2003	DBLP DOI BibTeX RDF	Wireless mobile computing, sequential broadcasting, indexing, energy saving
52	Yong Chang Kim, Kewal K. Saluja, Vishwani D. Agrawal	Combinational Test Generation for Acyclic SequentialCircuits using a Balanced ATPG Model.	VLSI Design	2001	DBLP DOI BibTeX RDF
50	Wen Ching Wu, Chung-Len Lee 0001, Jwu E. Chen	Identification of robust untestable path delay faults.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	robust untestable path delay faults, path reconvergence of fanouts, ISCAS 85' circuits, total path delay faults, six-valued logic, propagation graph, ROUNTEST program, fault diagnosis, logic testing, delays, partitioning, ATPG, combinational circuits, combinational circuits, automatic testing, logic CAD, multivalued logic, logic partitioning, signal flow graphs, fault identification
42	V. I. Kopp, J. Park, J. Singer, Dan Neugroschl, Takahiro Suganuma, Takemi Hasegawa, Takafumi Ohtsuka, Hidehisa Tazawa	Ultra-Low-Loss MCF Fanouts for Submarine SDM Applications.	OFC	2022	DBLP BibTeX RDF
42	Amir Moradi 0001, Mahmoud Salmasizadeh, Mohammad Taghi Manzuri Shalmani	On the Importance of the Number of Fanouts to Prevent the Glitches in DPA-Resistant Devices.	CSICC	2008	DBLP DOI BibTeX RDF
34	Taiga Takata, Yusuke Matsunaga	A heuristic algorithm for LUT-based FPGA technology mapping using the lower bound for DAG covering problem (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, technology mapping
34	Rob A. Rutenbar, Li-C. Wang, Kwang-Ting Cheng, Sandip Kundu	Static statistical timing analysis for latch-based pipeline designs.	ICCAD	2004	DBLP DOI BibTeX RDF
33	Susanta Chakraborty, Debesh Kumar Das, Bhargab B. Bhattacharya	Logical redundancies in irredundant combinational circuits.	J. Electron. Test.	1993	DBLP DOI BibTeX RDF	irredundancy, testing, Boolean functions, combinational circuits, stuck-at faults, fanouts
17	Xiao-dong Sun, Hong-Bin Zhang	A Fast Hole-filling Strategy of 3D Scanned Human Body.	CGIV	2009	DBLP DOI BibTeX RDF
17	Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman	Parallel fault backtracing for calculation of fault coverage.	ASP-DAC	2008	DBLP DOI BibTeX RDF
17	Ratnakar Goyal, Harindranath Parameswaran, Sachin Shrivastava	Computation of Waveform Sensitivity Using Geometric Transforms for SSTA.	ISQED	2008	DBLP DOI BibTeX RDF	Timing Library, Accuracy, SSTA
17	Dong Xiang, Kaiwei Li, Jiaguang Sun, Hideo Fujiwara	Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Scan forest, test application cost, test data volume, test power
17	Haikun Zhu, Yi Zhu 0002, Chung-Kuan Cheng, David M. Harris	An Interconnect-Centric Approach to Cyclic Shifter Design Using Fanout Splitting and Cell Order Optimization.	ASP-DAC	2007	DBLP DOI BibTeX RDF	64 bit, interconnect-centric approach, fanout splitting, cell order optimization, logarithmic cyclic shifter design, demultiplexers, shifting path, nonshifting paths, accumulated wire load, switching probabilities, integer linear programming
17	Sheng Sun, Carl Sechen	Post-layout comparison of high performance 64b static adders in energy-delay space.	ICCD	2007	DBLP DOI BibTeX RDF
17	Chi-Shong Wang, Chingwei Yeh	Performance-driven technology mapping with MSG partition and selective gate duplication.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	gate duplication, maximal super-gate, super-gate, dynamic programming, partition, matching, logic synthesis, directed acyclic graph, Technology mapping, covering
17	Wan-Ping Lee, Hung-Yi Liu, Yao-Wen Chang	Voltage island aware floorplanning for power and timing optimization.	ICCAD	2006	DBLP DOI BibTeX RDF
17	Zhenghao Zhang, Yuanyuan Yang 0001	Performance analysis of k-fold multicast networks.	IEEE Trans. Commun.	2005	DBLP DOI BibTeX RDF
17	Dong Xiang, Kaiwei Li, Hideo Fujiwara	Design for Cost Effective Scan Testing by Reconfiguring Scan Flip-Flops.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
17	Fei Hu, Vishwani D. Agrawal	Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis.	ICCD	2005	DBLP DOI BibTeX RDF
17	Satish Verma, Wei Tsang Ooi	Controlling Gossip Protocol Infection Pattern Using Adaptive Fanout.	ICDCS	2005	DBLP DOI BibTeX RDF
17	Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer	Ring generators - new devices for embedded test applications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
17	Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang	Performance-driven mapping for CPLD architectures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
17	Makram M. Mansour, Mohammad M. Mansour, Amit Mehrotra	Modified Sakurai-Newton Current Model and its Applications to CMOS Digital Circuit Design.	ISVLSI	2003	DBLP DOI BibTeX RDF
17	Dong Xiang, Shan Gu, Hideo Fujiwara	Non-Scan Design for Testability for Mixed RTL Circuits with Both Data Paths and Controller via Conflict Analysis.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
17	Dong Xiang, Hideo Fujiwara	Handling the pin overhead problem of DFTs for high-quality and at-speed tests.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
17	Shi-Yu Huang	Diagnosis Of Byzantine Open-Segment Faults.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
17	Alberto Medina, Nina Taft, Kavé Salamatian, Supratik Bhattacharyya, Christophe Diot	Traffic matrix estimation: existing techniques and new directions.	SIGCOMM	2002	DBLP DOI BibTeX RDF	statistical inference, traffic matrix estimation
17	Mohammad M. Mansour, Naresh R. Shanbhag	Simplified current and delay models for deep submicron CMOS digital circuits.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
17	Aditya D. Sathe, Michael L. Bushnell, Vishwani D. Agrawal	Analog Macromodeling of Capacitive Coupling Faults in Digital Circuit Interconnects.	ITC	2002	DBLP DOI BibTeX RDF
17	Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang	Performance-driven mapping for CPLD architectures.	FPGA	2001	DBLP DOI BibTeX RDF	PLA-style logic cells, FPGA, technology mapping, CPLD, delay optimization
17	Paul Kartschoke, Shervin Hojat	Techniques that Improved the Timing Convergence of the Gekko PowerPC Microprocessor.	ISQED	2001	DBLP DOI BibTeX RDF
17	Shervin Hojat, Paul Kartschoke	Techniques for Improving Timing Convergence of Advanced Microprocessors.	EUROMICRO	2000	DBLP DOI BibTeX RDF
17	Samir Boubezari, Eduard Cerny, Bozena Kaminska, Benoit Nadeau-Dostie	Testability analysis and test-point insertion in RTL VHDL specifications for scan-based BIST.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
17	Tim Menzies, Steve M. Easterbrook, Bashar Nuseibeh, Sam Waugh	An Empirical Investigation of Multiple Viewpoint Reasoning in Requirements Engineering.	RE	1999	DBLP DOI BibTeX RDF
17	Harm Arts, Michel R. C. M. Berkelaar, Koen van Eijk	Computing observability don't cares efficiently through polarization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
17	Chau-Shen Chen, TingTing Hwang	Layout Driven Selection and Chaining of Partial Scan Flip-Flops.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	design for testability, matching, placement, global routing, partial scan, digital testing, layout optimization
17	Tim Menzies, Sam Waugh	On the Practicality of Viewpoint-Based Requirements Engineering.	PRICAI	1998	DBLP DOI BibTeX RDF
17	Supratik Chakraborty, David L. Dill	More Accurate Polynomial-Time Min-Max Timing Simulation.	ASYNC	1997	DBLP DOI BibTeX RDF	Uncertain component delays, min-max timing simulation, thirteen-valued signal algebra, polynomial-time algorithm
17	Harm Arts, Michel R. C. M. Berkelaar, C. A. J. van Eijk	Polarized observability don't cares.	ICCAD	1996	DBLP DOI BibTeX RDF
17	Tapan J. Chakraborty, Vishwani D. Agrawal	Design for high-speed testability of stuck-at faults.	VLSI Design	1996	DBLP DOI BibTeX RDF	design for high-speed testability, stuck-at fault detection, signal transition, timing hazard, multivalue algebra, dh-robust test, sequential feedback, reconvergent fanout, cycle-free sequential circuit, fault diagnosis, logic testing, delays, design for testability, logic design, sequential circuits, partial scan, test generation algorithm, critical path delay
17	Amitava Majumdar 0001, Sarma B. K. Vrudhula	Analysis of signal probability in logic circuits using stochastic models.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF
17	Patrick Kam Lui, Jon C. Muzio	Constrained parity testing.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	compaction testing, parity testing, Built-in self-test, signature analysis
17	Yuzo Takamatsu, Kozo Kinoshita	Extended selection of switching target faults in CONT algorithm for test generation.	J. Electron. Test.	1990	DBLP DOI BibTeX RDF	fault target switching, fault simulation, D-algorithm