Search results for "fault-coverage"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
82	Ameet Bagwe, Rubin A. Parekhji	Functional testing and fault analysis based fault coverage enhancement techniques for embedded core based systems.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	fault coverage enhancement, embedded core based systems, test constraints, Texas Instruments TMS320C27xx, memory wrapper logic, fault diagnosis, logic testing, integrated circuit testing, application specific integrated circuits, functional testing, digital signal processing chips, fault analysis
80	Hailong Cui, Sharad C. Seth, Shashank K. Mehta	Modeling Fault Coverage of Random Test Patterns.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	fault-coverage prediction, cost-benefit analysis of fault simulation, variance of fault coverage, BIST, probabilistic model
74	Albert F. Myers	k-out-of-n: G System Reliability With Imperfect Fault Coverage.	IEEE Trans. Reliab.	2007	DBLP DOI BibTeX RDF
65	Gabriel M. Silberman, Ilan Y. Spillinger	Using functional fault simulation and the difference fault model to estimate implementation fault coverage.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
64	Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas	Statistical path delay fault coverage estimation for synchronous sequential circuits.	VLSI Design	1996	DBLP DOI BibTeX RDF	path delay fault coverage estimation, multi-valued algebra, signal statistics, latch updating, fault diagnosis, logic testing, delays, probability, controllability, controllability, statistical analysis, sequential circuits, observability, observabilities, logic simulation, synchronous sequential circuits, statistical estimation
64	Peter C. Maxwell, Robert C. Aitken	IDDQ testing as a component of a test suite: The need for several fault coverage metrics.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	quality, fault coverage, scan, functional testing, Current testing, physical defects
61	Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell	Statistical methods for delay fault coverage analysis.	VLSI Design	1995	DBLP DOI BibTeX RDF	delay fault coverage analysis, true value simulation, multi-value logic system, implicit random path sampling procedure, linear-time estimate, fault coverage estimates, longest path theorem, fanout branches, fault diagnosis, logic testing, delays, probability, statistical analysis, observabilities, multivalued logic, propagation delay, detection probabilities, statistical techniques, transition probabilities
59	Kwang-Ting Cheng	Transition fault testing for sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
59	Shanrui Zhang, Minsu Choi, Nohpill Park, Fabrizio Lombardi	Probabilistic Balancing of Fault Coverage and Test Cost in Combined Built-In Self-Test/Automated Test Equipment Testing Environment.	DFT	2004	DBLP DOI BibTeX RDF
58	Albert F. Myers, Antoine Rauzy	Efficient Reliability Assessment of Redundant Systems Subject to Imperfect Fault Coverage Using Binary Decision Diagrams.	IEEE Trans. Reliab.	2008	DBLP DOI BibTeX RDF
57	Wangqi Qiu, Xiang Lu, Jing Wang 0006, Zhuo Li 0001, D. M. H. Walker, Weiping Shi	A Statistical Fault Coverage Metric for Realistic Path Delay Faults.	VTS	2004	DBLP DOI BibTeX RDF
57	Yi Zhao, Sujit Dey	Fault-coverage analysis techniques of crosstalk in chip interconnects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
57	Shyue-Kung Lu, Tsung-Ying Lee, Cheng-Wen Wu	Defect Level Prediction Using Multi-Model Fault Coverage.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
57	Von-Kyoung Kim, Tom Chen 0001, Mick Tegethoff	Fault Coverage Estimation for Early Stage of VLSI Design.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
56	Irith Pomeranz, Sudhakar M. Reddy	Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
54	Von-Kyoung Kim, Tom Chen 0001	On comparing functional fault coverage and defect coverage for memory testing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
53	Puneet Gupta 0001, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma	Layout-aware scan chain synthesis for improved path delay fault coverage.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
52	Abdeslam En-Nouaary, Ferhat Khendek, Rachida Dssouli	Fault Coverage in Testing Real-Time Systems.	RTCSA	1999	DBLP DOI BibTeX RDF	Real-Time Systems, Testing, Specification, Implementation, Timed Automata, Fault Coverage
50	Jayant Deodhar, Spyros Tragoudas	Color Counting and its Application to Path Delay Fault Coverage.	ISQED	2001	DBLP DOI BibTeX RDF
49	Sezer Gören 0001, F. Joel Ferguson	Test sequence generation for controller verification and test with high coverage.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	finite state machine, Fault coverage, black box testing, X-machine
49	Sumit Ghosh, Tapan J. Chakraborty	On behavior fault modeling for digital designs.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	fault coverage correlation, fault model, fault simulation, stuck-at fault, behavior model
49	Pradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul	Validation Vector Grade (VVG): A New Coverage Metric for Validation and Test.	VTS	1999	DBLP DOI BibTeX RDF
49	William K. C. Lam, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Delay fault coverage, test set size, and performance trade-offs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
48	Pradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul	A test evaluation technique for VLSI circuits using register-transfer level fault modeling.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
48	Irith Pomeranz, Sudhakar M. Reddy	A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy.	DATE	2008	DBLP DOI BibTeX RDF
48	Albert F. Myers	Achievable Limits on the Reliability of k-out-of-n: G Systems Subject to Imperfect Fault Coverage.	IEEE Trans. Reliab.	2008	DBLP DOI BibTeX RDF
47	Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal	Improving accuracy in path delay fault coverage estimation.	VLSI Design	1996	DBLP DOI BibTeX RDF	fault coverage estimation, simulated vector pair, exact fault simulation, fixed-length path-segments, fan-in branches, fan-out branches, flagged path-segments, segment lengths, combinational paths, graph theory, fault diagnosis, logic testing, delays, combinational circuits, logic CAD, circuit analysis computing, path delay fault, approximate methods, CPU time
47	Dali L. Tao, Carlos R. P. Hartmann	A Novel Concurrent Error Detection Scheme for FFT Networks.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	concurrent error detection scheme, FFT networks, algorithm-based fault tolerancetechniques, digital signalprocessing chips, fault tolerant computing, fast Fourier transforms, error detection, fault coverage, system performance, roundoff errors, round-off errors
47	Yung-Ruei Chang, Suprasad V. Amari, Sy-Yen Kuo	OBDD-Based Evaluation of Reliability and Importance Measures for Multistate Systems Subject to Imperfect Fault Coverage.	IEEE Trans. Dependable Secur. Comput.	2005	DBLP DOI BibTeX RDF	multistate system, importance measure, Reliability, fault-coverage, OBDD
47	V. Prepin, R. David	Fault coverage of a long random test sequence estimated from a short simulation.	VTS	1997	DBLP DOI BibTeX RDF	long random test sequence, short simulation, fault coverage estimation, two-parameter model, fault diagnosis
47	Karim Arabi, Bozena Kaminska	Parametric and Catastrophic Fault Coverage of Analog Circuits in Oscillation-Test Methodology.	VTS	1997	DBLP DOI BibTeX RDF	Oscillation-Test Method, Parametric Fault Coverage, Analog Testing, Mixed-Signal Circuits
47	Marc D. Riedel, Janusz Rajski	Fault coverage analysis of RAM test algorithms.	VTS	1995	DBLP DOI BibTeX RDF	RAM test algorithms, flexible software analysis program, arbitrary test sequences, coverage statistics, functional cell-array faults, fault state transition conditions, representative fault classes, fault diagnosis, integrated circuit testing, fault coverage, random-access storage, integrated memory circuits, semiconductor memories, test algorithms
46	Eun Sei Park, M. Ray Mercer, Thomas W. Williams	The Total Delay Fault Model and Statistical Delay Fault Coverage.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	delay fault model, delay fault coverage, statistical delay fault coverage, defect level model, logic testing, delay testing, delay faults
46	Xia Cai, Michael R. Lyu	The effect of code coverage on fault detection under different testing profiles.	ACM SIGSOFT Softw. Eng. Notes	2005	DBLP DOI BibTeX RDF	software testing, fault detection, code coverage
46	Xia Cai, Michael R. Lyu	The effect of code coverage on fault detection under different testing profiles.	A-MOST	2005	DBLP DOI BibTeX RDF	software testing, fault detection, code coverage
46	Wilfried Daehn	Fault simulation using small fault samples.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	confidence level, sampling, fault simulation, Bayesian estimation
46	Thomas W. Williams, Stephen K. Sunter	How Should Fault Coverage Be Defined?	VTS	2000	DBLP DOI BibTeX RDF
46	Luca Simoncini, Arthur D. Friedman	Incomplete Fault Coverage In Modular Miltiprocessor Systems.	ACM Annual Conference (1)	1978	DBLP DOI BibTeX RDF
45	Deepinder P. Sidhu, Ting-Kau Leung	Formal Methods for Protocol Testing: A Detailed Study.	IEEE Trans. Software Eng.	1989	DBLP DOI BibTeX RDF	NBS Class 4 Transport Protocol, protocol-test-sequence generation techniques, real-world communication protocols, protocols, fault detection, fault coverage, fault coverage, conformance testing, Monte Carlo methods, Monte Carlo simulation, failure analysis, test sequences, protocol implementation, protocol testing
45	Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi	Exact Delay Fault Coverage in Sequential Logic Under Any Delay Fault Model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
45	Xiao Sun 0002, Carmie Hull	Functional Verification Coverage vs. Physical Stuck-at Fault Coverage.	DFT	1998	DBLP DOI BibTeX RDF	functional property, stuck-at fault coverage, verification coverage, UIO, verification, validation, ATPG, FSM, signature analysis, test application time
43	Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas	Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	statistical fault analysis, fault simulation, delay test, path-delay faults, transition faults
43	Zaifu Zhang, Robert D. McLeod, Gregory E. Bridges	Statistical estimation of delay fault detectabilities and fault grading.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	transition delay and path delay faults, statistical delay fault analysis, fault detectabilities, fault coverage, random patterns
43	K. Vijayananda	Distributed fault detection in communication protocols using extended finite state machines.	ICPADS	1996	DBLP DOI BibTeX RDF	distributed fault detection, run-time fault detection, coding defects, memory problems, protocol faults, vocabulary faults, sequencing faults, parallel decomposition method, multiple observers, distributed fault detection mechanism, fault tolerant computing, finite state machines, transport protocols, encoding, communication protocols, fault coverage, extended finite state machines
43	Yuyun Liao, D. M. H. Walker	Optimal voltage testing for physically-based faults.	VTS	1996	DBLP DOI BibTeX RDF	optimal voltage testing, physically-based faults, resistive bridges, gate outputs, pattern sensitive functional faults, transmission gates, fault diagnosis, logic testing, delays, integrated circuit testing, automatic testing, fault coverage, CMOS logic circuits, delay faults, Iddq tests, CMOS circuits, logic gates, test vector, noise margin, selection strategy, low-voltage testing, integrated circuit noise
43	Irith Pomeranz, Sudhakar M. Reddy	Improving the Transition Fault Coverage of Functional Broadside Tests by Observation Point Insertion.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
43	Mukund Sivaraman, Andrzej J. Strojwas	Delay fault coverage: a realistic metric and an estimation technique for distributed path delay faults.	ICCAD	1996	DBLP DOI BibTeX RDF	fabrication process, coverage, delay testing, delay fault, path sensitization
42	Li-C. Wang, M. Ray Mercer, Sophia W. Kao, Thomas W. Williams	On the decline of testing efficiency as fault coverage approaches 100%.	VTS	1995	DBLP DOI BibTeX RDF	single stuck-at fault model, ISCAS benchmark circuits, nontarget defects, fault diagnosis, logic testing, integrated circuit testing, automatic testing, fault coverage, test pattern generation, manufacturing process, test quality, production testing, testing efficiency, circuit sizes
41	Sanghyeon Baeg	Delay Fault Coverage Enhancement by Partial Clocking for Low-Power Designs With Heavily Gated Clocks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
41	Yinan N. Shen, Fabrizio Lombardi, Donatella Sciuto	Evaluation and improvement of fault coverage for verification and validation of protocols.	SPDP	1990	DBLP DOI BibTeX RDF
41	Krishnendu Chakrabarty, John P. Hayes	On the quality of accumulator-based compaction of test responses.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
40	Mitrajit Chatterjee, Dhiraj K. Pradhan	A BIST Pattern Generator Design for Near-Perfect Fault Coverage.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	core logic, built-in self-test, synthesis, fault coverage, Linear feedback shift registers, test pattern generation, scan, SOC
40	Wen-Ben Jone, Yun-Pan Ho, Sunil R. Das	Delay Fault Coverage Enhancement Using Variable Observation Times.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	statistical delay fault coverage, delay test observation times, delay fault testing
40	Mitrajit Chatterjee, Dhiraj K. Pradhan	A novel pattern generator for near-perfect fault-coverage.	VTS	1995	DBLP DOI BibTeX RDF	near-perfect fault-coverage, onchip BIST, GLFSR, logic mapping technique, weighted pattern technique, logic testing, built-in self test, integrated circuit testing, design methodology, combinational circuits, automatic testing, integrated logic circuits, shift registers, combinational logic, digital integrated circuits, pattern generator, single stuck-at fault
39	Michael S. Hsiao	On Non-Statistical Techniques for Fast Fault Coverage Estimation.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	fault coverage estimation, hyperactivity reduction, test generation, fault simulation, tolerance
39	Zhen Chen, Boxue Yin, Dong Xiang	Conflict driven scan chain configuration for high transition fault coverage and low test power.	ASP-DAC	2009	DBLP DOI BibTeX RDF
39	Shianling Wu, Laung-Terng Wang, Zhigang Jiang, Jiayong Song, Boryau Sheu, Xiaoqing Wen, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Ravi Apte	On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs.	DFT	2008	DBLP DOI BibTeX RDF
39	Chen Fu, Richard P. Martin, Kiran Nagaraja, Thu D. Nguyen, Barbara G. Ryder, David Wonnacott	Compiler-Directed Program-Fault Coverage for Highly Available Java Internet Services.	DSN	2003	DBLP DOI BibTeX RDF
39	Dimitrios Kagaris, Spyros Tragoudas, Dimitrios Karayiannis	Improved nonenumerative path-delay fault-coverage estimation based on optimal polynomial-time algorithms.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
38	Bing-Chuan Bai, Augusli Kifli, Chien-Mo James Li, Kun-Cheng Wu	Fault modeling and testing of retention flip-flops in low power designs.	ASP-DAC	2009	DBLP DOI BibTeX RDF
38	Alexandre Petrenko	Fault Model-Driven Test Derivation from Finite State Models: Annotated Bibliography.	MOVEP	2000	DBLP DOI BibTeX RDF
38	Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor, Mike Rodgers	Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	static faults, fault models, fault coverage, memory tests, dynamic faults, fault primitives
38	Vadim Trenkaev, Myungchul Kim 0001, Soonuk Seol	Interoperability Testing Based on a Fault Model for a System of Communicating FSMs.	TestCom	2003	DBLP DOI BibTeX RDF
37	Jien-Chung Lo	Analysis of a BICS-Only Concurrent Error Detection Method.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	unsafe probability, reliability, fault coverage, testability, concurrent error detection, built-in current sensors, operating speed
37	Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal	Compaction-based test generation using state and fault information.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	compaction-based test generation, newly-traversed state information, newly-detected fault information, vector compaction iterations, vector sequence bias, biased vectors, compacted test set extension, intelligent vector selection, state analysis, fault diagnosis, fault detection, sequential circuits, sequential circuits, automatic test pattern generation, iterative methods, vectors, fault coverage, circuit analysis computing, fault analysis, benchmark circuits, computing resources, vector generation
37	André Postma, Gerie Hartman, Thijs Krol	Removal of all Faulty Nodes from a Fault-Tolerant Service by means of Distributed Diagnosis with Imperfect Fault Coverage.	EDCC	1996	DBLP DOI BibTeX RDF
37	Sandip Kundu, Sujit T. Zachariah, Sanjay Sengupta, Rajesh Galivanche	Test Challenges in Nanometer Technologies.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	circuit marginality testing, process marginality testing, defect based testing, path delay testing
36	Warren H. Debany Jr., Kevin A. Kwiat, Sami A. Al-Arian	A Method for Consistent Fault Coverage Reporting.	IEEE Des. Test Comput.	1993	DBLP DOI BibTeX RDF
36	Ad J. van de Goor, Georgi Gaydadjiev, V. G. Mikitjuk, Vyacheslav N. Yarmolik	March LR: a test for realistic linked faults.	VTS	1996	DBLP DOI BibTeX RDF	disturb faults, March LR, March LRD, March LRDD, fault diagnosis, integrated circuit testing, fault models, fault coverage, march tests, integrated memory circuits, semiconductor memories, linked faults
36	C. P. Ravikumar, Gurjeet S. Saund, Nidhi Agrawal	A STAFAN-like functional testability measure for register-level circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	functional testability measure, register-level circuits, testability analysis programs, SCOAP, gate-level digital circuits, testability-driven synthesis, busses, F-STAFAN, Sun/SPARC workstation, performance evaluation, fault diagnosis, logic testing, high-level synthesis, statistical analysis, design for testability, fault simulation, fault coverage, circuit analysis computing, adders, multipliers, multiplexers, digital circuit, shift registers, logic gates, reliability theory, stuck-at fault model
36	Bjørg Reppen, Einar J. Aas	Combined probabilistic testability calculation and compact test generation for PLAs.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	probabilistic testability, Fault coverage, test pattern generation, programmable logic arrays
36	Marie-Lise Flottes, Christian Landrault, A. Petitqueux	Design for sequential testability: an internal state reseeding approach for 100 % fault coverage.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	sequential testability, internal state reseeding, observation points, minimum DFT insertion, non-scan approach, fault efficiency, 100 percent, fault diagnosis, logic testing, controllability, controllability, design for testability, logic design, sequential circuits, automatic test pattern generation, ATPG, observability, fault coverage, flip-flops, at-speed testing, benchmark circuits, CPU time, partial reset
36	Michel Renovell, P. Huc, Yves Bertrand	Bridging fault coverage improvement by power supply control.	VTS	1996	DBLP DOI BibTeX RDF	bridging fault coverage, power supply control, resistance interval, faulty value, VLSI, VLSI, fault diagnosis, logic testing, integrated circuit testing, automatic testing, logic circuits, parametric model, benchmark circuits
36	Surendra Bommu, Srimat T. Chakradhar, Kiran B. Doreswamy	Resource-Constrained Compaction of Sequential Circuit Test Sets.	VLSI Design	2000	DBLP DOI BibTeX RDF
36	Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara	On Test Generation with A Limited Number of Tests.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
36	Margot Karam, Gabriele Saucier	Functional versus random test generation for sequential circuits.	J. Electron. Test.	1993	DBLP DOI BibTeX RDF	simulation, Finite state machine, functional testing, graph traversal
36	Wei Li 0023, Seongmoon Wang, Srimat T. Chakradhar, Sudhakar M. Reddy	Distance Restricted Scan Chain Reordering to Enhance Delay Fault Coverage.	VLSI Design	2005	DBLP DOI BibTeX RDF
36	Shambhu J. Upadhyaya, Kewal K. Saluja	A new approach to the design of built-in self-testing PLAs for high fault coverage.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
35	Hamid R. Zarandi, Seyed Ghassem Miremadi, Ali Reza Ejlali	Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models.	DFT	2003	DBLP DOI BibTeX RDF
35	Dilip Krishnaswamy, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee	SPITFIRE: scalable parallel algorithms for test set partitioned fault simulation.	VTS	1997	DBLP DOI BibTeX RDF	SPITFIRE, scalable parallel algorithms, test set partitioned fault simulation, synchronous parallel algorithms, sequential VLSI circuits, VLSI, fault coverage
35	Joseph L. A. Hughes	Multiple fault detection using single fault test sets.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
35	V. R. Devanathan	Novel Bi-partitioned Scan Architecture to Improve Transition Fault Coverage.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
35	Huan-Chih Tsai, Sudipta Bhawmik, Kwang-Ting Cheng	An almost full-scan BIST solution-higher fault coverage and shorter test application time.	ITC	1998	DBLP DOI BibTeX RDF
35	Heidrun Engel	Data flow transformations to detect results which are corrupted by hardware faults.	HASE	1996	DBLP DOI BibTeX RDF	data flow transformations, corrupt result detection, hardware fault coverage, modified instruction, diverse data representation, modified instruction sequences, assembler level, high language level, fault tolerant computing, software faults, design diversity, hardware fault detection
35	Ajay Khoche, Erik Brunvand	A partial scan methodology for testing self-timed circuits.	VTS	1995	DBLP DOI BibTeX RDF	partial scan methodology, control section testing, macromodule based circuits, sequential network, logic testing, integrated circuit testing, design for testability, logic design, asynchronous circuits, fault coverage, stuck-at faults, integrated logic circuits, boundary scan testing, self-timed circuits
34	Irith Pomeranz, Sudhakar M. Reddy	Low-complexity fault simulation under the multiple observation time and the restricted multiple observation time testing approaches.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
34	Salvador Mir, Adoración Rueda, Diego Vázquez, José Luis Huertas	Switch-Level Fault Coverage Analysis for Switched-Capacitor Systems.	DATE	1998	DBLP DOI BibTeX RDF
34	Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell	Fault coverage estimation by test vector sampling.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
33	Janusz Sosnowski	Improving Fault Coverage in System Tests.	IOLTW	2000	DBLP DOI BibTeX RDF	In system testing, test controllability and observability, fault coverage analysis, on-line monitoring
33	Nan-Cheng Lai, Sying-Jyan Wang, Y.-H. Fu	Low-Power BIST With a Smoother and Scan-Chain Reorder Under Optimal Cluster Size.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
33	Amitava Majumdar 0001, Sarma B. K. Vrudhula	Techniques for estimating test length under random test.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	urn models, test quality, Circuit testing, waiting time distribution
32	Ghassan Al Hayek, Chantal Robach	On the Adequacy of Deriving Hardware Test Data from the Behavioral Specification.	EUROMICRO	1996	DBLP DOI BibTeX RDF	hardware test data, behavioral fault modeling, gate-level strategies, high-level fault detection, gate-level fault detection, design automation tools, generated test set, gate-level fault coverage, hardware description languages, hardware description languages, behavioral specification
32	Michel Renovell, P. Huc, Yves Bertrand	The concept of resistance interval: a new parametric model for realistic resistive bridging fault.	VTS	1995	DBLP DOI BibTeX RDF	electric resistance, resistance interval, intrinsic resistance, logic behavior, 0 to 500 ohm, VLSI, VLSI, fault diagnosis, logic testing, integrated circuit testing, fault detection, automatic testing, fault coverage, bridging faults, parametric model, logic gates, logic gates, resistive bridging fault, faulty behavior
32	Udo Mahlstedt, Jürgen Alt, Matthias Heinitz	CURRENT: a test generation system for IDDQ testing.	VTS	1995	DBLP DOI BibTeX RDF	CURRENT test system, test generation system, scan-based circuits, library-based fault modeling strategy, intra-gate shorts, inter-gate shorts, gate-drain shorts, deterministic test generator, test set compaction technique, fault diagnosis, logic testing, integrated circuit testing, automatic testing, fault simulator, fault coverage, fault location, CMOS logic circuits, bridging faults, boundary scan testing, I/sub DDQ/ testing, test application time reduction, stuck-on faults, leakage faults
32	Vimal K. Reddy, Eric Rotenberg, Sailashri Parthasarathy	Understanding prediction-based partial redundant threading for low-overhead, high- coverage fault tolerance.	ASPLOS	2006	DBLP DOI BibTeX RDF	redundant multithreading, simultaneous multithreading (SMT), slipstream processor, chip multiprocessor (CMP), branch prediction, transient faults, value prediction, time redundancy
32	Zhuo Zhang 0008, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Bashir M. Al-Hashimi	Enhancing Delay Fault Coverage through Low Power Segmented Scan.	ETS	2006	DBLP DOI BibTeX RDF
32	Narendra Devta-Prasanna, Sudhakar M. Reddy, Arun Gunda, P. Krishnamurthy, Irith Pomeranz	Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch Transitions.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
32	Suprasad V. Amari, Hoang Pham, G. Dill	Optimal design of k-out-of-n: G subsystems subjected to imperfect fault-coverage.	IEEE Trans. Reliab.	2004	DBLP DOI BibTeX RDF
32	Irith Pomeranz, Sudhakar M. Reddy	Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
32	Junichi Hirase, Shinichi Yoshimura, Tomohisa Sczaki	Automatic Test Pattern Generation for Improving the Fault Coverage of Microprocessors.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF