Search results for "glitching"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
122	Anand Raghunathan, Sujit Dey, Niraj K. Jha	Register-transfer level estimation techniques for switching activity and power consumption.	ICCAD	1996	DBLP DOI BibTeX RDF	gate-level implementation, register-transfer level estimation, logic design, power consumption, switching activity, glitching, RTL designs
72	Anand Raghunathan, Sujit Dey, Niraj K. Jha	High-level macro-modeling and estimation techniques for switching activity and power consumption.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
66	Janardhan H. Satyanarayana, Keshab K. Parhi	Theoretical analysis of word-level switching activity in the presence of glitching and correlation.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
60	Chad Spensky, Aravind Machiry, Nathan Burow, Hamed Okhravi, Rick Housley, Zhongshu Gu, Hani Jamjoom, Christopher Kruegel, Giovanni Vigna	Glitching Demystified: Analyzing Control-flow-based Glitching Attacks and Defenses.	DSN	2021	DBLP DOI BibTeX RDF
54	Anand Raghunathan, Sujit Dey, Niraj K. Jha	Register transfer level power optimization with emphasis on glitch analysis and reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
51	Anantha P. Chandrakasan	Ultra low power digital signal processing.	VLSI Design	1996	DBLP DOI BibTeX RDF	ultra low power digital signal processing, portable wireless device, capacitance minimization, spatial signal correlations, temporal signal correlations, re-synchronization, operation reduction, 1 V, logic design, DSP, power consumption, switching, integrated circuit design, voltage scaling, digital signal processing chips, circuit optimisation, circuit design, data representation, circuit optimization, glitching, architecture optimization
48	Janardhan H. Satyanarayana, Keshab K. Parhi	Theoretical Analysis of Word-Level Switching Activity in the Presence of Glitching and Correlation.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
36	Ruzica Jevtic, Carlos Carreras	Analytical High-Level Power Model for LUT-Based Components.	PATMOS	2008	DBLP DOI BibTeX RDF
36	Ruzica Jevtic, Carlos Carreras, Gabriel Caffarena	Switching Activity Models for Power Estimation in FPGA Multipliers.	ARC	2007	DBLP DOI BibTeX RDF
36	Ahmed Sayed, Hussain Al-Asaad	A New Statistical Approach for Glitch Estimation in Combinational Circuits.	ISCAS	2007	DBLP DOI BibTeX RDF
36	Brock J. LaMeres, Kanupriya Gulati, Sunil P. Khatri	Controlling inductive cross-talk and power in off-chip buses using CODECs.	ASP-DAC	2006	DBLP DOI BibTeX RDF
36	Xun Liu, Marios C. Papaefthymiou	Incorporation of input glitches into power macromodeling.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
30	Hao Lin 0005, Cai Liu, Zhenhua Li 0001, Feng Qian 0001, Mingliang Li, Ping Xiong, Yunhao Liu 0001	Aging or Glitching? What Leads to Poor Android Responsiveness and What Can We Do About It?	IEEE Trans. Mob. Comput.	2024	DBLP DOI BibTeX RDF
30	Xhani Marvin Saß, Richard Mitev, Ahmad-Reza Sadeghi	Oops..! I Glitched It Again! How to Multi-Glitch the Glitching-Protections on ARM TrustZone-M.	CoRR	2023	DBLP DOI BibTeX RDF
30	Xhani Marvin Saß, Richard Mitev, Ahmad-Reza Sadeghi	Oops..! I Glitched It Again! How to Multi-Glitch the Glitching-Protections on ARM TrustZone-M.	USENIX Security Symposium	2023	DBLP BibTeX RDF
30	Jonas Ruchti, Michael Gruber, Michael Pehl	When the Decoder Has to Look Twice: Glitching a PUF Error Correction.	IACR Trans. Cryptogr. Hardw. Embed. Syst.	2022	DBLP DOI BibTeX RDF
30	Otto Bittner, Thilo Krachenfels, Andreas Galauner, Jean-Pierre Seifert	The Forgotten Threat of Voltage Glitching: A Case Study on Nvidia Tegra X2 SoCs.	CoRR	2021	DBLP BibTeX RDF
30	Jonas Ruchti, Michael Gruber, Michael Pehl	When the Decoder Has to Look Twice: Glitching a PUF Error Correction.	IACR Cryptol. ePrint Arch.	2021	DBLP BibTeX RDF
30	Jonathon Durand, Anisul Abedin, Jakub Szefer	Ultra Freezing Attacks and Clock Glitching of Clock Oscillator Circuits.	AsianHOST	2021	DBLP DOI BibTeX RDF
30	Otto Bittner, Thilo Krachenfels, Andreas Galauner, Jean-Pierre Seifert	The Forgotten Threat of Voltage Glitching: A Case Study on Nvidia Tegra X2 SoCs.	FDTC	2021	DBLP DOI BibTeX RDF
30	Mingliang Li, Hao Lin 0005, Cai Liu, Zhenhua Li 0001, Feng Qian 0001, Yunhao Liu 0001, Nian Xiang Sun, Tianyin Xu	Experience: aging or glitching? why does android stop responding and what can we do about it?	MobiCom	2020	DBLP DOI BibTeX RDF
30	G. Surya, Paolo Maistri, Sriram Sankaran	Local Clock Glitching Fault Injection with Application to the ASCON Cipher.	iSES	2020	DBLP DOI BibTeX RDF
30	Thomas Polzer, Florian Huemer, Andreas Steininger	An Experimental Study of Metastability-Induced Glitching Behavior.	J. Circuits Syst. Comput.	2019	DBLP DOI BibTeX RDF
30	Yifan Lu	Injecting Software Vulnerabilities with Voltage Glitching.	CoRR	2019	DBLP BibTeX RDF
30	Raúl Jiménez-Naharro, Fernando Gómez-Bravo, Jonathan Medina García, Manuel Sanchez-Raya, Juan Antonio Gómez Galán	A Smart Sensor for Defending against Clock Glitching Attacks on the I2C Protocol in Robotic Applications.	Sensors	2017	DBLP DOI BibTeX RDF
30	Beverley Hood	Glitching.	Creativity & Cognition	2015	DBLP DOI BibTeX RDF
30	Michael Meixner, Tobias G. Noll	Statistical Modeling of Glitching Effects in Estimation of Dynamic Power Consumption.	VLSID	2014	DBLP DOI BibTeX RDF
30	Jakub Korczyc, Andrzej Krasniewski	Evaluation of susceptibility of FPGA-based circuits to fault injection attacks based on clock glitching.	DDECS	2012	DBLP DOI BibTeX RDF
30	Tomasz S. Czajkowski, Stephen Dean Brown	Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits.	DAC	2007	DBLP DOI BibTeX RDF
30	Sangjin Hong, Shu-Shin Chin, Magesh Sadasivam	Glitching power reduction through supply voltage adaptation mechanism for low power array structure design.	ISCAS (2)	2004	DBLP BibTeX RDF
30	Ioannis Karafyllidis, Stelios Mavridis, Dimitrios Soudris, Adonios Thanailakis	Estimation of power dissipation in glitching using complex-time cellular automata.	ICECS	1999	DBLP DOI BibTeX RDF
18	Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton	GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
18	Fuding Ge, Malay Trivedi, Brent Thomas, William Jiang, Hongjiang Song	1.5V 0.5mW 2MSPS 10B DAC with rail-to-rail output in 0.13mum CMOS technology.	SoCC	2008	DBLP DOI BibTeX RDF
18	Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton	GlitchLess: an active glitch minimization technique for FPGAs.	FPGA	2007	DBLP DOI BibTeX RDF	field-programmable gate arrays, power minimization
18	V. R. Devanathan, C. P. Ravikumar, V. Kamakoti 0001	Interactive presentation: On power-profiling and pattern generation for power-safe scan tests.	DATE	2007	DBLP DOI BibTeX RDF
18	V. R. Devanathan, C. P. Ravikumar, V. Kamakoti 0001	Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test.	VTS	2007	DBLP DOI BibTeX RDF	Low Power ATPG, Glitch Power, IR Drop, Peak Power, Power-profiling
18	Dhananjai Madhava Rao, Philip A. Wilsey	Applying parallel, dynamic-resolution simulations to accelerate VLSI power estimation.	WSC	2006	DBLP DOI BibTeX RDF
18	Olli Vertanen	Java Type Confusion and Fault Attacks.	FDTC	2006	DBLP DOI BibTeX RDF	type confusion, Java, embedded systems, fault attacks, Java Card
18	Wieland Fischer, Berndt M. Gammel	Masking at Gate Level in the Presence of Glitches.	CHES	2005	DBLP DOI BibTeX RDF	random masking, masked logic circuits, Cryptanalysis, side-channel attacks, DPA, power analysis, logic circuits, digital circuits, masking, glitches
18	Sangjin Hong, Shu-Shin Chin	Incorporating Power Reduction Mechanism in Arithmetic Core Design.	ISVLSI	2004	DBLP DOI BibTeX RDF
18	Victor V. Zyuban	Optimization of scannable latches for low energy.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
18	Horng-Bin Wang, Shi-Yu Huang, Jing-Reng Huang	Gate-Delay Fault Diagnosis Using the Inject-and-Evaluate Paradigm.	DFT	2002	DBLP DOI BibTeX RDF
18	Sergei P. Skorobogatov, Ross J. Anderson	Optical Fault Induction Attacks.	CHES	2002	DBLP DOI BibTeX RDF
18	K'Andrea C. Bickerstaff, Earl E. Swartzlander Jr., Michael J. Schulte	Analysis of Column Compression Multipliers.	IEEE Symposium on Computer Arithmetic	2001	DBLP DOI BibTeX RDF
18	Artur Wróblewski, Otto Schumacher, Christian V. Schimpfle, Josef A. Nossek	Minimizing gate capacitances with transistor sizing.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
18	Antonio G. M. Strollo, Ettore Napoli, Carlo Cimino	Analysis of power dissipation in double edge-triggered flip-flops.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
18	Subodh Gupta, Farid N. Najm	Power modeling for high-level power estimation.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
18	Henrik Eriksson, Per Larsson-Edefors	Impact of Voltage Scaling on Glitch Power Consumption.	PATMOS	2000	DBLP DOI BibTeX RDF
18	Sujit Dey, Anand Raghunathan, Niraj K. Jha, Kazutoshi Wakabayashi	Controller-based power management for control-flow intensive designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
18	Christian V. Schimpfle, Sven Simon 0001, Josef A. Nossek	Device level based cell modeling for fast power estimation.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
18	Anand Raghunathan, Sujit Dey, Niraj K. Jha, Kazutoshi Wakabayashi	Power Management Techniques for Control-Flow Intensive Designs.	DAC	1997	DBLP DOI BibTeX RDF
18	Chin-Chi Teng, Anthony M. Hill, Sung-Mo Kang	Estimation of maximum transition counts at internal nodes in CMOS VLSI circuits.	ICCAD	1995	DBLP DOI BibTeX RDF	maximum switching activity, uncertainty waveforms, circuit reliability
18	Srinivas Devadas, Kurt Keutzer, Jacob K. White 0001	Estimation of power dissipation in CMOS combinational circuits using Boolean function manipulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF