Search results for "iDCT"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
144	Mihai Sima, Sorin Cotofana, Jos T. J. van Eijndhoven, Stamatis Vassiliadis, Kees A. Vissers	IEEE-Compliant IDCT on FPGA-Augmented TriMedia.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	inverse discrete cosine transform, field-programmable gate array, configurable computing, VLIW processor
136	Hui-Cheng Hsu, Kun-Bin Lee, Nelson Yen-Chung Chang, Tian-Sheuan Chang	Architecture Design of Shape-Adaptive Discrete Cosine Transform and Its Inverse for MPEG-4 Video Coding.	IEEE Trans. Circuits Syst. Video Technol.	2008	DBLP DOI BibTeX RDF
117	Lijie Liu, Trac D. Tran	Rate-Distortion Analysis of Multiplierless Lifting-based IDCT Approximations.	CISS	2007	DBLP DOI BibTeX RDF
117	Jiun-In Guo, Rei-Chin Ju, Jia-Wei Chen	An efficient 2-D DCT/IDCT core design using cyclic convolution and adder-based realization.	IEEE Trans. Circuits Syst. Video Technol.	2004	DBLP DOI BibTeX RDF
113	Jiun-In Guo, Jui-Cheng Yen	An Efficient IDCT Processor Design for HDTV Applications.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	inverse discrete cosine transform (IDCT), adder-based implementation, common sub-expression sharing, HDTV, cyclic convolution
99	Tze-Yun Sung, Yaw-Shih Shieh, Chun-Wang Yu, Hsi-Chin Hsin	High-Efficiency and Low-Power Architectures for 2-D DCT and IDCT Based on CORDIC Rotation.	PDCAT	2006	DBLP DOI BibTeX RDF	low-power, DCT, CORDIC, IDCT
95	Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers	A Reconfigurable Functional Unit for TriMedia/CPU64. A Case Study.	Embedded Processor Design Challenges	2002	DBLP DOI BibTeX RDF
91	Tze-Yun Sung, Mao-Jen Sun, Yaw-Shih Shieh, Hsi-Chin Hsin	Memory-Efficiency and High-Speed Architectures for Forward and Inverse DCT with Multiplierless Operation.	PSIVT	2006	DBLP DOI BibTeX RDF	parallel-pipelined architecture, memory-efficiency, DCT, high-performances, IDCT
90	Dae Won Kim, Taek Won Kwon, Jung Min Seo, Jae Kun Yu, Kyu Lee, Jung Hee Suk, Jun Rim Choi	A compatible DCT/IDCT architecture using hardwired distributed arithmetic.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
82	Jooheung Lee, Narayanan Vijaykrishnan, Mary Jane Irwin	Inverse discrete cosine transform architecture exploiting sparseness and symmetry properties.	IEEE Trans. Circuits Syst. Video Technol.	2006	DBLP DOI BibTeX RDF
82	Mihai Sima, Sorin Dan Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers	Pel reconstruction on FPGA-augmented TriMedia.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
82	Kibum Suh, Seongmo Park, Seongmin Kim, Bontae Koo, Igkyun Kim, Kyungsoo Kim, Hanjin Cho	An efficient architecture of DCTQ module in MPEG-4 video codec.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
82	Kibum Suh, Kyung Yuk Min, Kyeounsoo Kim, Jong-Seog Koh, Jong-Wha Chong	A design of DPCM hybrid coding loop using single 1-D DCT in MPEG-2 video encoder.	ISCAS (4)	1999	DBLP DOI BibTeX RDF
76	Yuriy A. Reznik, De Hsu, Prasanjit Panda, Brijesh Pillai	Low-Drift Fixed-Point 8X8 IDCT Approximationwith 8-Bit Transform Factors.	ICIP (6)	2007	DBLP DOI BibTeX RDF
72	Gustavo A. Ruiz, Juan A. Michell, Angel M. Burón	High Throughput Parallel-Pipeline 2-D DCT/IDCT Processor Chip.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	inverse discrete cosine transform (IDCT), row column decomposition, parallel pipelined architectures, very large scale integration (VLSI), image compression, discrete cosine transform (DCT)
68	Honggang Qi, Wen Gao 0001	High-Accuracy and Low-Complexity Fixed-Point Inverse Discrete Cosine Transform Based on AAN's Fast Algortihm.	ISCAS	2007	DBLP DOI BibTeX RDF
64	Bret Stott, Dave Johnson 0003, Venkatesh Akella	Asynchronous 2-D discrete cosine transform core processor.	ICCD	1995	DBLP DOI BibTeX RDF	asynchronous 2-D discrete cosine transform core processor, self-timed design, CCITT compatible asynchronous DCT/IDCT processor, two-phase transition signaling, bounded delay approach, Sutherland's micropipeline, custom techniques, 2 /spl mu/ SCMOS technology, delays, discrete cosine transforms, digital signal processing chips, CMOS digital integrated circuits, standard cell, 2 micron
62	Lodewijk T. Smit, Gerard K. Rauwerda, Albert Molderink, Pascal T. Wolkotte, Gerard J. M. Smit	Implementation of a 2-D 8x8 IDCT on the Reconfigurable Montium Core.	FPL	2007	DBLP DOI BibTeX RDF
62	João Manuel R. S. Tavares, António Silva, Antonio Navarro 0002	H.263 Video Codec Performance with a Fast 8×8 Integer IDCT.	ICME	2006	DBLP DOI BibTeX RDF
62	Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh, Jia-Wei Chen	An Energy-Aware IP Core Design for the Variable-Length DCT/IDCT Targeting at MPEG4 Shape-Adaptive Transforms.	IEEE Trans. Circuits Syst. Video Technol.	2005	DBLP DOI BibTeX RDF
62	Bo Fang, Guobin Shen, Shipeng Li 0001, Huifang Chen	Techniques for efficient DCT/IDCT implementation on generic GPU.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
62	Nathaniel J. August, Dong Sam Ha	Low power design of DCT and IDCT for low bit rate video codecs.	IEEE Trans. Multim.	2004	DBLP DOI BibTeX RDF
62	Rohini Krishnan, Om Prakash Gangwal, Jos T. J. van Eijndhoven, Anshul Kumar	Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks.	VLSI Design	2003	DBLP DOI BibTeX RDF
62	Hyesook Lim, Changhoon Yim, Earl E. Swartzlander Jr.	Finite Word-Length Effects Of An Unified Systolic Array For 2-D DCT/IDCT.	ASAP	1996	DBLP DOI BibTeX RDF	finite word-length effects, unified systolic array, fixed-point error analysis, inverse discrete cosine transform, fixed-point rounding-errors, minimum word-length, fixed-point error, discrete cosine transforms, discrete cosine transform, systolic arrays, digital simulation, error analysis, simulation results, roundoff errors, closed form expressions, truncation-errors
62	Feng Zhou, Peter Kornerup	High Speed DCT/IDCT Using a Pipelined CORDIC Algorithm.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF
54	Woong Hwangbo, Jaemoon Kim, Chong-Min Kyung	A High-Performance 2-D Inverse Transform Architecture for the H.264/AVC Decoder.	ISCAS	2007	DBLP DOI BibTeX RDF
54	Qionghai Dai, Xinjian Chen 0002, Chuang Lin 0002	Fast algorithms for multidimensional DCT-to-DCT computation between a block and its associated subblocks.	IEEE Trans. Signal Process.	2005	DBLP DOI BibTeX RDF
49	M. F. Mansour	On the odd-DFT and its applications to DCT/IDCT computation.	IEEE Trans. Signal Process.	2006	DBLP DOI BibTeX RDF
49	Shyue-Kung Lu, Ting-Yu Chen, Wei-Yuan Liu	Efficient Built-In Self-Test Schemes for Video Coding Cores: a Case Study on DCT/IDCT Circuits.	PRDC	2006	DBLP DOI BibTeX RDF
49	Gustavo A. Ruiz, Juan A. Michell, Angel M. Burón	High throughput 2D DCT/IDCT processor for video coding.	ICIP (3)	2005	DBLP DOI BibTeX RDF
49	Yi Yang, Chunyan Wang 0004, M. Omair Ahmad, M. N. S. Swamy	An FPGA implementation of an on-line radix-4 CORDIC 2-D IDCT core.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
49	Minyi Fu, Vassil S. Dimitrov, Graham A. Jullien	An efficient technique for error-free algebraic-integer encoding for high performance implementation of the DCT and IDCT.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
49	Dave Johnson 0003, Venkatesh Akella, Bret Stott	Micropipelined asynchronous discrete cosine transform (DCT/IDCT) processor.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
49	Claus Schneider, Martin Kayss, Thomas Hollstein, Jürgen Deicke	From Algorithms to Hardware Architectures: A Comparison of Regular and Irregular Structured IDCT Algorithms.	DATE	1998	DBLP DOI BibTeX RDF
45	Thomas Tziortzios, Stavros Dokouzyannis	A Fast 8*8 2D IDCT Architecture, Avoiding Zero Transformed Coefficients.	IIH-MSP	2010	DBLP DOI BibTeX RDF	2D IDCT, forward mapping, image processing
43	Chaouki Diab, Mohamad Oueidat, Rémy Prost	A new IDCT-DFT relationship reducing the IDCT computational cost.	IEEE Trans. Signal Process.	2002	DBLP DOI BibTeX RDF
41	Yanmei Qu, Shunliang Mei, Yun He	A Cost-effective VLD Architecture for MPEG-2 and AVS.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	CA-2D-VLC, VLD, inverse quantisation, MPEG-2, AVS, VLC
41	Jiun-In Guo, Jia-Wei Chen, Han-Chen Chen	A new 2-D 8×8 DCT/IDT core design using group distributed arithmetic.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
41	Jiun-In Guo	A low cost 2-D inverse discrete cosine transform design for image compression.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
41	Yoichi Katayama, Toshiaki Kitsuki, Yasushi Ooi	A Block Processing Unit in a Single-Chip MPEG-2 Video Encoder LSI.	J. VLSI Signal Process.	1999	DBLP DOI BibTeX RDF
37	Andrew Kinane, Noel E. O'Connor	Energy-efficient Hardware Accelerators for the SA-DCT and Its Inverse.	J. VLSI Signal Process.	2007	DBLP DOI BibTeX RDF	shape adaptive DCT/IDCT, low power, MPEG-4, hardware acceleration, video objects
37	Armando Sánchez-Peña, Pedro P. Carballo, Luz García 0001, Antonio Núñez	VIPACES, Verification Interface Primitives for the Development of AXI Compliant Elements and Systems.	DSD	2006	DBLP DOI BibTeX RDF	AMBA 3 AXI, VIPACES, Virtual Components, Verification, Test, System-on-Chip (SoC), IP, DCT, Emulation, SystemC, Environment, TLM, IDCT, VIP
37	Marco Antonio Dal Poz, Jose Edinson Aedo Cobo, Wilhelmus A. M. Van Noije, Marcelo Knörich Zuffo	A Simple RISC Microprocessor Core Designed for Digital Set-Top-Box Applications.	ASAP	2000	DBLP DOI BibTeX RDF	FPGA, VHDL, Reconfigurable Computing, Microprocessor, MPEG, RISC, Co-Design, Instruction Set, HDTV, Set-Top-Box, iDCT, cable TV
37	Yi-Shin Tung, Chia-Chiang Ho, Ja-Ling Wu	MMX-Based DCT and MC Algorithms for Real-Time Pure Software MPEG Decoding.	ICMCS, Vol. 1	1999	DBLP DOI BibTeX RDF	Pattern-Based IDCT, MPEG, Video Compression, MMX
35	Khan Wahid, Vassil S. Dimitrov, Graham A. Jullien	Error-Free Computation of 8x8 2-D DCT and IDCT Using Two-Dimensional Algebraic Integer Quantization.	IEEE Symposium on Computer Arithmetic	2005	DBLP DOI BibTeX RDF
35	Peter Lee 0001	An evaluation of a hybrid-logarithmic number system DCT/IDCT algorithm [image compression applications].	ISCAS (5)	2005	DBLP DOI BibTeX RDF
35	Takashi Miyazaki, Takao Nishitani, Masato Edahiro, Ikuko Ono, Kaoru Mitsuhashi	DCT/IDCT processor for HDTV developed with dsp silicon compiler.	J. VLSI Signal Process.	1993	DBLP DOI BibTeX RDF
27	Veera Papirla, Aarul Jain, Chaitali Chakrabarti	Low power robust signal processing.	ISLPED	2009	DBLP DOI BibTeX RDF	algorithmic noise tolerance, redundant binary arithmetic, soft DSP
27	Zhu Chen, Moon Ho Lee, Chang-Joo Kim	Fast Hybrid DFT/DCT Architecture for OFDM in Cognitive Radio System.	FGCN (1)	2007	DBLP DOI BibTeX RDF
27	Javier D. Bruguera, Roberto R. Osorio	A Unified Architecture for H.264 Multiple Block-Size DCT with Fast and Low Cost Quantization.	DSD	2006	DBLP DOI BibTeX RDF
27	Hanli Wang, Sam Kwong, Chi-Wah Kok	Fast video coding based on Gaussian model of DCT coefficients.	ISCAS	2006	DBLP DOI BibTeX RDF
27	Alex Ginzburg, Evgeny Kaminsky, Yuri Abramov, Ofer Hadar	DCT-Domain Coder for Digital Video Applications.	ITRE	2006	DBLP DOI BibTeX RDF
27	Jooheung Lee, Narayanan Vijaykrishnan, Mary Jane Irwin	High Performance Array Processor for Video Decoding.	ISVLSI	2005	DBLP DOI BibTeX RDF
27	Stephan Gatzka, Christian Hochberger	On the Scope of Hardware Acceleration of Reconfigurable Processors in Mobile Devices.	HICSS	2005	DBLP DOI BibTeX RDF
27	Jianmin Jiang, Ying Weng	Video extraction for fast content access to MPEG compressed videos.	IEEE Trans. Circuits Syst. Video Technol.	2004	DBLP DOI BibTeX RDF
27	Danian Gong, Yun He, Zhigang Cao	New cost-effective VLSI implementation of a 2-D discrete cosine transform and its inverse.	IEEE Trans. Circuits Syst. Video Technol.	2004	DBLP DOI BibTeX RDF
27	Matjaz Verderber, Andrej Zemva, Damjan Lampret	HW/SW Partitioned Optimization and VLSI-FPGA Implementation of the MPEG-2 Video Decoder.	DATE	2003	DBLP DOI BibTeX RDF
27	Matjaz Verderber, Andrej Zemva, Andrej Trost	HW/SW Codesign of the MPEG-2 Video Decoder.	IPDPS	2003	DBLP DOI BibTeX RDF
27	Kunihiro Yamada, Yukihisa Naoe, Masanori Kojima, Tadanori Mizuno	A New MPEG-2 Solution Using a 2nd ALU in the RISC.	KES	2003	DBLP DOI BibTeX RDF
27	Huesung Kim, Arun K. Somani, Akhilesh Tyagi	A reconfigurable multi-function computing cache architecture.	FPGA	2000	DBLP DOI BibTeX RDF
27	Kyeounsoo Kim, Peter A. Beerel, Youpyo Hong	An asynchronous matrix-vector multiplier for discrete cosine transform.	ISLPED	2000	DBLP DOI BibTeX RDF	asynchronous matrix-vector multiplier, discrete cosine transform
27	Jarno K. Tanskanen, Jarkko Niittylahti	Parallel Memories in Video Encoding.	Data Compression Conference	1999	DBLP DOI BibTeX RDF
23	Yifeng Qiu, Wael M. Badawy, Robert D. Turney	An Architecture for Programmable Multi-core IP Accelerated Platform with an Advanced Application of H.264 Codec Implementation.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Virtual socket, DCT/Q, IDCT/Q-1, Deblocking, Architecture, Motion estimation, Multi-core, H.264/AVC, Accelerator, Video codec, CAVLC
23	Chao-Jang Hwang, Chih-Tung Lin, Shi-Jinn Horng	Implementation of Different Function Units Using Flexible and Reconfigurable Architecture.	ITNG	2009	DBLP DOI BibTeX RDF	Image Processing, DCT, IDCT
23	Zhenyu Wu, Hongyang Yu, Bin Tang, Hong Hu	Performance Evaluation of Transcoding Algorithms for MPEG-2 to AVS-P2.	IIH-MSP	2006	DBLP DOI BibTeX RDF	AVS-P2(Audio Video Standard Part2: video), re-quantization, IT(integer transform), IIT(inverse integer transform), IDCT(inverse DCT), transcoding, MPEG-2
23	Osvaldo Colavin, Davide Rizzo	A scalable wide-issue clustered VLIW with a reconfigurable interconnect.	CASES	2003	DBLP DOI BibTeX RDF	clustered VLIW, reconfigurable co-processor (RCP), modulo scheduling, IDCT
23	Carla L. Pagliari, Tim J. Dennis	Stereo disparity computation in the DCT domain using genetic algorithms.	ICIP (3)	1997	DBLP DOI BibTeX RDF	stereo disparity computation, image block, estimated disparity map, AC coefficients, DC component, intensity similarity measure, biologically inspired optimisation, genetic algorithms, discrete cosine transform, camera, stereo image processing, stereo matching, correspondence problem, DCT coefficients, statistical properties, inverse transform, IDCT, DCT domain, image domain
23	Marco Mattavelli, Sylvain Brunetton, Daniel Mlynek	Computational Graceful Degradation for Video Sequence Decoding.	ICIP (1)	1997	DBLP DOI BibTeX RDF	computational graceful degradation, video sequence decoding, software based video decoders, dedicated hardware real time systems, video/audio decoders, video compression standards, video/audio bitstreams processing, multimedia processors, compressed video sequences, H.263 video compression standard, video processor platform, interfaces, video coding, simulation results, real-time performance, main memory, IDCT, hardware platform
22	Mojtaba Mahdavi 0001	Towards Low-Complexity, Fully Parallel and Flexible Hardware Realization of DCT/IDCT.	ICSPCS	2023	DBLP DOI BibTeX RDF
22	Zhiwei Zhou, Zhongliang Pan	Effective Hardware Accelerator for 2D DCT/IDCT Using Improved Loeffler Architecture.	IEEE Access	2022	DBLP DOI BibTeX RDF
22	Yadwinder Singh, Lakhwinder Kaur, Nirvair Neeru	A New Improved Obstacle Detection Framework Using IDCT and CNN to Assist Visually Impaired Persons in an Outdoor Environment.	Wirel. Pers. Commun.	2022	DBLP DOI BibTeX RDF
22	Arunachalam Venkatesan, Alex Noel Joseph Raj, Deepika Selvaraj	Performance Improvement of Vector-Radix Decimation-in-Frequency 3D-DCT/IDCT Using Variable Word Length.	Circuits Syst. Signal Process.	2021	DBLP DOI BibTeX RDF
22	Yifan Wang, Zhanxuan Mei, Chia-Yang Tsai, Ioannis Katsavounidis, C.-C. Jay Kuo	A Machine Learning Approach to Optimal Inverse Discrete Cosine Transform (IDCT) Design.	CoRR	2021	DBLP BibTeX RDF
22	Shensheng Tang, Monali Sinare, Yi Zheng	Design, optimisation and implementation of a DCT/IDCT-based image processing system on FPGA.	Int. J. Comput. Appl. Technol.	2021	DBLP DOI BibTeX RDF
22	Barmak Honarvar Shakibaei Asli, Jan Flusser, Yifan Zhao 0001, John Ahmet Erkoyuncu, Kajoli Banerjee Krishnan, Yasin Farrokhi, Rajkumar Roy	Ultrasound Image Filtering and Reconstruction Using DCT/IDCT Filter Structure.	IEEE Access	2020	DBLP DOI BibTeX RDF
22	Dezhi An, Shengcai Zhang, Jun Lu, Yan Li	Efficient and Privacy-Preserving Outsourcing of 2D-DCT and 2D-IDCT.	Wirel. Commun. Mob. Comput.	2020	DBLP DOI BibTeX RDF
22	Debasish Mukherjee, Susanta Mukhopadhyay	Hardware Efficient Architecture for 2D DCT and IDCT Using Taylor-Series Expansion of Trigonometric Functions.	IEEE Trans. Circuits Syst. Video Technol.	2020	DBLP DOI BibTeX RDF
22	Ahmed Ben Atitallah, Manel Kammoun, Karim M. A. Ali, Rabie Ben Atitallah	An FPGA comparative study of high-level and low-level combined designs for HEVC intra, inverse quantization, and IDCT/IDST 2D modules.	Int. J. Circuit Theory Appl.	2020	DBLP DOI BibTeX RDF
22	Ashish Singhadia, Meghan Mamillapalli, Indrajit Chakrabarti	Hardware-Efficient 2D-DCT/IDCT Architecture for Portable HEVC-Compliant Devices.	IEEE Trans. Consumer Electron.	2020	DBLP DOI BibTeX RDF
22	Barmak Honarvar Shakibaei Asli, Jan Flusser, Yifan Zhao 0001, John Ahmet Erkoyuncu, Rajkumar Roy	DCT/IDCT Filter Design for Ultrasound Image Filtering.	ICPR	2020	DBLP DOI BibTeX RDF
22	Martin Johnson, Daniel P. Playne	A Fast and Concise Parallel Implementation of the 8x8 2D IDCT using Halide.	SBAC-PAD	2020	DBLP DOI BibTeX RDF
22	En-Pei Wu, Trong-An Bui, Kermit Chen, Pei-Jun Lee	Hardware Implementation of DCT/IDCT sharing for HEVC/MPEG Video Coding.	ICCE	2020	DBLP DOI BibTeX RDF
22	Jianfeng Zhang, Wei Shi, Li Zhou, Rui Gong, Lei Wang 0011, Hongwei Zhou	A Low-Power and High-PSNR Unified DCT/IDCT Architecture Based on EARC and Enhanced Scale Factor Approximation.	IEEE Access	2019	DBLP DOI BibTeX RDF
22	Subiman Chatterjee, Kishor Sarawadekar	WHT and Matrix Decomposition-Based Approximated IDCT Architecture for HEVC.	IEEE Trans. Circuits Syst. II Express Briefs	2019	DBLP DOI BibTeX RDF
22	He Ma, Yi Zuo, Tieshan Li, C. L. Philip Chen, Junxia Liu	A Euclidean metric based voice feature extraction method using IDCT cepstrum coefficient.	SMC	2019	DBLP DOI BibTeX RDF
22	Genwei Tang, Ming-e Jing, Xiaoyang Zeng, Yibo Fan	A 32-Pixel IDCT-Adapted HEVC Intra Prediction VLSI Architecture.	ISCAS	2019	DBLP DOI BibTeX RDF
22	Mohammad Ali Pourabed, Sajjad Nouri, Jari Nurmi	Design and Implementation of 2D IDCT/IDST-Specific Accelerator on Heterogeneous Multicore Architecture.	NORCAS	2018	DBLP DOI BibTeX RDF
22	Luciano A. Braatz, Daniel Palomino 0001, Luciano Volcan Agostini, Bruno Zatt, Marcelo Schiavon Porto	Low-Power HEVC 1-D IDCT Hardware Architecture.	SBCCI	2018	DBLP DOI BibTeX RDF
22	Doru-Florin Chiper, Laura-Teodora Cotorobai	A Unified VLSI architecture for 1D IDCT and IDST based on pseudo-band correlations.	ECAI	2018	DBLP DOI BibTeX RDF
22	Yuan-Ho Chen, Yi-Fan Ko	High-throughput IDCT architecture for high-efficiency video coding (HEVC).	Int. J. Circuit Theory Appl.	2017	DBLP DOI BibTeX RDF
22	Vili Viitamäki, Panu Sjovall, Jarno Vanne, Timo D. Hämäläinen	High-level synthesized 2-D IDCT/IDST implementation for HEVC codecs on FPGA.	ISCAS	2017	DBLP DOI BibTeX RDF
22	Mingyu Wang, Fang Wang, Shaojun Wei, Zhaolin Li	A pipelined area-efficient and high-speed reconfigurable processor for floating-point FFT/IFFT and DCT/IDCT computations.	Microelectron. J.	2016	DBLP DOI BibTeX RDF
22	Liang Hong, Wei-Feng He, Guanghui He, Zhigang Mao	Area-efficient HEVC IDCT/IDST architecture for 8K × 4K video decoding.	IEICE Electron. Express	2016	DBLP DOI BibTeX RDF
22	Kaili Yao, Ronggang Wang, Zhenyu Wang 0002, Wenmin Wang, Wen Gao 0001	A Fast and Lossless IDCT Design for AVS2 Codec.	BigMM	2016	DBLP DOI BibTeX RDF
22	Yiliu Feng, Jianfeng Zhang, Hengzhu Liu	A Novel Low-Power and High-PSNR Architecture Based on ARC for DCT/IDCT.	NCCET	2016	DBLP DOI BibTeX RDF
22	Yibo Fan, Leilei Huang, Yufeng Bai, Xiaoyang Zeng	A Parallel-Access Mapping Method for the Data Exchange Buffers Around DCT/IDCT in HEVC Encoders Based on Single-Port SRAMs.	IEEE Trans. Circuits Syst. II Express Briefs	2015	DBLP DOI BibTeX RDF
22	Ahmed Kilany, Maher Abdelrasoul, Ahmed Shalaby 0001, Mohammed Sharaf Sayed	A reconfigurable 2-D IDCT architecture for HEVC encoder/decoder.	ICM	2015	DBLP DOI BibTeX RDF
22	Ruhan A. Conceição, Andrio Araujo, Marcelo Schiavon Porto, Bruno Zatt, Luciano Volcan Agostini	Hardware design of fast HEVC 2-D IDCT targeting real-time UHD 4K applications.	LASCAS	2015	DBLP DOI BibTeX RDF
22	Jianfeng Zhang, Paul Chow, Hengzhu Liu	FPGA implementation of low-power and high-PSNR DCT/IDCT architecture based on adaptive recoding CORDIC.	FPT	2015	DBLP DOI BibTeX RDF
22	Qing Shang, Yibo Fan, Weiwei Shen, Sha Shen, Xiaoyang Zeng	Single-Port SRAM-Based Transpose Memory With Diagonal Data Mapping for Large Size 2-D DCT/IDCT.	IEEE Trans. Very Large Scale Integr. Syst.	2014	DBLP DOI BibTeX RDF