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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 11 occurrences of 11 keywords
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Results
Found 7 publication records. Showing 7 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
54 | Fei Wu 0005, Liang Wang, Jiguang Wan |
A Low Cost and Inner-round Pipelined Design of ECB-AES-256 Crypto Engine for Solid State Disk. |
NAS |
2010 |
DBLP DOI BibTeX RDF |
inner-round, ECB-AES-256 crypto engine, SSD |
28 | Afshin Shiravi, Yoon G. Kim, Paul S. Min |
Proportional Nested Deficit Round Robin: Improving the Latency of Packet Scheduler with an O(1) Complexity. |
AAA-IDEA |
2005 |
DBLP DOI BibTeX RDF |
Nested- DRR, Quantum Size, Complexity, Packet switch, Fair queueing, Deficit Round Robin |
22 | Sanjay Deshpande, Kris Gaj |
Analysis and Inner-Round Pipelined Implementation of Selected Parallelizable CAESAR Competition Candidates. |
DSD |
2017 |
DBLP DOI BibTeX RDF |
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17 | Alireza Hodjat, Ingrid Verbauwhede |
Area-Throughput Trade-Offs for Fully Pipelined 30 to 70 Gbits/s AES Processors. |
IEEE Trans. Computers |
2006 |
DBLP DOI BibTeX RDF |
crypto-processor, security, VLSI, cryptography, Advanced Encryption Standard (AES), ASIC, hardware architectures |
17 | Alireza Hodjat, Ingrid Verbauwhede |
Minimum Area Cost for a 30 to 70 Gbits/s AES Processor. |
ISVLSI |
2004 |
DBLP DOI BibTeX RDF |
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17 | Alireza Hodjat, Ingrid Verbauwhede |
A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA. |
FCCM |
2004 |
DBLP DOI BibTeX RDF |
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12 | Sébastien Kunz-Jacques, Frédéric Muller, Frédéric Valette |
The Davies-Murphy Power Attack. |
ASIACRYPT |
2004 |
DBLP DOI BibTeX RDF |
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Displaying result #1 - #7 of 7 (100 per page; Change: )
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