Search results for "inter-processor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
64	Sekhar R. Sarukkai, Jerry C. Yan, Melisa Schmidt	Automated instrumentation and monitoring of data movement in parallel programs.	IPPS	1995	DBLP DOI BibTeX RDF	data-structure alignments, inter-processor data-structure interactions, compiler front end tools, tracking data-structure movements, NAS benchmarks, parallel programming, parallel programs, data structures, message passing, data flow analysis, software performance evaluation, program diagnostics, performance tools, message passing programs, inter-processor communications, data movement
42	Guilin Chen, Mahmut T. Kandemir	Optimizing inter-processor data locality on embedded chip multiprocessors.	EMSOFT	2005	DBLP DOI BibTeX RDF	chip multiprocessors, data locality, stencil computation
39	Hea-Sook Park, Sung-Jin Moon, Man-Sik Park, Boseob Kwon, Kwang-Suk Song	Design of inter processor communication controller using ATM switch and analysis of its optimal message length considering retransmission.	RTCSA	1997	DBLP DOI BibTeX RDF	inter processor communication controller, optimal message length, distributed large-scale multiprocessors, ATM adaptation layer, message error rate, message retransmission rate, asynchronous transfer mode, ATM switch, asynchronous transfer mode switches
39	Eryk Laskowski, Marek Tudruj	Inter-processor Connection Reconfiguration Based on Dynamic Look-Ahead Control of Multiple Crossbar Switches.	FPL	2003	DBLP DOI BibTeX RDF
37	Guilin Chen, Mahmut T. Kandemir	An Approach for Enhancing Inter-processor Data Locality on Chip Multiprocessors.	Trans. High Perform. Embed. Archit. Compil.	2007	DBLP DOI BibTeX RDF
36	Shekhar Srikantaiah, Mahmut T. Kandemir, Mary Jane Irwin	Adaptive set pinning: managing shared caches in chip multiprocessors.	ASPLOS	2008	DBLP DOI BibTeX RDF	inter-processor, intra-processor, set pinning, CMP, shared cache
33	Jack L. Lo, Susan J. Eggers, Henry M. Levy, Sujay S. Parekh, Dean M. Tullsen	Tuning Compiler Optimizations for Simultaneous Multithreading.	MICRO	1997	DBLP DOI BibTeX RDF	cyclic algorithm, fine-grained sharing, inter-thread instruction-level parallelism, loop-iteration scheduling, memory system resources, software speculative execution, performance, parallel programs, parallel architecture, compiler optimizations, shared-memory multiprocessors, processor architecture, instructions, simultaneous multithreading, latency hiding, loop tiling, optimising compilers, inter-processor communication, cache size
32	Marek Tudruj	Embedded Cluster Computing through Dynamic Reconfigurability of Inter-Processor Connections.	IWCC	2001	DBLP DOI BibTeX RDF
30	Ken-ichiro Murakami	A Pseudo Network Approach to Inter-processor Communication on a Shared-memory Multi-processor MacELIS.	Workshop on Parallel Lisp	1989	DBLP DOI BibTeX RDF
30	Ken'ichirou Kimura, Hirofumi Amano, Akifumi Makinouchi	Dynamic Performance Optimization Mechanism for Parallel Object-Oriented Database Programming Languages.	IDEAS	2000	DBLP DOI BibTeX RDF	dynamic performance optimization, parallel object-oriented database programming languages, distributed-memory parallel processor, remote object referencing, biased distribution, object relocation, simulation tests, topology, parallel languages, performance degradation, inter-processor communication, load imbalance, object allocation
29	Eryk Laskowski, Marek Tudruj	Efficient Parallel Embedded Computing through Look-Ahead Configured Dynamic Inter-Processor Connections.	PARELEC	2006	DBLP DOI BibTeX RDF
28	Eryk Laskowski, Marek Tudruj	Inter-processor Communication Optimization in Dynamically Reconfigurable Embedded Parallel Systems.	PPAM	2007	DBLP DOI BibTeX RDF
27	Eunseuk Oh, Hongsik Choi, David Primeaux	An All-Reduce Operation in Star Networks Using All-to-All Broadcast Communication Pattern.	International Conference on Computational Science (1)	2005	DBLP DOI BibTeX RDF	all-reduce, distributed memory parallel computing systems, all-to-all broadcast, star network, inter-processor communication
27	Sangman Moh, Chansu Yu, Dongsoo Han	Design and Experiment of a Communication-Aware Parallel Quicksort with Weighted Partition of Processors.	ICCSA (4)	2004	DBLP DOI BibTeX RDF
27	Mohamed A. Gomaa, Chad Scarbrough, Irith Pomeranz, T. N. Vijaykumar	Transient-Fault Recovery for Chip Multiprocessors.	ISCA	2003	DBLP DOI BibTeX RDF
27	Mahmut T. Kandemir, Yuanrui Zhang, Sai Prashanth Muralidhara, Ozcan Ozturk 0001, Sri Hari Krishna Narayanan	Slicing based code parallelization for minimizing inter-processor communication.	CASES	2009	DBLP DOI BibTeX RDF	automatic code parallelization, code analysis and optimization, iteration space slicing, parallelizing compilers
27	Syed Misbahuddin, Nizar Al-Holou	Improving Inter-processor Data Transfer Rates over Industrial Networks.	AICCSA	2007	DBLP DOI BibTeX RDF
26	Arata Shinozaki, Masatoshi Shima 0002, Minyi Guo, Mitsunori Kubo	A High Performance Simulator System for a Multiprocessor System Based on a Multi-way Cluster.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF
26	Eryk Laskowski, Marek Tudruj	Assessment of Dynamic Look-Ahead Inter-Processor Connection Reconfiguration for Different Control Paradigms.	ISPDC	2006	DBLP DOI BibTeX RDF
26	Yongwha Chung, Jin-Won Park	Solving Irregular Inter-processor Data Dependency in Image Understanding Tasks.	ACPC	1999	DBLP DOI BibTeX RDF
25	Jih-Fu Tu, Chih-Yung Chen	An Effective Bus-Band Arbiter for Processors Communication.	AINA (2)	2004	DBLP DOI BibTeX RDF	Bus-based arbitration circuit, multistage bus network (MBN), M-to-B Arbiter and inter-processor communication
25	Hea-Sook Park, Sung-Jin Moon, Mee-Hye Lee, Kwang-Suk Song	The design and comparison of two IPC control methods in an ATM switching control system.	RTCSA	1996	DBLP DOI BibTeX RDF	IPC control methods, ATM switching control system, inter-processor communication control, asynchronous transfer mode switching system, indirect control method, local software, direct memory access, main control software, asynchronous transfer mode, local memory
25	Hatem Sellami, Sudhakar Yalamanchili	Time scale combining of conservative parallel discrete event simulations.	IPPS	1995	DBLP DOI BibTeX RDF	time scale combining, inter-processor communication messages, distinct simulations, simulation trials, parallel processing, parallel architectures, discrete event simulation, discrete event simulations, parallel discrete event simulations
25	Ben Lee, Chae Shin, Ali R. Hurson	A strategy for scheduling partially ordered program graphs onto multicomputers.	HICSS (2)	1995	DBLP DOI BibTeX RDF	partially ordered program graphs, scalar performance, user code, compile-time scheduling heuristic, SISAL programs, scheduling, performance evaluation, scalability, parallel programming, message passing, reconfigurable architectures, program compilers, processor scheduling, multicomputers, communication overhead, simulation studies, BLAS, massively parallel processing, message-passing programming, inter-processor communication, message-passing multicomputers
24	Kiyoshi Shibayama, Masaaki Yamamoto, Hiroaki Hirata, Yasushi Konoh, Takanori Sanetoh, Hiroshi Hagiwara	KPR: A Logic Programming Language-Oriented Parallel Machine.	LP	1987	DBLP DOI BibTeX RDF	Parallel Inference Machine, High-Level Language Machine, Parallel Processing, Logic Programming Language
23	Frank E. B. Ophelders, Samarjit Chakraborty, Henk Corporaal	Intra- and inter-processor hybrid performance modeling for MPSoC architectures.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	simulation, performance analysis, system-on-chip
22	Shiao-Li Tsao, Sung-Yuan Lee	Performance Evaluation of Inter-Processor Communication for an Embedded Heterogeneous Multi-Core Processor.	J. Inf. Sci. Eng.	2012	DBLP BibTeX RDF
22	Yan Ying, Kaidi You, Liyang Zhou, Heng Quan, Ming-e Jing, Zhiyi Yu, Xiaoyang Zeng	A pure software ldpc decoder on a multi-core processor platform with reduced inter-processor communication cost.	ISCAS	2012	DBLP DOI BibTeX RDF
22	Guilin Chen, Guangyu Chen, Ozcan Ozturk 0001, Mahmut T. Kandemir	Exploiting Inter-Processor Data Sharing for Improving Behavior of Multi-Processor SoCs.	ISVLSI	2005	DBLP DOI BibTeX RDF
21	Awni Itradat, M. Omair Ahmad, Ali M. Shatnawi	Minimization of I/O Delay in the architectural synthesis of DSP data flow graphs.	ISCAS	2008	DBLP DOI BibTeX RDF
21	Mark D. Hill	How computer architecture trends may affect future distributed systems: from infiniBand clusters to inter-processor speculation (abstract).	PODC	2000	DBLP DOI BibTeX RDF
20	Moo-Kyoung Chung, Heejun Shim, Chong-Min Kyung	Performance Improvement of Multiprocessor Simulation by Optimizing Synchronization a Communication.	IEEE International Workshop on Rapid System Prototyping	2005	DBLP DOI BibTeX RDF
19	Klaus Herrmann 0002, Sören Moch, Jörg Hilgenstock, Peter Pirsch	Implementation of a Multiprocessor System with Distributed Embedded DRAM on a Large Area Integrated Circuit.	DFT	2000	DBLP DOI BibTeX RDF
19	Stamatis G. Kavadias, Manolis Katevenis, Michail Zampetakis, Dimitrios S. Nikolopoulos	On-chip communication and synchronization mechanisms with cache-integrated network interfaces.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	explicit communication, inter-processor synchronization, cache, network interface
19	Junjie Wu 0003, Xiaohui Pan, Guanghui Liu, Baida Zhang, Xuejun Yang	Parallel Data Reuse Theory for OpenMP Applications.	SNPD	2009	DBLP DOI BibTeX RDF	Intra-processor, Inter-processor, Parallel, Locality, Reuse, OpenMP
19	Slo-Li Chu, Chih-Chieh Hsiao, Pin-Hua Chiu	Design a Hardware Mechanism to Utilize Multiprocessors on a Uni-processor Operating System.	ICA3PP	2009	DBLP DOI BibTeX RDF	Xilinx ML310, FPGA, Linux, Multi-core, Inter-Processor Communication
19	Saulo Oliveira Dornellas Luiz, Genildo de Moura Vasconcelos, Leandro Dias da Silva	Formal specification of DSP gateway for data transmission between processor cores of OMAP platform.	SAC	2008	DBLP DOI BibTeX RDF	OMAP161x platform, modelling, model checking, embedded systems, timed-automata, discrete event systems, inter-processor communication
19	Taeweon Suh, Daehyun Kim 0001, Hsien-Hsin S. Lee	Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs.	DAC	2005	DBLP DOI BibTeX RDF	heterogeneous, cache coherence, MPSoC, real-time and embedded systems, inter-processor communication
19	Young-Joo Suh, Kang G. Shin, Syungog An	Configurable Complete Exchanges in 2D Torus-Connected Networks.	ICPP	1999	DBLP DOI BibTeX RDF	parallel algorithms, collective communication, all-to-all communication, complete exchange, all-to-all personalized exchange, inter-processor communication
19	Shuvra S. Bhattacharyya, Sundararajan Sriram, Edward A. Lee	Self-Timed Resynchronization: A Post-Optimization for Static Multiprocessor Schedules.	IPPS	1996	DBLP DOI BibTeX RDF	inter-processor communication overhead, scheduling, embedded systems, synchronization, multiprocessors, static schedules
18	Eryk Laskowski, Marek Tudruj	Embedded Parallel Systems Based on Dynamic Look-Ahead Reconfiguration in Redundant Communication Resources.	DSD	2006	DBLP DOI BibTeX RDF
17	Lukasz Masko, Marek Tudruj	Task Scheduling for SoC-Based Dynamic SMP Clusters with Communication on the Fly.	ISPDC	2008	DBLP DOI BibTeX RDF
17	Marek Tudruj, Lukasz Masko	Dynamic SMP Clusters in SoC Technology - Towards Massively Parallel Fine Grain Numerics.	PPAM	2005	DBLP DOI BibTeX RDF
17	Daniel Cociorva, Xiaoyang Gao, Sandhya Krishnan, Gerald Baumgartner, Chi-Chung Lam, P. Sadayappan, J. Ramanujam	Global Communication Optimization for Tensor Contraction Expressions under Memory Constraints.	IPDPS	2003	DBLP DOI BibTeX RDF
17	Daniel Cociorva, Gerald Baumgartner, Chi-Chung Lam, P. Sadayappan, J. Ramanujam	Memory-Constrained Communication Minimization for a Class of Array Computations.	LCPC	2002	DBLP DOI BibTeX RDF
17	Changhee Jung, Daeseob Lim, Jaejin Lee, Yan Solihin	Helper thread prefetching for loosely-coupled multiprocessor systems.	IPDPS	2006	DBLP DOI BibTeX RDF
16	Sophie Bonneau, Abdelkader Hameurlain	Database Program Mapping onto a Shared-Nothing Multiprocessor Architecture: Minimizing Communication Costs.	Euro-Par	1997	DBLP DOI BibTeX RDF
15	Eryk Laskowski, Marek Tudruj	Optimized Communication Control in Programs for Dynamic Look-Ahead Reconfigurable SoC Systems.	ISPDC	2008	DBLP DOI BibTeX RDF
15	Théodore Marescaux, Erik Brockmeyer, Henk Corporaal	The Impact of Higher Communication Layers on NoC Supported MP-SoCs.	NOCS	2007	DBLP DOI BibTeX RDF
15	Mahmut T. Kandemir, J. Ramanujam, Alok N. Choudhary	Exploiting shared scratch pad memory space in embedded multiprocessor systems.	DAC	2002	DBLP DOI BibTeX RDF	data tiles, memories, compiler optimizations, energy consumption, access patterns, scratch pad, embedded multiprocessors
15	Keiichiro Kagawa, Kouichi Nitta, Yusuke Ogura, Jun Tanida, Yoshiki Ichioka	Architecture Description and Prototype Demonstration of Optoelectronic Parallel-Matching Architecture.	IPDPS Workshops	2000	DBLP DOI BibTeX RDF
15	Hiroaki Fujii, Yoshiko Yasuda, Hideya Akashi, Yasuhiro Inagami, Makoto Koga, Osamu Ishihara, Masamori Kashiyama, Hideo Wada, Tsutomu Sumimoto	Architecture and Performance of the Hitachi SR2201 Massively Parallel Processor System.	IPPS	1997	DBLP DOI BibTeX RDF
14	Daniel Andrade, João Nuno Silva, Miguel Correia 0001	I Can't Escape Myself: Cloud Inter-Processor Attestation and Sealing using Intel SGX.	PRDC	2023	DBLP DOI BibTeX RDF
14	Zhifang Li, Beicheng Peng, Chuliang Weng	XeFlow: Streamlining Inter-Processor Pipeline Execution for the Discrete CPU-GPU Platform.	IEEE Trans. Computers	2020	DBLP DOI BibTeX RDF
14	Emiliano Silvestri, Cristian Milia, Romolo Marotta, Alessandro Pellegrini 0001, Francesco Quaglia	Exploiting Inter-Processor-Interrupts for Virtual-Time Coordination in Speculative Parallel Discrete Event Simulation.	SIGSIM-PADS	2020	DBLP DOI BibTeX RDF
14	Rubén Nieto, Edel Díaz, Raúl Mateos, Álvaro Hernández	Evaluation of Software Inter-Processor Synchronization Methods for the Zynq-UltraScale+ Architecture.	DCIS	2020	DBLP DOI BibTeX RDF
14	El Mostafa Daoudi, Abdelmajid Dargham, Aicha Kerfali, Mohammed Khatiri	Reducing the inter processor migrations of the DP-WRAP scheduling.	AICCSA	2015	DBLP DOI BibTeX RDF
14	Luca Cassano, Dario Cozzi, Dirk Jungewelter, Sebastian Korf, Jens Hagemeyer, Mario Porrmann, Cinzia Bernardeschi	An inter-processor communication interface for data-flow centric heterogeneous embedded multiprocessor systems.	DTIS	2014	DBLP DOI BibTeX RDF
14	Charbel Khawand	Smart Inter-Processor Communicator Protocol Stack.	Encyclopedia of Wireless and Mobile Communications	2008	DBLP BibTeX RDF
14	Manolis Katevenis	Towards unified mechanisms for inter-processor communication.	ICSAMOS	2008	DBLP DOI BibTeX RDF
14	Chengmo Yang, Alex Orailoglu	Light-weight synchronization for inter-processor communication acceleration on embedded MPSoCs.	CASES	2007	DBLP DOI BibTeX RDF	synchronization, interprocessor communication
14	Wim Heirman, Joni Dambre, Jan M. Van Campenhout	Congestion modeling for reconfigurable inter-processor networks.	SLIP	2006	DBLP DOI BibTeX RDF	interconnection network, prediction, reconfiguration, congestion
14	Faramarz Valafar, R. Harris, A. M. Ausin, J. S. Angulo, T. Impelluso	Scalability of VSTM: A Memory Model and Inter-Processor Communication Perspective.	PDPTA	2004	DBLP BibTeX RDF
14	Eryk Laskowski, Marek Tudruj	Time-Transparent Inter-Processor Connection Reconfiguration in Parallel Systems Based on Multiple Crossbar Switches.	PARCO	2003	DBLP BibTeX RDF
14	Mohammad El-Hajj, Osmar R. Zaïane	Parallel Association Rule Mining with Minimum Inter-Processor Communication.	DEXA Workshops	2003	DBLP DOI BibTeX RDF
14	Jessica Yantachka, Frank W. Moore, Gregory Kramer, Michael Echler, Yi Pan 0001	An Improved Genetic Algorithm for Multiprocessor Task Scheduling with Non-Negligible Inter-processor Communication Delay.	MAICS	2003	DBLP BibTeX RDF
14	Guan-Joe Lai, Jywe-Fei Fang, Pei-Shan Sung, Der-Lin Pean	Scheduling Parallel Tasks onto NUMA Multiprocessors with Inter-processor Communication Overhead.	ISPA	2003	DBLP DOI BibTeX RDF
14	Jeremy Ekman, Christoph Berger, Fouad E. Kiamilev, X. Wang, Henk A. E. Spaanenburg, Philippe J. Marchand, Sadik C. Esener	A Distributed Computing Demonstration System Using FSOI Inter-processor Communication.	IPDPS Workshops	2000	DBLP DOI BibTeX RDF
14	Atsushi Kubota, Shogo Tatsumi, Toshihiko Tanaka, Masahiro Goshima, Shin-ichiro Mori, Hiroshi Nakashima, Shinji Tomita	A Technique to Eliminate Redundant Inter-Processor Communication on Parallelizing Compiler TINPAR.	Int. J. Parallel Program.	1999	DBLP DOI BibTeX RDF
14	S. Rosner, M. Scholles, D. Forchel	Near-Optimal Scheduling of Synchronous Data-Flow Graphs by Exact Calculation of Inter-Processor Communication Costs.	HPCN	1997	DBLP DOI BibTeX RDF
14	Atsushi Kubota, Shogo Tatsumi, Toshihiko Tanaka, Masahiro Goshima, Shin-ichiro Mori, Hiroshi Nakashima, Shinji Tomita	A Technique to Eliminate Redundant Inter-Processor Communication on Parallelizing Compiler TINPAR.	ISHPC	1997	DBLP DOI BibTeX RDF
14	Kenji Sayano, Tomonori Shirakawa	Pleiades: A Prototype of Inter-Processor Network Generation System.	ISPAN	1997	DBLP DOI BibTeX RDF
14	Kjell W. Nielsen, Harald Carlsson	Inter-processor communication and Ada in distributed real-time systems.	Comput. Commun.	1990	DBLP DOI BibTeX RDF
14	Shin'ichi Yuta, Jun'ichi Iijima	State information panel for inter-processor communication in an autonomous mobile robot controller-a proposal of the system architecture for autonomous mobile robot.	IROS	1990	DBLP DOI BibTeX RDF
14	Katsuto Nakajima, Nobuyuki Ichiyoshi	Evaluation of Inter-processor Communication in the KL1 Implementation on the Multi-PSI.	ICPP (1)	1990	DBLP BibTeX RDF
14	David R. Manfield, Phuoc Tran-Gia, Herbert Jans	Modelling and Performance Analysis of Inter-Processor Messaging in Distributed Systems.	Perform. Evaluation	1987	DBLP DOI BibTeX RDF
14	T. Hoshiko, Y. Kimura, S. Tomita	A 100Mb/s Optical Token Ring Network Suitable for High-Speed Inter-Processor Communications.	ICDCS	1987	DBLP BibTeX RDF
14	P. A. Hoffman, Christine G. Enke	Inter-processor communications software for a hierarchical system of intelligent laboratory instrumentation.	Comput. Chem.	1983	DBLP DOI BibTeX RDF
14	Marek Tudruj, Lukasz Masko	Dynamic SMP Clusters with Communication on the Fly in NoC Technology for Very Fine Grain Computations.	ISPDC/HeteroPar	2004	DBLP DOI BibTeX RDF	Parallel System Architecture, Shared Memory Systems, Cluster Systems
14	Ching-Hsien Hsu, Kun-Ming Yu	Processor Mapping Technique For Communication Free Data Redistribution on Symmetrical Matrix.	ISPAN	2004	DBLP DOI BibTeX RDF	communication free, runtime support, data redistribution, symmetrical matrix, processor mapping
14	G. D. Nagendra, V. G. Prem Kumar, B. S. Sheshadri Chakravarthy	Simulation bridge: a framework for multi-processor simulation.	CODES	2002	DBLP DOI BibTeX RDF	simulation framework, instruction set simulator, multiprocessor simulation
14	Frank K. H. A. Dehne, Todd Eavis, Susanne E. Hambrusch, Andrew Rau-Chaplin	Parallelizing the Data Cube.	ICDT	2001	DBLP DOI BibTeX RDF
14	R. M. Lea	ASP modules: cost-effective building-blocks for real-time DSP systems.	J. VLSI Signal Process.	1989	DBLP DOI BibTeX RDF
12	Lei Ju 0001, Bach Khoa Huynh, Abhik Roychoudhury, Samarjit Chakraborty	Timing analysis of esterel programs on general-purpose multiprocessors.	DAC	2010	DBLP DOI BibTeX RDF	multiprocessor, timing analysis, synchronous language, esterel
12	Syed Khairuzzaman Tanbeer, Chowdhury Farhan Ahmed, Byeong-Soo Jeong	Parallel and Distributed Frequent Pattern Mining in Large Databases.	HPCC	2009	DBLP DOI BibTeX RDF
12	Hamid R. Arabnia	A Scalable Network Topology for Medical Imaging.	HPCC	2008	DBLP DOI BibTeX RDF
12	Lisane B. de Brisolara, Sang-Il Han, Xavier Guerin, Luigi Carro, Ricardo Reis 0001, Soo-Ik Chae, Ahmed Amine Jerraya	Reducing fine-grain communication overhead in multithread code generation for heterogeneous MPSoC.	SCOPES	2007	DBLP DOI BibTeX RDF
12	Awni Itradat, M. Omair Ahmad, Ali M. Shatnawi	Architectural Synthesis of DSP Applications with Dynamically Reconfigurable Functional Units.	ISCAS	2007	DBLP DOI BibTeX RDF
12	Yusaku Yamamoto	Efficient parallel implementation of a weather derivatives pricing algorithm based on the fast Gauss transform.	IPDPS	2006	DBLP DOI BibTeX RDF
12	Awni Itradat, M. Omair Ahmad, Ali M. Shatnawi	A Delay-Optimal Static Scheduling of DSP Applications Mapped onto Multiprocessor Architectures.	PARELEC	2006	DBLP DOI BibTeX RDF
12	Xing Cai	Improving the Performance of Large-Scale Unstructured PDE Applications.	PARA	2004	DBLP DOI BibTeX RDF
12	Yong Meng Teo, Yew Kwong Ng	SPaDES/Java: Object-Oriented Parallel Discrete-Event Simulatio.	Annual Simulation Symposium	2002	DBLP DOI BibTeX RDF
12	Yong Meng Teo, Y. K. Ng, Bhakti S. S. Onggo	Conservative simulation using distributed-shared memory.	PADS	2002	DBLP DOI BibTeX RDF
12	Marek Tudruj	'Connection by Communication' Paradigm for Dynamically Reconfigurable Multi-Processor Systems.	PARELEC	2000	DBLP DOI BibTeX RDF
12	Thomas Lippert, Armin Seyfried, Achim Bode, Klaus Schilling 0002	Hyper-Systolic Parallel Computing.	IEEE Trans. Parallel Distributed Syst.	1998	DBLP DOI BibTeX RDF	hyper-systolic algorithm, n-body computation, n2-loop computation, connection machine CM5 and Cray T3D, novel complexity class, parallel computer, Systolic algorithm
12	Robert W. Horst	TNet: A Reliable System Area Network.	IEEE Micro	1995	DBLP DOI BibTeX RDF	TNet, routing, reliability, multiprocessor, wormhole routing, multistage interconnect network, flow control, I/O, system area network, massively parallel processing, IPC
11	Zhiyi Yu, Bevan M. Baas	A low-area interconnect architecture for chip multiprocessors.	ISCAS	2008	DBLP DOI BibTeX RDF
11	Ahsan Shabbir, Akash Kumar 0001, Bart Mesman, Henk Corporaal	Enabling MPSoC Design Space Exploration on FPGAs.	IMTIC	2008	DBLP DOI BibTeX RDF	FPGAs, MPSoC, FIFO, FSL
11	Chih-Chi Cheng, Chia-Hua Lin, Chung-Te Li, Samuel C. Chang, Liang-Gee Chen	iVisual: an intelligent visual sensor SoC with 2790fps CMOS image sensor and 205GOPS/W vision processor.	DAC	2008	DBLP DOI BibTeX RDF	vision processor, VLSI, video analysis, SIMD, intelligent sensor
11	Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Julien Lallet, Olivier Sentieys, Sébastien Pillement	Modeling of Interconnection Networks in Massively Parallel Processor Architectures.	ARCS	2007	DBLP DOI BibTeX RDF