Search results for "last-level-cache"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
107	Aamer Jaleel, Matthew Mattina, Bruce L. Jacob	Last level cache (LLC) performance of data mining workloads on a CMP - a case study of parallel bioinformatics workloads.	HPCA	2006	DBLP DOI BibTeX RDF
82	Mainak Chaudhuri	Pseudo-LIFO: the foundation of a new family of replacement policies for last-level caches.	MICRO	2009	DBLP DOI BibTeX RDF	chip-multiprocessor, replacement policy, last-level cache
79	Nikos Hardavellas, Michael Ferdman, Babak Falsafi, Anastasia Ailamaki	Reactive NUCA: near-optimal block placement and replication in distributed caches.	ISCA	2009	DBLP DOI BibTeX RDF	block migration, block placement, block replication, cache indexing, cache lookup, non-uniform cache access, nuca, r-nuca, reactive nuca, rotational interleaving, cache, replication, chip multiprocessor, cmp, placement, multicore, multi-core, migration, cache coherence, data replication, coherence, interleaving, data migration, data placement, shared cache, cache management, lookup, last-level cache, private cache
75	Livio Soares, David K. Tam, Michael Stumm	Reducing the harmful effects of last-level cache polluters with an OS-level, software-only pollute buffer.	MICRO	2008	DBLP DOI BibTeX RDF
55	Jeffrey Stuecheli, Dimitris Kaseridis, David Daly, Hillery C. Hunter, Lizy K. John	The virtual write queue: coordinating DRAM and last-level cache policies.	ISCA	2010	DBLP DOI BibTeX RDF	cmp many-core, ddr ddr2 ddr3, dram-parameters, memory-scheduling writeback, page-mode, write-queue, write-scheduling, dram, cache-replacement, last-level-cache
55	Arkaprava Basu, Nevin Kirman, Meyrem Kirman, Mainak Chaudhuri, José F. Martínez	Scavenger: A New Last Level Cache Architecture with Global Block Priority.	MICRO	2007	DBLP DOI BibTeX RDF
55	Javier Lira, Carlos Molina, Antonio González 0001	The auction: optimizing banks usage in Non-Uniform Cache Architectures.	ICS	2010	DBLP DOI BibTeX RDF	bank replacement policy, non-uniform cache architecture (NUCA), chip multiprocessors (CMP)
44	Guanjun Jiang, Degui Feng, Liangliang Tong, Lingxiang Xiang, Chao Wang 0058, Tianzhou Chen	L1 Collective Cache: Managing Shared Data for Chip Multiprocessors.	APPT	2009	DBLP DOI BibTeX RDF	CMP, cache design, L1 cache
43	Tao Wang 0004, Qigang Wang, Dong Liu, Michael Liao, Kevin Wang, Lu Cao, Li Zhao 0002, Ravi R. Iyer 0001, Ramesh Illikkal, John Du, Liang Wang	Hardware/Software Co-Simulation for Last Level Cache Exploration.	NAS	2009	DBLP DOI BibTeX RDF
39	Haakon Dybdahl, Per Stenström	An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors.	HPCA	2007	DBLP DOI BibTeX RDF
39	Han Jun Bae, Lynn Choi	Filter cache: filtering useless cache blocks for a small but efficient shared last-level cache.	J. Supercomput.	2020	DBLP DOI BibTeX RDF
39	Cesar Gomes, Mark Hempstead	Combative cache efficacy techniques: Cache replacement in the context of independent prefetching in last level cache.	ICCD	2015	DBLP DOI BibTeX RDF
38	Jugash Chandarlapati, Mainak Chaudhuri	LEMap: Controlling leakage in large chip-multiprocessor caches via profile-guided virtual address translation.	ICCD	2007	DBLP DOI BibTeX RDF
38	Shekhar Srikantaiah, Mahmut T. Kandemir, Qian Wang	SHARP control: controlled shared cache management in chip multiprocessors.	MICRO	2009	DBLP DOI BibTeX RDF
35	Bijay Paikaray	Relative Performance of a Multi-level Cache with Last-Level Cache Replacement: An Analytic Review.	CoRR	2013	DBLP BibTeX RDF
35	Aamer Jaleel, Kevin B. Theobald, Simon C. Steely Jr., Joel S. Emer	High performance cache replacement using re-reference interval prediction (RRIP).	ISCA	2010	DBLP DOI BibTeX RDF	scan resistance, thrashing, shared cache, replacement
35	Moinuddin K. Qureshi	Adaptive Spill-Receive for robust high-performance caching in CMPs.	HPCA	2009	DBLP DOI BibTeX RDF
31	Jaspinder Kaur, Shirshendu Das	ACPC: Covert Channel Attack on Last Level Cache using Dynamic Cache Partitioning.	ISQED	2023	DBLP DOI BibTeX RDF
31	Anurag Agarwal, Jaspinder Kaur, Shirshendu Das	Exploiting Secrets by Leveraging Dynamic Cache Partitioning of Last Level Cache.	DATE	2021	DBLP DOI BibTeX RDF
31	Kousik Kumar Dutta, Prathamesh Nitin Tanksale, Shirshendu Das	A Fairness Conscious Cache Replacement Policy for Last Level Cache.	DATE	2021	DBLP DOI BibTeX RDF
31	Ashutosh Dhar, Xiaohao Wang, Hubertus Franke, Jinjun Xiong, Jian Huang 0006, Wen-Mei W. Hwu, Nam Sung Kim, Deming Chen	FReaC Cache: Folded-logic Reconfigurable Computing in the Last Level Cache.	MICRO	2020	DBLP DOI BibTeX RDF
31	Fanfan Shen, Yanxiang He, Jun Zhang 0058, Qingan Li, Jianhua Li 0003, Chao Xu	Reuse locality aware cache partitioning for last-level cache.	Comput. Electr. Eng.	2019	DBLP DOI BibTeX RDF
31	Jungwoo Park, Myoungjun Lee, Soontae Kim, Minho Ju, Jeongkyu Hong	MH Cache: A Mult Stephen Jarvisi-retention STT-RAM-based Low-power Last-level Cache for Mobile Hardware Rendering Systems.	ACM Trans. Archit. Code Optim.	2019	DBLP DOI BibTeX RDF
31	Gangyong Jia, Guangjie Han, Hao Wang 0047, Feng Wang	Cost aware cache replacement policy in shared last-level cache for hybrid memory based fog computing.	Enterp. Inf. Syst.	2018	DBLP DOI BibTeX RDF
31	Martin Rapp, Anuj Pathania, Jörg Henkel	Pareto-Optimal Power- and Cache-Aware Task Mapping for Many-Cores with Distributed Shared Last-Level Cache.	ISLPED	2018	DBLP DOI BibTeX RDF
31	Fazal Hameed, Christian Menard, Jerónimo Castrillón	Efficient STT-RAM last-level-cache architecture to replace DRAM cache.	MEMSYS	2017	DBLP DOI BibTeX RDF
31	Aswinkumar Sridharan, André Seznec	Discrete Cache Insertion Policies for Shared Last Level Cache Management on Large Multicores.	IPDPS	2016	DBLP DOI BibTeX RDF
31	Seunghee Shin, Sihong Kim, Yan Solihin	Dense Footprint Cache: Capacity-Efficient Die-Stacked DRAM Last Level Cache.	MEMSYS	2016	DBLP DOI BibTeX RDF
31	Ju Hee Choi, Jong Wook Kwak, Chu Shik Jhon	Write Avoidance Cache Coherence Protocol for Non-volatile Memory as Last-Level Cache in Chip-Multiprocessor.	IEICE Trans. Inf. Syst.	2014	DBLP DOI BibTeX RDF
31		A Cache Energy Optimization Technique for STT-RAM Last Level Cache.	CoRR	2013	DBLP BibTeX RDF
31	Jorge Albericio, Pablo Ibáñez, Víctor Viñals, José M. Llabería	The reuse cache: downsizing the shared last-level cache.	MICRO	2013	DBLP DOI BibTeX RDF
31	Tao Huang, Jing Wang 0055, Xuetao Guan, Qi Zhong, Keyi Wang	Combining Process-Based Cache Partitioning and Pollute Region Isolation to Improve Shared Last Level Cache Utilization on Multicore Systems.	TrustCom/ISPA/IUCC	2013	DBLP DOI BibTeX RDF
31	Yu-Ting Chen, Jason Cong, Hui Huang 0001, Bin Liu 0006, Chunyue Liu, Miodrag Potkonjak, Glenn Reinman	Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design.	DATE	2012	DBLP DOI BibTeX RDF
31	Deukhyeon Ahn, Jee-hong Kim, JungHyun Han, Young Ik Eom	Reducing Last Level Cache Pollution in NUMA Multicore Systems for Improving Cache Performance.	ICCSA (3)	2012	DBLP DOI BibTeX RDF
31	Jiayuan Meng, Kevin Skadron	Avoiding cache thrashing due to private data placement in last-level cache for manycore scaling.	ICCD	2009	DBLP DOI BibTeX RDF
29	Jason Loew, Dmitry Ponomarev 0001	Two-Level Reorder Buffers: Accelerating Memory-Bound Applications on SMT Architectures.	ICPP	2008	DBLP DOI BibTeX RDF
27	Tao Huang, Qi Zhong, Xuetao Guan, Xiaoyin Wang, Xu Cheng 0001, Keyi Wang	Reducing last level cache pollution through OS-level software-controlled region-based partitioning.	SAC	2012	DBLP DOI BibTeX RDF
24	Yu Chen, Wenlong Li, Junmin Lin, Aamer Jaleel, Zhizhong Tang	Data Sharing Analysis of Emerging Parallel Media Mining Workloads.	HiPC	2008	DBLP DOI BibTeX RDF
24	William B. Langdon, David Clark 0001	Genetic Improvement of Last Level Cache.	EuroGP	2024	DBLP DOI BibTeX RDF
24	Zirui Neil Zhao, Adam Morrison 0001, Christopher W. Fletcher, Josep Torrellas	Last-Level Cache Side-Channel Attacks Are Feasible in the Modern Public Cloud.	ASPLOS (2)	2024	DBLP DOI BibTeX RDF
24	Gregory K. Chen, Phil C. Knag, Carlos Tokunaga, Ram K. Krishnamurthy	An Eight-Core RISC-V Processor With Compute Near Last Level Cache in Intel 4 CMOS.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
24	Daniel A. Jiménez, Elvira Teran, Paul V. Gratz	Last-Level Cache Insertion and Promotion Policy in the Presence of Aggressive Prefetching.	IEEE Comput. Archit. Lett.	2023	DBLP DOI BibTeX RDF
24	Alexandre Valentin Jamet, Lluc Alvarez, Marc Casas	Characterizing the impact of last-level cache replacement policies on big-data workloads.	CoRR	2023	DBLP DOI BibTeX RDF
24	Gianluca Brilli, Paolo Burgio	Interference analysis of shared last-level cache on embedded GP-GPUs with multiple CUDA streams.	CoRR	2023	DBLP DOI BibTeX RDF
24	Fernando García-Redondo, S. Rao, M. Gupta, Manu Perumkunnil, Y. Xiang, D. Abdi, Simon Van Beek, S. Couet, Marie Garcia Bardon	STT-MRAM Stochastic and Defects-aware DTCO for Last Level Cache at Advanced Process Nodes.	ESSDERC	2023	DBLP DOI BibTeX RDF
24	Marcelo Ruaro, Hadrien Barral, Matteo Bertolino, Rodrigo Cataldo, Roberto Medina 0001, Mohamed Karaoui, Etienne Borde	The Last-Level-Cache Interference in Guest Performance: a Case-Study with Zephyr OS.	DSD	2023	DBLP DOI BibTeX RDF
24	Probir Roy, Birhanu Eshete, Pengfei Su 0001	Designing Secure Performance Metrics for Last Level Cache.	IPDPS Workshops	2023	DBLP DOI BibTeX RDF
24	Osang Kwon, Yongho Lee, Seokin Hong	Pinning Page Structure Entries to Last-Level Cache for Fast Address Translation.	IEEE Access	2022	DBLP DOI BibTeX RDF
24	Dawen Xu 0002, Zhuangyu Feng, Cheng Liu 0008, Li Li, Ying Wang 0001, Huawei Li 0001, Xiaowei Li 0001	Taming Process Variations in CNFET for Efficient Last-Level Cache Design.	IEEE Trans. Very Large Scale Integr. Syst.	2022	DBLP DOI BibTeX RDF
24	Fazal Hameed, Jerónimo Castrillón	BlendCache: An Energy and Area Efficient Racetrack Last-Level-Cache Architecture.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2022	DBLP DOI BibTeX RDF
24	Tommaso Marinelli, José Ignacio Gómez Pérez, Christian Tenllado, Manu Komalan, Mohit Gupta 0004, Francky Catthoor	Microarchitectural Exploration of STT-MRAM Last-level Cache Parameters for Energy-efficient Devices.	ACM Trans. Embed. Comput. Syst.	2022	DBLP DOI BibTeX RDF
24	Zhuanhao Wu, Hiren D. Patel	Predictable Sharing of Last-level Cache Partitions for Multi-core Safety-critical Systems.	CoRR	2022	DBLP DOI BibTeX RDF
24	Sina Darabi, Mohammad Sadrosadati, Joël Lindegger, Negar Akbarzadeh, Mohammad Hosseini, Jisung Park 0001, Juan Gómez-Luna, Hamid Sarbazi-Azad, Onur Mutlu	Morpheus: Extending the Last Level Cache Capacity in GPU Systems Using Idle GPU Core Resources.	CoRR	2022	DBLP DOI BibTeX RDF
24	Carlos Escuin, Pablo Ibáñez, Teresa Monreal, José M. Llabería, Víctor Viñals	Forecasting lifetime and performance of a novel NVM last-level cache with compression.	CoRR	2022	DBLP DOI BibTeX RDF
24	Sina Darabi, Mohammad Sadrosadati, Negar Akbarzadeh, Joël Lindegger, Mohammad Hosseini, Jisung Park 0001, Juan Gómez-Luna, Onur Mutlu, Hamid Sarbazi-Azad	Morpheus: Extending the Last Level Cache Capacity in GPU Systems Using Idle GPU Core Resources.	MICRO	2022	DBLP DOI BibTeX RDF
24	Gregory K. Chen, Phil C. Knag, Carlos Tokunaga, Ram K. Krishnamurthy	An 8-core RISC-V Processor with Compute near Last Level Cache in Intel 4 CMOS.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
24	Ya-Hui Yang, Shuo-Han Chen, Yuan-Hao Chang 0001	Evolving Skyrmion Racetrack Memory as Energy-Efficient Last-Level Cache Devices.	ISLPED	2022	DBLP DOI BibTeX RDF
24	Javier Barrera, Leonidas Kosmidis, Hamid Tabani, Jaume Abella 0001, Francisco J. Cazorla	Contention Tracking in GPU Last-Level Cache.	ICCD	2022	DBLP DOI BibTeX RDF
24	Yashika Verma, Biswabandan Panda	Avenger: Punishing the Cross-Core Last-Level Cache Attacker and Not the Victim by Isolating the Attacker.	SEED	2022	DBLP DOI BibTeX RDF
24	Zhuanhao Wu, Hiren D. Patel	Predictable sharing of last-level cache partitions for multi-core safety-critical systems.	DAC	2022	DBLP DOI BibTeX RDF
24	Tomohiro Korikawa, Akio Kawabata, Fujun He, Eiji Oki	Packet Processing Architecture with Off-Chip Last Level Cache Using Interleaved 3D-Stacked DRAM.	IEICE Trans. Commun.	2021	DBLP BibTeX RDF
24	Jen-Wei Hsieh, Yi-Yu Liu, Hung-Tse Lee, Tai Chang	TSE: Two-Step Elimination for MLC STT-RAM Last-Level Cache.	IEEE Trans. Computers	2021	DBLP DOI BibTeX RDF
24	Qianqian Wu, Zhenzhou Ji	A perceptron-based replication scheme for managing the shared last level cache.	Microprocess. Microsystems	2021	DBLP DOI BibTeX RDF
24	Candace Walden, Devesh Singh, Meenatchi Jagasivamani, Shang Li 0001, Luyi Kang, Mehdi Asnaashari, Sylvain Dubois, Bruce L. Jacob, Donald Yeung	Monolithically Integrating Non-Volatile Main Memory over the Last-Level Cache.	ACM Trans. Archit. Code Optim.	2021	DBLP DOI BibTeX RDF
24	Dawen Xu 0002, Zhuangyu Feng, Cheng Liu 0008, Li Li, Ying Wang 0001, Yuanqing Cheng, Huawei Li 0001, Xiaowei Li 0001	Taming Process Variations in CNFET for Efficient Last Level Cache Design.	CoRR	2021	DBLP BibTeX RDF
24	Sidharth Rao, Woojin Kim, Simon Van Beek, Shreya Kundu, Manu Perumkunnil, Stefan Cosemans, Farrukh Yasin, Sebastien Couet, Robert Carpenter, Barry J. O'Sullivan, Shamin H. Sharifi, N. Jossart, Laurent Souriau, Ludovic Goux, Dimitri Crotti, Gouri Sankar Kar	STT-MRAM array performance improvement through optimization of Ion Beam Etch and MTJ for Last-Level Cache application.	IMW	2021	DBLP DOI BibTeX RDF
24	Xiaoyang Lu, Rujia Wang, Xian-He Sun	Premier: A Concurrency-Aware Pseudo-Partitioning Framework for Shared Last-Level Cache.	ICCD	2021	DBLP DOI BibTeX RDF
24	Sukarn Agarwal, Shounak Chakraborty 0001	ABACa: Access Based Allocation on Set Wise Multi-Retention in STT-RAM Last Level Cache.	ASAP	2021	DBLP DOI BibTeX RDF
24	Mohammad Shahrad, Sameh Elnikety, Ricardo Bianchini	Provisioning Differentiated Last-Level Cache Allocations to VMs in Public Clouds.	SoCC	2021	DBLP DOI BibTeX RDF
24	Mainak Chaudhuri	Zero Inclusion Victim: Isolating Core Caches from Inclusive Last-level Cache Evictions.	ISCA	2021	DBLP DOI BibTeX RDF
24	Tomohiro Korikawa, Akio Kawabata, Fujun He, Eiji Oki	Packet Processing Architecture Using Last-Level-Cache Slices and Interleaved 3D-Stacked DRAM.	IEEE Access	2020	DBLP DOI BibTeX RDF
24	Jiacheng Ni, Keren Liu, Bi Wu, Weisheng Zhao, Yuanqing Cheng, Xiaolong Zhang, Ying Wang 0001	Write Back Energy Optimization for STT-MRAM-based Last-level Cache with Data Pattern Characterization.	ACM J. Emerg. Technol. Comput. Syst.	2020	DBLP DOI BibTeX RDF
24	Bi Wu, Weisheng Zhao, Xiaobo Sharon Hu, Pengcheng Dai, Zhaohao Wang, Chao Wang 0094, Ying Wang 0001, Jianlei Yang 0001, Yuanqing Cheng, Dijun Liu, Youguang Zhang	Bulkyflip: A NAND-SPIN-Based Last-Level Cache With Bandwidth-Oriented Write Management Policy.	IEEE Trans. Circuits Syst. I Regul. Pap.	2020	DBLP DOI BibTeX RDF
24	Xian-Shu Li, Su-Kyung Yoon, Jeong-Geun Kim, Bernd Burgstaller, Shin-Dug Kim	Algorithm-Switching-Based Last-Level Cache Structure with Hybrid Main Memory Architecture.	Comput. J.	2020	DBLP DOI BibTeX RDF
24	Alexandre Valentin Jamet, Lluc Alvarez, Daniel A. Jiménez, Marc Casas	Characterizing the impact of last-level cache replacement policies on big-data workloads.	IISWC	2020	DBLP DOI BibTeX RDF
24	Jiaheng Liu, Ryusuke Egawa, Mulya Agung, Hiroyuki Takizawa	A Conflict-Aware Capacity Control Mechanism for Last-Level Cache.	CANDAR (Workshops)	2020	DBLP DOI BibTeX RDF
24	Fazal Hameed, Jerónimo Castrillón	A Novel Hybrid DRAM/STT-RAM Last-Level-Cache Architecture for Performance, Energy, and Endurance Enhancement.	IEEE Trans. Very Large Scale Integr. Syst.	2019	DBLP DOI BibTeX RDF
24	Jing-Yuan Luo, Hsiang-Yun Cheng, Ing-Chao Lin, Da-Wei Chang	TAP: Reducing the Energy of Asymmetric Hybrid Last-Level Cache via Thrashing Aware Placement and Migration.	IEEE Trans. Computers	2019	DBLP DOI BibTeX RDF
24	Alexandra Ferrerón-Labari, Jesús Alastruey-Benedé, Darío Suárez Gracia, Teresa Monreal Arnal, Pablo Ibáñez-Marín, Víctor Viñals Yúfera	A fault-tolerant last level cache for CMPs operating at ultra-low voltage.	J. Parallel Distributed Comput.	2019	DBLP DOI BibTeX RDF
24	Yang Song 0006, Olivier Alavoine, Bill Lin 0001	Harvesting Row-Buffer Hits via Orchestrated Last-Level Cache and DRAM Scheduling for Heterogeneous Multicore Systems.	ACM Trans. Design Autom. Electr. Syst.	2019	DBLP DOI BibTeX RDF
24	Biswabandan Panda	Fooling the Sense of Cross-core Last-level Cache Eviction based Attacker by Prefetching Common Sense.	IACR Cryptol. ePrint Arch.	2019	DBLP BibTeX RDF
24	Sheela Kathavate, Lakshmi Rajesh, N. K. Srinath	PR-LRU: partial random LRU technique for performance improvement of last level cache.	Int. J. Comput. Aided Eng. Technol.	2019	DBLP DOI BibTeX RDF
24	Anatoly Shusterman, Lachlan Kang, Yarden Haskal, Yosef Meltzer, Prateek Mittal, Yossi Oren, Yuval Yarom	Website Fingerprinting - Last Level Cache Contention Traces.		2019	DOI RDF
24	Biswabandan Panda	Fooling the Sense of Cross-Core Last-Level Cache Eviction Based Attacker by Prefetching Common Sense.	PACT	2019	DBLP DOI BibTeX RDF
24	Jongwook Chung, Yuhwan Ro, Joonsung Kim, Jaehyung Ahn, Jangwoo Kim, John Kim, Jae W. Lee, Jung Ho Ahn	Enforcing Last-Level Cache Partitioning through Memory Virtual Channels.	PACT	2019	DBLP DOI BibTeX RDF
24	Dawen Xu 0002, Li Li, Ying Wang 0001, Cheng Liu 0008, Huawei Li 0001	Exploring emerging CNFET for efficient last level cache design.	ASP-DAC	2019	DBLP DOI BibTeX RDF
24	Ganghee Jang, Jean-Luc Gaudiot	Data Shepherding: A Last Level Cache Design for Large Scale Chips.	HPCC/SmartCity/DSS	2019	DBLP DOI BibTeX RDF
24	Swapnil Bhosale, Sudeep Pasricha	SLAM: High Performance and Energy Efficient Hybrid Last Level Cache Architecture for Multicore Embedded Systems.	ICESS	2019	DBLP DOI BibTeX RDF
24	Yu-Pei Liang, Tseng-Yi Chen, Yuan-Hao Chang 0001, Shuo-Han Chen, Pei-Yu Chen, Wei-Kuan Shih	Rethinking Last-level-cache Write-back Strategy for MLC STT-RAM Main Memory with Asymmetric Write Energy.	ISLPED	2019	DBLP DOI BibTeX RDF
24	Raphael Durner, Christian Sieber, Wolfgang Kellerer	Towards Reducing Last-Level-Cache Interference of Co-Located Virtual Network Functions.	ICCCN	2019	DBLP DOI BibTeX RDF
24	Alexander Hankin, Tomer Shapira, Karthik Sangaiah, Michael Lui, Mark Hempstead	Evaluation of Non-Volatile Memory Based Last Level Cache Given Modern Use Case Behavior.	IISWC	2019	DBLP DOI BibTeX RDF
24	Huanxing Shen, Cong Li	Detecting Last-Level Cache Contention in Workload Colocation with Meta Learning.	IISWC	2019	DBLP DOI BibTeX RDF
24	Alireza Farshin, Amir Roozbeh, Gerald Q. Maguire Jr., Dejan Kostic	Make the Most out of Last Level Cache in Intel Processors.	EuroSys	2019	DBLP DOI BibTeX RDF
24	Jinsu Park, Seongbeom Park, Woongki Baek	CoPart: Coordinated Partitioning of Last-Level Cache and Memory Bandwidth for Fairness-Aware Workload Consolidation on Commodity Servers.	EuroSys	2019	DBLP DOI BibTeX RDF
24	Burak Sezin Ovant, Isa Ahmet Güney, Muhammed Emin Savas, Gürhan Küçük	Last level cache partitioning via multiverse thread classification.	Turkish J. Electr. Eng. Comput. Sci.	2018	DBLP DOI BibTeX RDF
24	Fazal Hameed, Asif Ali Khan, Jerónimo Castrillón	Performance and Energy-Efficient Design of STT-RAM Last-Level Cache.	IEEE Trans. Very Large Scale Integr. Syst.	2018	DBLP DOI BibTeX RDF
24	Lan Gao, Rui Wang 0014, Yunlong Xu, Hailong Yang, Zhongzhi Luan, Depei Qian, Han Zhang, Jihong Cai	SRAM- and STT-RAM-based hybrid, shared last-level cache for on-chip CPU-GPU heterogeneous architectures.	J. Supercomput.	2018	DBLP DOI BibTeX RDF
24	Jingyu Zhang, Minyi Guo, Chentao Wu, Yuanyi Chen	Toward multi-programmed workloads with different memory footprints: a self-adaptive last level cache scheduling scheme.	Sci. China Inf. Sci.	2018	DBLP DOI BibTeX RDF
24	Guan Wang, Chuanqi Zang, Lei Ju 0001, Mengying Zhao, Xiaojun Cai, Zhiping Jia	Shared Last-Level Cache Management and Memory Scheduling for GPGPUs with Hybrid Main Memory.	ACM Trans. Embed. Comput. Syst.	2018	DBLP DOI BibTeX RDF
24	Yumna Zahid, Hina Khurshid, Zulfiqar Ali Memon	On Improving Efficiency and Utilization of Last Level Cache in Multicore Systems.	Inf. Technol. Control.	2018	DBLP DOI BibTeX RDF