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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 18 occurrences of 15 keywords
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Results
Found 5 publication records. Showing 5 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
75 | Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian |
Easily Testable Cellular Carry Lookahead Adders. |
J. Electron. Test. |
2003 |
DBLP DOI BibTeX RDF |
cellular carry lookahead adders, linear-testability, design-for-testability, cell fault model |
34 | Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis |
Robust Sequential Fault Testing of Iterative Logic Arrays. |
VTS |
1997 |
DBLP DOI BibTeX RDF |
Sequential Faults, Linear-testability, Fault Modeling, Automatic Test Generation, C-testability, Iterative Logic Arrays |
34 | Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis |
Testing combinational iterative logic arrays for realistic faults. |
VTS |
1995 |
DBLP DOI BibTeX RDF |
combinational iterative logic arrays, realistic faults, two-dimensional logic arrays, one-dimensional logic arrays, n-pattern tests, linear-testability, efficient test set, ILA, VLSI, fault diagnosis, logic testing, integrated circuit testing, combinational circuits, cellular arrays, logic arrays, C-testability, cell fault model |
17 | Fabrizio Lombardi, Donatella Sciuto |
Linear testability conditions for two-dimensional arrays. |
Microprocess. Microprogramming |
1989 |
DBLP DOI BibTeX RDF |
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17 | Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian |
Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays. |
IEEE Trans. Computers |
2000 |
DBLP DOI BibTeX RDF |
Sequential fault modeling, test pattern generation, robust testing, iterative logic arrays |
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