Search results for "litho"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
87	Min-Chun Tsai, Daniel Zhang, Zongwu Tang	Modeling Litho-Constrained Design Layout.	DAC	2007	DBLP DOI BibTeX RDF
87	Manish Garg, Aatish Kumar, Johannes van Wingerden, Laurent Le Cam	Litho-driven layouts for reducing performance variability.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
77	Manish Garg, Laurent Le Cam, Matthieu Gonzalez	Lithography Driven Layout Design.	VLSI Design	2005	DBLP DOI BibTeX RDF
58	Minsik Cho, Kun Yuan, Yongchan Ban, David Z. Pan	ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction.	DAC	2008	DBLP DOI BibTeX RDF	routing, VLSI, manufacturability, OPC, lithography
58	Sean X. Shi, Peng Yu, David Z. Pan	A unified non-rectangular device and circuit simulation model for timing and power.	ICCAD	2006	DBLP DOI BibTeX RDF	physical design, VLSI CAD, device modeling
49	Shankar Krishnamoorthy	Variation and litho driven physical implementation system.	ISPD	2007	DBLP DOI BibTeX RDF	multi-variation optimization, VLSI, lithography
49	Yong-Chan Ban, Soo-Han Choi, Ki-Hung Lee, Dong-Hyun Kim, Jisuk Hong, Yoo-Hyon Kim, Moon-Hyun Yoo, Jeong-Taek Kong	A Fast Lithography Verification Framework for Litho-Friendly Layout Design.	ISQED	2005	DBLP DOI BibTeX RDF
38	Andrew B. Kahng	How to get real mad.	ISPD	2008	DBLP DOI BibTeX RDF	design-aware manufacturing, integrated circuit physical design, manufacturing-aware design, performance analysis, design for manufacturability
38	Hua Xiang 0001, Liang Deng, Li-Da Huang, Martin D. F. Wong	OPC-Friendly Bus Driven Floorplanning.	ISQED	2007	DBLP DOI BibTeX RDF
33	Stephen P. Kornachuk, Michael C. Smayling	New strategies for gridded physical design for 32nm technologies and beyond.	ISPD	2009	DBLP DOI BibTeX RDF	28nm, 32nm, 45nm, litho, rdr, placement, layout, physical design, manufacturability, lithography, standard cell, vlsi, drc, dfm
33	Robert P. Martin, B. Nassersharif	A Diagnostic Expert System for Analyzing Multiple-Failure Transients in Nuclear Power Plants.	IEA/AIE (Vol. 1)	1988	DBLP DOI BibTeX RDF	LITHO
29	Galena Jordanova, Timotej Verbovsek	Improved Automatic Classification of Litho-Geomorphological Units by Using Raster Image Blending, Vipava Valley (SW Slovenia).	Remote. Sens.	2023	DBLP DOI BibTeX RDF
29	Qing Zhang, Yuhang Zhang, Wei Lu, Huajie Huang, Zheng Zhong, Congshu Zhou, Yongfu Li	Litho-AsymVnet: super-resolution lithography modeling with an asymmetric V-net architecture.	Sci. China Inf. Sci.	2023	DBLP DOI BibTeX RDF
29	Qing Zhang 0008, Yuhang Zhang, Jizuo Li, Wei Lu, Yongfu Li 0002	Litho-NeuralODE 2.0: Improving hotspot detection accuracy with advanced data augmentation, DCT-based features, and neural ordinary differential equations.	Integr.	2022	DBLP DOI BibTeX RDF
29	Haoyu Yang, Zongyi Li, Kumara Sastry, Saumyadip Mukhopadhyay, Anima Anandkumar, Brucek Khailany, Vivek Singh, Haoxing Ren	Large Scale Mask Optimization Via Convolutional Fourier Neural Operator and Litho-Guided Self Training.	CoRR	2022	DBLP DOI BibTeX RDF
29	Wei Lu, Yuhang Zhang, Qing Zhang 0008, Xinjie Zhang, Yongfu Li 0002	Litho-NeuralODE: Improving Hotspot Detection Accuracy with Advanced Data Augmentation and Neural Ordinary Differential Equations.	ACM Great Lakes Symposium on VLSI	2020	DBLP DOI BibTeX RDF
29	Jun Huang 0004, Lei Zou, Peng Tian, Quan Zhang, Yuan Wang, Jian-Hui Zhang	A Valveless Piezoelectric Micropump Based on Projection Micro Litho Stereo Exposure Technology.	IEEE Access	2019	DBLP DOI BibTeX RDF
29	Wei Ye 0008, Mohamed Baker Alawieh, Meng Li 0004, Yibo Lin, David Z. Pan	Litho-GPA: Gaussian Process Assurance for Lithography Hotspot Detection.	DATE	2019	DBLP DOI BibTeX RDF
29	Jea Woo Park, Andres Torres, Xiaoyu Song	Litho-Aware Machine Learning for Hotspot Detection.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2018	DBLP DOI BibTeX RDF
29	Minoo Mirsaeedi, Andres J. Torres, Mohab H. Anis	Litho-Friendly Decomposition Method for Self-Aligned Triple Patterning.	IEEE Trans. Very Large Scale Integr. Syst.	2014	DBLP DOI BibTeX RDF
29	Minoo Mirsaeedi, Andres J. Torres, Mohab H. Anis	Litho-Friendly Decomposition Method for Self-Aligned Double Patterning.	IEEE Trans. Very Large Scale Integr. Syst.	2013	DBLP DOI BibTeX RDF
29	Bing Yan, Hsin Yuan Chen, Peter B. Luh, Simon Wang, Joey Chang	Litho Machine Scheduling With Convex Hull Analyses.	IEEE Trans Autom. Sci. Eng.	2013	DBLP DOI BibTeX RDF
29	Raghavan Kumar, Wayne P. Burleson	Litho-aware and low power design of a secure current-based physically unclonable function.	ISLPED	2013	DBLP DOI BibTeX RDF
29	Vibhu Sharma, Stefan Cosemans, Maryam Ashouei, Jos Huisken, Francky Catthoor, Wim Dehaene	Ultra low power litho friendly local assist circuitry for variability resilient 8T SRAM.	DATE	2012	DBLP DOI BibTeX RDF
29	Bing Yan, Hsin Yuan Chen, Peter B. Luh, Simon Wang, Joey Chang	Optimization-based litho machine scheduling with load balancing and reticle expiration.	CASE	2012	DBLP DOI BibTeX RDF
29	Bin Li, Feiyan Liao, Hao Meng, Yanchun Zhong	Application of spatial database in quantitative analysis of litho-paleogeography - A case study of a middle ordovician sequence interval in the Ordos Basin.	Geo spatial Inf. Sci.	2011	DBLP DOI BibTeX RDF
29	Sergio Gómez, Francesc Moll, Antonio Rubio 0001, Martin Elhøj, Guilherme Schlinker, Nigel Woolaway	Design Guidelines towards Compact Litho-Friendly Regular cells.	ARCS Workshops	2011	DBLP BibTeX RDF
29	Vivek Singh	Litho and design: moore close than ever.	ISPD	2011	DBLP DOI BibTeX RDF
29	Bing Yan, Hsin Yuan Chen, Peter B. Luh, Simon Wang, Joey Chang	Optimization-based litho machine scheduling with multiple reticles and setups.	CASE	2011	DBLP DOI BibTeX RDF
29	Rance Rodrigues, Sandip Kundu	A mask double patterning technique using litho simulation by wavelet transform.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	double patterning lithography, edge placement error, polygon stitch, wavelet transform
29	Lanny L. Lewyn, Markus Loose	A 1.5mW 16b ADC with improved segmentation and centroiding algorithms and litho-friendly physical design (LFD) used in space telescope imaging applications.	CICC	2009	DBLP DOI BibTeX RDF
29	Franklin M. Schellenberg	Design for Manufacturing in the Semiconductor Industry: The Litho/Design Workshops.	VLSI Design	1999	DBLP DOI BibTeX RDF
19	Yang-Shan Tong, Chia-Wei Lin, Sao-Jie Chen	An automatic optical-simulation-based lithography hotspot fix flow for post-route optimization.	ISPD	2009	DBLP DOI BibTeX RDF	routing, opc, lithography, hotspot
19	Wojciech Maly	Vertical slit transistor based integrated circuits (VeSTICs) paradigm.	ISPD	2009	DBLP DOI BibTeX RDF	dual gate transistor, ic deign-manufacturing paradigm, vertical channel, vesfet, 3d integration, regular fabric, dfm
19	Nancy Ying Zhou, Rouwaida Kanj, Kanak Agarwal, Zhuo Li 0001, Rajiv V. Joshi, Sani R. Nassif, Weiping Shi	The impact of BEOL lithography effects on the SRAM cell performance and yield.	ISQED	2009	DBLP DOI BibTeX RDF
19	Rob Aitken, Jerry Bautista, Wojciech Maly, Jan M. Rabaey	More Moore: foolish, feasible, or fundamentally different?	ICCAD	2008	DBLP DOI BibTeX RDF
19	Jason Cong, Karthik Gururaj, Guoling Han, Adam Kaplan, Mishali Naik, Glenn Reinman	MC-Sim: an efficient simulation tool for MPSoC designs.	ICCAD	2008	DBLP DOI BibTeX RDF
19	Aswin Sreedhar, Sandip Kundu	Modeling and analysis of non-rectangular transistors caused by lithographic distortions.	ICCD	2008	DBLP DOI BibTeX RDF
19	Nancy Ying Zhou, Zhuo Li 0001, Yuxin Tian, Weiping Shi, Frank Liu 0001	A New Methodology for Interconnect Parasitics Extraction Considering Photo-Lithography Effects.	ASP-DAC	2007	DBLP DOI BibTeX RDF
19	David Cross, Eric Nequist, Louis Scheffer	A DFM aware, space based router.	ISPD	2007	DBLP DOI BibTeX RDF
19	Aswin Sreedhar, Sandip Kundu	On modeling impact of sub-wavelength lithography on transistors.	ICCD	2007	DBLP DOI BibTeX RDF
19	Philippe Magarshack	Design challenges in 45nm and below: DFM, low-power and design for reliability.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	design for reliability, low-power design, design for manufacturability
19	Ritu Singhal, Asha Balijepalli, Anupama R. Subramaniam, Frank Liu 0001, Sani R. Nassif, Yu Cao 0001	Modeling and Analysis of Non-Rectangular Gate for Post-Lithography Circuit Simulation.	DAC	2007	DBLP DOI BibTeX RDF
19	Mark A. Lavin, Lars Liebmann	CAD computation for manufacturability: can we save VLSI technology from itself?	ICCAD	2002	DBLP DOI BibTeX RDF
19	Franklin M. Schellenberg, Luigi Capodieci	Impact of RET on physical layouts.	ISPD	2001	DBLP DOI BibTeX RDF	off-axis illumination, physical verification, simulation, DFM, OPC, lithography, RET, phase-shifting, PSM
19	Warren Grobman, Robert Boone, Cece Philbin, Bob Jarvis	Reticle enhancement technology trends: resource and manufacturability implications for the implementation of physical designs.	ISPD	2001	DBLP DOI BibTeX RDF