Search results for "lithography"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
101	Andrzej J. Strojwas, Tejas Jhaveri, Vyacheslav Rovner, Lawrence T. Pileggi	Creating an affordable 22nm node using design-lithography co-optimization.	DAC	2009	DBLP DOI BibTeX RDF	design technology co-optimization, templates, DFM, regular fabric
89	David Z. Pan	Lithography friendly routing: from construct-by-correction to correct-by-construction.	SBCCI	2008	DBLP DOI BibTeX RDF	routing
84	B. D. Cook, Soo-Young Lee	Fast exposure simulation for large circuit patterns in electron beam lithography.	ICIP	1995	DBLP DOI BibTeX RDF	electron beam lithography, proximity effect (lithography), fast exposure simulation, large circuit patterns, electron beam lithography, global exposure, local exposure, proximity effect, simulation
83	Tai-Chen Chen, Guang-Wan Liao, Yao-Wen Chang	Predictive formulae for OPC with applications to lithography-friendly routing.	DAC	2008	DBLP DOI BibTeX RDF	routing, DFM, OPC, lithography, RET
79	Rance Rodrigues, Sandip Kundu	A mask double patterning technique using litho simulation by wavelet transform.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	double patterning lithography, edge placement error, polygon stitch, wavelet transform
72	David Z. Pan, Stephen Renwick, Vivek Singh, Judy Huckabay	Nanolithography and CAD challenges for 32nm/22nm and beyond.	ICCAD	2008	DBLP DOI BibTeX RDF
72	Shiyan Hu, Jiang Hu	Pattern sensitive placement for manufacturability.	ISPD	2007	DBLP DOI BibTeX RDF	placement, physical design, manufacturability
71	Yue Xu, Chris Chu	A matching based decomposer for double patterning lithography.	ISPD	2010	DBLP DOI BibTeX RDF	doubel patterning lithography, planar graph, matching algorithm
71	Yang-Shan Tong, Chia-Wei Lin, Sao-Jie Chen	An automatic optical-simulation-based lithography hotspot fix flow for post-route optimization.	ISPD	2009	DBLP DOI BibTeX RDF	routing, opc, lithography, hotspot
71	Liang Deng, Martin D. F. Wong, Kai-Yuan Chao, Hua Xiang 0001	Coupling-aware Dummy Metal Insertion for Lithography.	ASP-DAC	2007	DBLP DOI BibTeX RDF	coupling-aware dummy metal insertion, integrated circuits manufacturing technology, resolution enhancement techniques, off-axis illumination, forbidden pitches, printability improvement, invisible dummy metal segments, lithography cost minimization, optimal algorithm, chemical mechanical polish
64	Phiroze N. Parakh, Shankar Krishnamoorthy	A robust approach to lithography friendly design implementation.	ISPD	2008	DBLP DOI BibTeX RDF
64	Colin P. Williams, Pieter Kok, Hwang Lee, Jonathan P. Dowling	Quantum lithography: A non-computing application of quantum information.	Inform. Forsch. Entwickl.	2006	DBLP DOI BibTeX RDF
64	Edward W. Scheckler, Nelson N. Tam, Anton K. Pfau, Andrew R. Neureuther	An efficient volume-removal algorithm for practical three-dimensional lithography simulation with experimental verification.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
59	Pratik J. Shah, Jiang Hu	Impact of lithography-friendly circuit layout.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	cd variation, lithography, wirelength, routing congestion
59	Dragoljub Gagi Drmanac, Frank Liu 0001, Li-C. Wang	Predicting variability in nanoscale lithography processes.	DAC	2009	DBLP DOI BibTeX RDF	modeling variability, photo lithography, machine learning, process variation, kernel methods
59	Peng Yu, Sean X. Shi, David Z. Pan	Process variation aware OPC with variational lithography modeling.	DAC	2006	DBLP DOI BibTeX RDF	lithography modeling, process variation, OPC
59	Jihyun Kim 0001, Sanghyeok Seo, Sung-Shick Kim	Neural Networks Fusion to Overlay Control System for Lithography Process.	Australian Conference on Artificial Intelligence	2006	DBLP DOI BibTeX RDF	Run-to-Run Control, Neural Networks, Lithography
55	Shankar Krishnamoorthy	Variation and litho driven physical implementation system.	ISPD	2007	DBLP DOI BibTeX RDF	multi-variation optimization, VLSI, lithography
53	Linda Dailey Paulson	New Lithography Approach Promises Powerful Chips.	Computer	2010	DBLP DOI BibTeX RDF	bootup, BIOS, United Extensible Firmware Interface, extreme ultraviolet lithography, deep ultraviolet lithography, medical camera, accelerometer, data glove, OS, CMOS image sensor
52	Munkang Choi, Linda S. Milor	Diagnosis of Optical Lithography Faults With Product Test Sets.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
52	Manseung Seo, Jaesung Song, Changgeun An	Region-Based Pattern Generation Scheme for DMD Based Maskless Lithography.	GREC	2005	DBLP DOI BibTeX RDF
52	Nikos Glezos, Ioannis Raptis	A fast electron beam lithography simulator based on the Boltzmann transport equation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
48	Andrew B. Kahng	How to get real mad.	ISPD	2008	DBLP DOI BibTeX RDF	design-aware manufacturing, integrated circuit physical design, manufacturing-aware design, performance analysis, design for manufacturability
47	Yongchan Ban, David Z. Pan	Compact modeling and robust layout optimization for contacts in deep sub-wavelength lithography.	DAC	2010	DBLP DOI BibTeX RDF	optimization, VLSI, DFM, variation, lithography, contact
47	Kanak Agarwal	Frequency domain decomposition of layouts for double dipole lithography.	DAC	2010	DBLP DOI BibTeX RDF	decomposition, layout, OPC, lithography, OAI, DDL
47	Liangliang Yang, Yunfei Zhou, Haihong Pan, Wei Teng	Realization of the Synchronization Mechanism of Step and Scan Projection Lithography.	ICIRA (2)	2008	DBLP DOI BibTeX RDF	Step and scan projection lithography, state synchronization, high speed high precision motion control, synchronization control
47	Minsik Cho, Kun Yuan, Yongchan Ban, David Z. Pan	ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction.	DAC	2008	DBLP DOI BibTeX RDF	routing, VLSI, manufacturability, OPC, lithography
43	Kwangok Jeong, Andrew B. Kahng, Rasit Onur Topaloglu	Is overlay error more important than interconnect variations in double patterning?	SLIP	2009	DBLP DOI BibTeX RDF	double patterning lithography, interconnect variations, overlay
43	Yufu Zhang, Zheng Shi	A New Method of Implementing Hierarchical OPC.	ISQED	2007	DBLP DOI BibTeX RDF	Sub-wavelength Lithography, Cell-wise, EPE, Hierarchy, DFM, OPC, RET
43	Puneet Gupta 0001, Andrew B. Kahng, Dennis Sylvester, Jie Yang 0010	A cost-driven lithographic correction methodology based on off-the-shelf sizing tools.	DAC	2003	DBLP DOI BibTeX RDF	VLSI manufacturability, yield, OPC, lithography, RET
40	Yen-Hung Lin, Yih-Lang Li	Double patterning lithography aware gridless detailed routing with innovative conflict graph.	DAC	2010	DBLP DOI BibTeX RDF	double patterning, gridless model, detailed routing
40	Kwangok Jeong, Andrew B. Kahng	Timing analysis and optimization implications of bimodal CD distribution in double patterning lithography.	ASP-DAC	2009	DBLP DOI BibTeX RDF
40	Stanley H. Chan, Edmund Y. Lam	Inverse image problem of designing phase shifting masks in optical lithography.	ICIP	2008	DBLP DOI BibTeX RDF
40	Jinyu Zhang, Wei Xiong, Yan Wang 0023, Zhiping Yu, Min-Chun Tsai	A highly efficient optimization algorithm for pixel manipulation in inverse lithography technique.	ICCAD	2008	DBLP DOI BibTeX RDF
40	Ritu Singhal, Asha Balijepalli, Anupama R. Subramaniam, Frank Liu 0001, Sani R. Nassif, Yu Cao 0001	Modeling and Analysis of Non-Rectangular Gate for Post-Lithography Circuit Simulation.	DAC	2007	DBLP DOI BibTeX RDF
40	Peter Wright, Minghui Fan	A DFM Methodology to Evaluate the Impact of Lithography Conditions on the Speed of Critical Paths in a VLSI Circuit.	ISQED	2006	DBLP DOI BibTeX RDF
40	Yong-Chan Ban, Soo-Han Choi, Ki-Hung Lee, Dong-Hyun Kim, Jisuk Hong, Yoo-Hyon Kim, Moon-Hyun Yoo, Jeong-Taek Kong	A Fast Lithography Verification Framework for Litho-Friendly Layout Design.	ISQED	2005	DBLP DOI BibTeX RDF
40	Manish Garg, Laurent Le Cam, Matthieu Gonzalez	Lithography Driven Layout Design.	VLSI Design	2005	DBLP DOI BibTeX RDF
40	Louis Scheffer	Physical CAD changes to incorporate design for lithography and manufacturability.	ASP-DAC	2004	DBLP DOI BibTeX RDF
40	Noppachai Anupongpaibool, Soo-Young Lee	Distributed Correction of Proximity Effect in Electron Beam Lithography on a Heterogeneous Cluster.	IPDPS	2004	DBLP DOI BibTeX RDF
40	Jun-ho Jeong, Young-suk Sim, Hyonkee Sohn, Eung-sug Lee	UV Nanoimprint Lithography Using an Elementwise Embossed Stamp.	ICMENS	2004	DBLP DOI BibTeX RDF
40	Linke Jian, Bernd Loechel, Heinz-Ulrich Scheunemann, Martin Bednarzik, Yohannes M. Desta, Jost Goettert	Fabrication of Ultra Thick, Ultra High Aspect Ratio Microcomponents by Deep and Ultra Deep X-Ray Lithography.	ICMENS	2003	DBLP DOI BibTeX RDF
40	Ruiqi Tian, Ronggang Yu, Xiaoping Tang, D. F. Wong 0001	On mask layout partitioning for electron projection lithography.	ICCAD	2002	DBLP DOI BibTeX RDF
40	Roberto Guerrieri, Karim H. Tadros, John K. Gamelin, Andrew R. Neureuther	Massively parallel algorithms for scattering in optical lithography.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
40	Yoshihiko Hirai, Sadafumi Tomida, Kazushi Ikeda, Masaru Sasago, Masayuki Endo, Sigeru Hayama, Noboru Nomura	Three-dimensional resist process simulator PEACE (photo and electron beam lithography analyzing computer engineering system).	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
36	Sani R. Nassif, Kevin J. Nowka	Physical design challenges beyond the 22nm node.	ISPD	2010	DBLP DOI BibTeX RDF	technology, scaling
36	Kristopher Pataky, Oscar Vazquez-Mena, Juergen Brugger	Nanostencil and InkJet Printing for Bionanotechnology Applications.	NanoNet	2009	DBLP DOI BibTeX RDF	Inkjet, Plasmonics, Cell Patterning, Cell Printing, Nanotechnology, Biosensor, Stencil, Tissue Engineering
36	Shayak Banerjee, Praveen Elakkumanan, Lars Liebmann, Michael Orshansky	Electrically driven optical proximity correction based on linear programming.	ICCAD	2008	DBLP DOI BibTeX RDF
36	Peng Yu, David Z. Pan	TIP-OPC: a new topological invariant paradigm for pixel based optical proximity correction.	ICCAD	2007	DBLP DOI BibTeX RDF
36	Qi Lin, Mei Ma, Tony Vo, Jenny Fan, Xin Wu, Richard Li, Xiao-Yu Li	Design-for-Manufacture for Multi Gate Oxide CMOS Process.	ISQED	2007	DBLP DOI BibTeX RDF	multi gate oxide, FPGA, layout, yield, DFM
35	Jeehong Yang, Serap A. Savari	A Lossless Circuit Layout Image Compression Algorithm for Maskless Lithography Systems.	DCC	2010	DBLP DOI BibTeX RDF	Circuit Layout Image, Maskless Lithography System, C4, Block C4, Lossless image compression
35	David Abercrombie, Fedor Pikus, Cosmin Cazan	Use of lithography simulation for the calibration of equation-based design rule checks.	DAC	2009	DBLP DOI BibTeX RDF	LFD, Leff, equation based DRC, verification, manufacturability, DFM, lithography, DRC
35	Zhenhai Zhu	A parameterized mask model for lithography simulation.	DAC	2009	DBLP DOI BibTeX RDF	mask model, parameterized model order reduction, lithography
35	Salman Gopalani, Rajesh Garg, Sunil P. Khatri, Mosong Cheng	A lithography-friendly structured ASIC design approach.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	ASIC, OPC, lithography
35	Joydeep Mitra, Peng Yu, David Zhigang Pan	RADAR: RET-aware detailed routing using fast lithography simulations.	DAC	2005	DBLP DOI BibTeX RDF	DFM, OPC, lithography, detailed routing, RET
33	Seongbo Shim, Youngsoo Shin	Mask optimization for directed self-assembly lithography: Inverse DSA and inverse lithography.	ASP-DAC	2016	DBLP DOI BibTeX RDF
33	Luis Guillermo Villanueva, Oscar Vazquez-Mena, Cristina Martin-Olmos, Veronica Savu, Katrin Sidler, Juergen Brugger	Resistless Fabrication of Nanoimprint Lithography (NIL) Stamps Using Nano-Stencil Lithography.	Micromachines	2013	DBLP DOI BibTeX RDF
33	Hongwen Sun, Jingquan Liu, Di Chen	Cell Growth Orientated in Substrate Fabricated by Holographic Lithography and Nanoimprint Lithography.	BMEI	2009	DBLP DOI BibTeX RDF
33	Jerome P. Silverman, Robert P. Rippstein, James M. Oberschmidt	X-ray lithography beamlines in the IBM Advanced Lithography Facility.	IBM J. Res. Dev.	1993	DBLP DOI BibTeX RDF
30	Yongchan Ban, Savithri Sundareswaran, David Z. Pan	Total sensitivity based dfm optimization of standard library cells.	ISPD	2010	DBLP DOI BibTeX RDF	optimization, VLSI, sensitivity, DFM, lithography
30	Alessandro Carpentiero, Manuela De Leo, Ivan Garcia Romero, Stefano Pozzi Mucelli, Freimut Reuther, Giorgio Stanta, Massimo Tormen, Paolo Ugo, Martina Zamuner	Nanoelectrochemical Immunosensors for Protein Detection.	NanoNet	2009	DBLP DOI BibTeX RDF	Nanoelectrode, electrochemical immunosensor, trastuzumab, voltammetry, electron beam lithography, proteomics
30	Stephen P. Kornachuk, Michael C. Smayling	New strategies for gridded physical design for 32nm technologies and beyond.	ISPD	2009	DBLP DOI BibTeX RDF	28nm, 32nm, 45nm, litho, rdr, placement, layout, physical design, manufacturability, lithography, standard cell, vlsi, drc, dfm
30	Kun Yuan, Jae-Seok Yang, David Z. Pan	Double patterning layout decomposition for simultaneous conflict and stitch minimization.	ISPD	2009	DBLP DOI BibTeX RDF	double patterning lithography, layout decomposition, integer linear programming
30	Jason Cong, Yi Zou	Lithographic aerial image simulation with FPGA-based hardwareacceleration.	FPGA	2008	DBLP DOI BibTeX RDF	co-processor acceleration, lithography simulation, FPGA
30	Steve Leibson, James Kim	Configurable Processors: A New Era in Chip Design.	Computer	2005	DBLP DOI BibTeX RDF	nanometer silicon lithography, microprocessors, multiprocessor systems, MPSoCs, configurable processors
30	Lars Liebmann	Layout impact of resolution enhancement techniques: impediment or opportunity?	ISPD	2003	DBLP DOI BibTeX RDF	radically restricted designs, resolution enhancement techniques, design for manufacturability, lithography
30	Anton A. Kachayev, David M. Klymyshyn, Sven Achenbach, Volker Saile	High Vertical Aspect Ratio Liga Microwave 3-DB Coupler.	ICMENS	2003	DBLP DOI BibTeX RDF	LIGA, deep X-ray lithography, high vertical aspect ratio, microwave directional coupler, coupled lines
30	Franklin M. Schellenberg, Luigi Capodieci	Impact of RET on physical layouts.	ISPD	2001	DBLP DOI BibTeX RDF	off-axis illumination, physical verification, simulation, DFM, OPC, lithography, RET, phase-shifting, PSM
30	Michael J. Flynn	What's ahead in computer design?	EUROMICRO	1997	DBLP DOI BibTeX RDF	die area improvement, very high level superscalar processors, very large cache, pin bandwidth, processor complexity, scalability, multiprocessors, logic design, instruction level parallelism, VLIW, CMOS technology, lithography, cycle time, computer design, silicon area, cache size
28	Caroline Prodhon, Demetrio Macías, Farouk Yalaoui, Alexandre Vial, Lionel Amodeo	Evolutionary Optimization for Plasmon-Assisted Lithography.	EvoWorkshops	2009	DBLP DOI BibTeX RDF
28	Nancy Ying Zhou, Rouwaida Kanj, Kanak Agarwal, Zhuo Li 0001, Rajiv V. Joshi, Sani R. Nassif, Weiping Shi	The impact of BEOL lithography effects on the SRAM cell performance and yield.	ISQED	2009	DBLP DOI BibTeX RDF
28	Kun Yuan, Katrina Lu, David Z. Pan	Double patterning lithography friendly detailed routing with redundant via consideration.	DAC	2009	DBLP DOI BibTeX RDF	double patterning, redundant via, detailed routing
28	Aswin Sreedhar, Alodeep Sanyal, Sandip Kundu	On Modeling and Testing of Lithography Related Open Faults in Nano-CMOS Circuits.	DATE	2008	DBLP DOI BibTeX RDF
28	Puneet Gupta 0001, Andrew B. Kahng, Youngmin Kim, Saumil Shah, Dennis Sylvester	Investigation of diffusion rounding for post-lithography analysis.	ASP-DAC	2008	DBLP DOI BibTeX RDF
28	Kuen-Yu Tsai, Meng-Fu You, Yi-Chang Lu, Philip C. W. Ng	A new method to improve accuracy of leakage current estimation for transistors with non-rectangular gates due to sub-wavelength lithography effects.	ICCAD	2008	DBLP DOI BibTeX RDF
28	Andrew B. Kahng, Chul-Hong Park, Xu Xu 0001, Hailong Yao	Layout decomposition for double patterning lithography.	ICCAD	2008	DBLP DOI BibTeX RDF
28	Nancy Ying Zhou, Zhuo Li 0001, Yuxin Tian, Weiping Shi, Frank Liu 0001	A New Methodology for Interconnect Parasitics Extraction Considering Photo-Lithography Effects.	ASP-DAC	2007	DBLP DOI BibTeX RDF
28	Aswin Sreedhar, Sandip Kundu	On modeling impact of sub-wavelength lithography on transistors.	ICCD	2007	DBLP DOI BibTeX RDF
28	Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki J. Murakami, Katsuya Okumura	A character size optimization technique for throughput enhancement of character projection lithography.	ISCAS	2006	DBLP DOI BibTeX RDF
28	Ke Cao, Sorin Dobre, Jiang Hu	Standard cell characterization considering lithography induced variations.	DAC	2006	DBLP DOI BibTeX RDF	process CD, CAD, OPC, design flow, standard cell, RET
28	Franck Robin, Esteban Moreno Soriano	Analysis of fitness functions for electron-beam lithography simulation and evolutionary optimization.	IEEE Trans. Evol. Comput.	2004	DBLP DOI BibTeX RDF
28	Pradiptya Ghosh, Chung-shin Kang, Michael Sanie, David Pinto 0003	New DFM Approach Abstracts AltPSM Lithography Requirements for sub-100nm IC Design Domains.	ISQED	2003	DBLP DOI BibTeX RDF
28	Kenji Harafuji, Akio Misaka, Noboru Nomura, Masahiro Kawamoto, Hirohiko Yamashita	A novel hierarchical approach for proximity effect correction in electron beam lithography.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
24	Ru Huang, HanMing Wu, Jinfeng Kang, DeYuan Xiao, XueLong Shi, Xia An, Yu Tian, Runsheng Wang, Liangliang Zhang, Xing Zhang 0002, Yangyuan Wang	Challenges of 22 nm and beyond CMOS technology.	Sci. China Ser. F Inf. Sci.	2009	DBLP DOI BibTeX RDF	22 nm technology node, device architectures, metal gate/high K dielectrics, ultra low K dielectrics, CMOS technology
24	Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera	Erect of regularity-enhanced layout on printability and circuit performance of standard cells.	ISQED	2009	DBLP DOI BibTeX RDF
24	David Z. Pan	Synergistic modeling and optimization for nanometer IC design/manufacturing integration.	SBCCI	2008	DBLP DOI BibTeX RDF	design for manufacturing
24	Minsik Cho, Yongchan Ban, David Z. Pan	Double patterning technology friendly detailed routing.	ICCAD	2008	DBLP DOI BibTeX RDF
24	Jae-Seok Yang, Andrew R. Neureuther	Crosstalk Noise Variation Assessment and Analysis for the Worst Process Corner.	ISQED	2008	DBLP DOI BibTeX RDF	worst corner, noise, crosstalk, variation, signal integrity
24	Yun Ye, Frank Liu 0001, Sani R. Nassif, Yu Cao 0001	Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness.	DAC	2008	DBLP DOI BibTeX RDF	atomistic simulations, line-edge roughness, non-rectangular gate, random dopant fluctuations, threshold variation, predictive modeling, SPICE simulation
24	Philippe Magarshack	Design challenges in 45nm and below: DFM, low-power and design for reliability.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	design for reliability, low-power design, design for manufacturability
24	Jamil Kawa, Charles C. Chiang	DFM issues for 65nm and beyond.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	DFY, DFM
24	Yokesh Kumar, Prosenjit Gupta	Reducing EPL Alignment Errors for Large VLSI Layouts.	ISQED	2007	DBLP DOI BibTeX RDF
24	Munkang Choi, Linda S. Milor	Impact on circuit performance of deterministic within-die variation in nanoscale semiconductor manufacturing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
24	Raul Camposano	Adding Manufacturability to the Quality of Results.	ISQED	2006	DBLP DOI BibTeX RDF
24	Jaidev P. Patwardhan, Vijeta Johri, Chris Dwyer, Alvin R. Lebeck	A defect tolerant self-organizing nanoscale SIMD architecture.	ASPLOS	2006	DBLP DOI BibTeX RDF	self-organizing, SIMD, data parallel, DNA, defect tolerance, nanocomputing, bit-serial
24	Wei Zhang 0012, Niraj K. Jha, Li Shang	NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture.	DAC	2006	DBLP DOI BibTeX RDF	NRAM, logic folding, run-time reconfiguration
24	André DeHon	Design of programmable interconnect for sublithographic programmable logic arrays.	FPGA	2005	DBLP DOI BibTeX RDF	Manhattan mesh, sublithographic architecture, programmable logic arrays, nanowires, programmable interconnect
24	Soo-Young Lee, Noppachai Anupongpaibool	Optimization of Distributed Implementation of Grayscale Electron-Beam Proximity Effect Correction on a Temporally Heterogeneous Cluster.	IPDPS	2005	DBLP DOI BibTeX RDF
24	André DeHon, Michael J. Wilson	Nanowire-based sublithographic programmable logic arrays.	FPGA	2004	DBLP DOI BibTeX RDF	sublithographic architecture, programmable logic arrays, nanowires
24	Alfred K. Wong	Microlithography: Trends, Challenges, Solutions, and Their Impact on Design.	IEEE Micro	2003	DBLP DOI BibTeX RDF