|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 65 occurrences of 52 keywords
|
|
|
Results
Found 308 publication records. Showing 308 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
83 | Hyun Woo Choi, Abhijit Chatterjee |
Digital bit stream jitter testing using jitter expansion. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
76 | Isaac Keslassy, Murali S. Kodialam, T. V. Lakshman, Dimitrios Stiliadis |
On guaranteed smooth scheduling for input-queued switches. |
IEEE/ACM Trans. Netw. |
2005 |
DBLP DOI BibTeX RDF |
scheduling, router, switch, jitter |
68 | T. H. Szymanski |
A Conflict-Free Low-Jitter Guaranteed-Rate MAC Protocol for Base-Station Communications in Wireless Mesh Networks. |
AccessNets |
2008 |
DBLP DOI BibTeX RDF |
low jitter, scheduling, quality of service, networks, mesh, multihop |
60 | Shalabh Goyal, Abhijit Chatterjee, Mike Atia |
Reducing Sampling Clock Jitter to Improve SNR Measurement of A/D Converters in Production Test. |
ETS |
2006 |
DBLP DOI BibTeX RDF |
|
57 | David Hay, Gabriel Scalosub |
Jitter Regulation for Multiple Streams. |
ESA |
2005 |
DBLP DOI BibTeX RDF |
|
51 | David C. Keezer, Dany Minier, Patrice Ducharme |
Method for reducing jitter in multi-gigahertz ATE. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
46 | Takashi Kawamoto, Masaru Kokubo |
A low-jitter 1.5-GHz and large-EMI reduction 10-dBm spread-spectrum clock generator for Serial-ATA. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
45 | Tony Pialis, Eric W. Hu, Khoman Phang |
A 1.8V low-jitter CMOS ring oscillator with supply regulation. |
ISCAS (3) |
2005 |
DBLP DOI BibTeX RDF |
|
43 | Daisuke Watanabe, Masakatsu Suda, Toshiyuki Okayasu |
34.1Gbps Low Jitter, Low BER High-Speed Parallel CMOS Interface for Interconnections in High-Speed Memory Test System. |
ITC |
2004 |
DBLP DOI BibTeX RDF |
|
39 | Adrian Maxim, Baker Scott, Ed Schneider, Melvin Hagge, Steve Chacko, Dan Stiurca |
Sample-reset loop filter architecture for process independent and ripple-pole-less low jitter CMOS charge-pump PLLs. |
ISCAS (4) |
2001 |
DBLP DOI BibTeX RDF |
|
36 | Zvika Brakerski, Boaz Patt-Shamir |
Jitter-approximation tradeoff for periodic scheduling. |
Wirel. Networks |
2006 |
DBLP DOI BibTeX RDF |
Jitter minimization, Perfect periodicity, Asymmetric communication, Periodic scheduling |
36 | Zvika Brakerski, Boaz Patt-Shamir |
Jitter-Approximation Tradeoff for Periodic Scheduling. |
IPDPS |
2004 |
DBLP DOI BibTeX RDF |
|
36 | Alfio Zanchi, Ioannis Papantonopoulos, Frank (Ching-Yuh) Tsay |
Measurement and SPICE prediction of sub-picosecond clock jitter in A/D converters. |
ISCAS (5) |
2003 |
DBLP DOI BibTeX RDF |
|
33 | Tingzhou Yang, Zhao Chen, Dimitrios Makrakis, Abdelhakim Hafid |
A Study of AF and EF Services Interaction. |
ICOIN |
2001 |
DBLP DOI BibTeX RDF |
|
31 | Abdelohahab Djemouai, Mohamad Sawan |
Fast-locking low-jitter integrated CMOS phase-locked loop. |
ISCAS (1) |
2001 |
DBLP DOI BibTeX RDF |
|
28 | Yu Duan, Chi-Hang Chan, Yan Zhu 0001, Rui Paulo Martins |
Supply-Noise-Desensitized Techniques for Low Jitter RO-Based PLL Achieving ≤1.6 ps RMS Jitter Within Full-Spectrum Supply Interference. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2022 |
DBLP DOI BibTeX RDF |
|
28 | Dongjun Park, Jongsun Kim |
A low-jitter 2.4 GHz all-digital MDLL with a dithering jitter reduction scheme for 256 times frequency multiplication. |
IEICE Electron. Express |
2020 |
DBLP DOI BibTeX RDF |
|
25 | Haw-Yun Shin, Jean-Lien C. Wu, Yi-Hsien Wu |
A Packet Scheduling Scheme for Broadband Wireless Networks with Heterogeneous Services. |
AINA (2) |
2004 |
DBLP DOI BibTeX RDF |
Frame-Based, Quality-of-Service, Packet Scheduling, Round-robin, Weighted-round-robin, Slot-reuse |
24 | Kazuhiko Miki, David Boerstler, Eskinder Hailu, Jieming Qi, Sarah Pettengill, Yuichi Goto |
A new test and characterization scheme for 10+ GHz low jitter wide band PLL. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Sitt Tontisirin, Reinhard Tielert |
A Gb/s one-fourth-rate CMOS CDR circuit without external reference clock. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Shun Nagata, Ewout Martens, Adam Cooman, Jan Craninckx |
A 28GHz Low Jitter, Low Power Fully Differential Self-Biased Clock Buffer with Embedded Low Pass Filter Utilizing Enable Switch in 16nm FinFET. |
MWSCAS |
2023 |
DBLP DOI BibTeX RDF |
|
23 | N. K. Anushkannan, H. Mangalam |
Design of an ultra-low power, low complexity and low jitter PLL with digitally controlled oscillator. |
Int. J. Adv. Intell. Paradigms |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Kuo-Hsing Cheng, Yu-Lung Lo |
A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs. |
DATE Designers' Forum |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Chien-Hung Kuo, Yi-Shun Shih |
A frequency synthesizer using two different delay feedbacks. |
ISCAS (3) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | S. Nagavarapu, J. Yan, Edward K. F. Lee, Randall L. Geiger |
An asynchronous data recovery/retransmission technique with foreground DLL calibration. |
ISCAS (6) |
1999 |
DBLP DOI BibTeX RDF |
|
22 | T. H. Szymanski |
Scheduling and Channel Assignment of Backhaul Traffic in Infrastructure Wireless Mesh Networks with Near-Minimal Delay and Jitter. |
ICDS |
2010 |
DBLP DOI BibTeX RDF |
backhaul, low-jitter, scheduling, quality of service, wireless mesh network, TDMA, OFDMA, crossbar, relay network, input-queue |
22 | T. H. Szymanski |
Throughput and QoS optimization in nonuniform multichannel wireless mesh networks. |
Q2SWinet |
2008 |
DBLP DOI BibTeX RDF |
low-jitter, scheduling, QoS, network, wireless, mesh, multihop |
19 | Hamed Khanmirza, Sajjad Zarifzadeh, Nasser Yazdani |
ADPQ: An Adaptive Approach for Expedited Forwarding Traffic Scheduling. |
ISCC |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Saurabh Kumar, Yatendra Kumar Singh |
A low-jitter and low-phase noise switched-loop filter PLL using fast phase-error correction and dual-edge phase comparison technique. |
Integr. |
2024 |
DBLP DOI BibTeX RDF |
|
19 | Jianguo Hu, Renfei Zou, Yao Yao, Jiajun He, Deming Wang |
A 2.4-GHz ring-VCO-based time-to-voltage conversion PLL achieving low-jitter and low-spur performance. |
Microelectron. J. |
2024 |
DBLP DOI BibTeX RDF |
|
19 | Simone Mattia Dartizio, Francesco Tesolin, Giacomo Castoro, Francesco Buccoleri, Michele Rossoni, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino |
A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering. |
IEEE J. Solid State Circuits |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Suneui Park, Seojin Choi, Seyeon Yoo, Yoonseo Cho, Jaehyouk Choi |
An Ultra-Low Jitter, Low-Power, 102-GHz PLL Using a Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector. |
IEEE J. Solid State Circuits |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Chanwoong Hwang, Hangi Park, Yongsun Lee, Taeho Seong, Jaehyouk Choi |
A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC's Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping ΔΣM. |
IEEE J. Solid State Circuits |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Younghyun Lim, Juyeop Kim, Yongwoo Jo, Jooeun Bang, Jaehyouk Choi |
A Wide-Lock-In-Range and Low-Jitter 12-14.5 GHz SSPLL Using a Low-Power Frequency-Disturbance-Detecting and Correcting Loop. |
IEEE J. Solid State Circuits |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Jiang Gong, Edoardo Charbon, Fabio Sebastiano, Masoud Babaie |
A Low-Jitter and Low-Spur Charge-Sampling PLL. |
IEEE J. Solid State Circuits |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Mohammad Bagheri, Xun Li |
An ultra-low power and low jitter frequency synthesizer for 5G wireless communication and IoE applications. |
Int. J. Circuit Theory Appl. |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Seyeon Yoo, Seojin Choi, Yongsun Lee, Taeho Seong, Younghyun Lim, Jaehyouk Choi |
A Low-Jitter and Low-Reference-Spur Ring-VCO- Based Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator. |
IEEE J. Solid State Circuits |
2021 |
DBLP DOI BibTeX RDF |
|
19 | Charalampos Stylianopoulos, Magnus Almgren, Olaf Landsiedel, Marina Papatriantafilou, Trevor Neish, Linus Gillander, Bengt Johansson, Staffan Bonnier |
On the performance of commodity hardware for low latency and low jitter packet processing. |
DEBS |
2020 |
DBLP DOI BibTeX RDF |
|
19 | Mario Mercandelli |
Techniques for low-jitter and low-area occupation fractional-N Frequency synthesis. |
|
2020 |
RDF |
|
19 | Yongping Fan, Bo Xiang, Dan Zhang, James S. Ayers, Kuan-Yueh James Shen, Andrey Mezhiba |
Digital Leakage Compensation for a Low-Power and Low-Jitter 0.5-to-5GHz PLL in 10nm FinFET CMOS Technology. |
ISSCC |
2019 |
DBLP DOI BibTeX RDF |
|
19 | Xiang Gao |
Low Jitter and Low Power PLL:Towards The Utopia. |
ISOCC |
2019 |
DBLP DOI BibTeX RDF |
|
19 | Yongsun Lee, Taeho Seong, Seyeon Yoo, Jaehyouk Choi |
A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop Filter PLL Using a Fast Phase-Error Correction Technique. |
IEEE J. Solid State Circuits |
2018 |
DBLP DOI BibTeX RDF |
|
19 | Motahhareh Estebsari, Mohammad Gholami, Mohammad Javad Ghahramanpour |
A wide range delay locked loop for low power and low jitter applications. |
Int. J. Circuit Theory Appl. |
2018 |
DBLP DOI BibTeX RDF |
|
19 | Faeze Noruzpur, Sina Mahdavi, Maryam Poreh, Shima Tayyeb Ghasemi |
A New Semi-Digital Low Power Low Jitter and Fast PLL in 0.18μm Technology. |
MIXDES |
2018 |
DBLP DOI BibTeX RDF |
|
19 | Ahmed Musa, Wei Deng 0001, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa |
A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration. |
IEEE J. Solid State Circuits |
2014 |
DBLP DOI BibTeX RDF |
|
19 | Roberto Nonis, Werner Grollitsch, Thomas Santa, Dmytro Cherniak, Nicola Da Dalt |
digPLL-Lite: A Low-Complexity, Low-Jitter Fractional-N Digital PLL Architecture. |
IEEE J. Solid State Circuits |
2013 |
DBLP DOI BibTeX RDF |
|
19 | Davide Tasca |
Low-power low-jitter fractional-N frequency synthesizer using bang bang phase detection. |
|
2012 |
RDF |
|
19 | Yingmei Chen, Zhigong Wang, Li Zhang |
A low-jitter low-power monolithically integrated optical receiver for SDH STM-16. |
Sci. China Inf. Sci. |
2011 |
DBLP DOI BibTeX RDF |
|
19 | Ulrich L. Rohde, Ajay K. Poddar |
Digital frequency synthesizer using adaptive mode-coupled resonator mechanism for low phase noise and low jitter applications. |
ISCAS |
2011 |
DBLP DOI BibTeX RDF |
|
19 | Fu Luo, Godi Fischer |
Low jitter audio range PLL with ultra low power dissipation. |
ACM Great Lakes Symposium on VLSI |
2011 |
DBLP DOI BibTeX RDF |
|
19 | David E. Duarte, Suching Hsu, Keng L. Wong, Mingwei Huang, Greg Taylor |
Interpolated VCO design for a low bandwidth, low-jitter, self-biased PLL in 45 nm CMOS. |
CICC |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Régis Roubadia, Sami Ajram, Guy Cathébras |
Low Power and Low Jitter Wideband Clock Synthesizers in CMOS ASICs. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Amr M. Fahim |
A compact, low-power low-jitter digital PLL. |
ESSCIRC |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Ramin Farjad-Rad, William J. Dally, Hiok-Tiaq Ng, Ramesh Senthinathan, Ming-Ju Edward Lee, Rohit Rathi, John Poulton |
A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips. |
IEEE J. Solid State Circuits |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Kuo-Hsing Chen, Huan-Sen Liao, Lin-Jiunn Tzou |
A low-jitter and low-power phase-locked loop design. |
ISCAS |
2000 |
DBLP DOI BibTeX RDF |
|
17 | Jun Zhao 0002, Yong-Bin Kim |
A low power 32 nanometer CMOS digitally controlled oscillator. |
SoCC |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Jaehong Ko, Wookwan Lee, Soo-Won Kim |
2.5GHz PLL with current matching charge-pump for 10Gbps transmitter design. |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP DOI BibTeX RDF |
jitter, PLL, output buffer, charge-pump |
17 | Wen-Chi Wu, Chih-Chien Huang, Chih-Hsiung Chang, Nai-Heng Tseng |
Low-power CMOS PLL for clock generator. |
ISCAS (1) |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Juyeop Kim, Yongwoo Jo, Hangi Park, Taeho Seong, Younghyun Lim, Jaehyouk Choi |
A 12.8-15.0-GHz Low-Jitter Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation. |
IEEE J. Solid State Circuits |
2024 |
DBLP DOI BibTeX RDF |
|
16 | Min-Ji Kim, Won-Young Lee |
Design of a Low-Jitter Digitally Controlled Oscillator With Supply Noise Compensation. |
ICEIC |
2024 |
DBLP DOI BibTeX RDF |
|
16 | Seheon Jang, Munjae Chae, Hangi Park, Chanwoong Hwang, Jaehyouk Choi |
10.2 A 5.5μs-Calibration-Time, Low-Jitter, and Compact-Area Fractional-N Digital PLL Using the Recursive-Least-Squares (RLS) Algorithm. |
ISSCC |
2024 |
DBLP DOI BibTeX RDF |
|
16 | Xiangyu Meng 0003, Wang Xie, Jiaqi Zhang, Zhao Zhang 0004 |
A 0.2-7.1-Gb/s Low-Jitter Full-Rate Reference-Less CDR for Communication Signal Analyzers. |
IEEE Trans. Instrum. Meas. |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Dengyu Ran, Xiao Chen, Lei Song |
Agile: A high-scalable and low-jitter flow tables lifecycle management framework for multi-core programmable data plane. |
Comput. Commun. |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Zhen Li 0037, Zhenrong Li, Xudong Wang, Zeyuan Wang, Yiqi Zhuang |
A low jitter sub-sampling phase-locked loop with sampling thermal noise cancellation technique. |
Int. J. Circuit Theory Appl. |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Jin Wu, Minwei Hu, Xudong Wu, Yang Zuo, Chenggong Wan, Lixia Zheng, Weifeng Sun |
A low jitter fractional PLL with offset current charge pump. |
Microelectron. J. |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Shaorong Lu, Sheng Xie, Luhong Mao, Ruiliang Song, Naibo Zhang |
A low jitter 50 Gb/s PAM4 optical receiver in 130 nm SiGe BiCMOS. |
Microelectron. J. |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Qing Liu, Heming Wang, Fangxu Lv, Geng Zhang 0001, Dongbin Lv |
Low-Jitter Retimer Circuits for High-Performance Computer Optical Communications. |
ICCEIC |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Tianshu Xu, Wen Gu, Koichi Ota, Shinobu Hasegawa |
A Low-Jitter Hand Tracking System for Improving Typing Efficiency in Virtual Reality Workspace. |
TENCON |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Andreas Depold, Christian Dorn, Robert Weigel, Fabian Lurz |
A Simple Low Jitter Wireless Triggering and Unidirectional Communication System. |
WiSNeT |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Hsi-Hao Huang, Chun-Hsien Liu, Tzu-Yun Huang, Sheng-Di Lin, Chen-Yi Lee |
Self-Restoring and Low-Jitter Circuits for High Timing-Resolution SPAD Sensing Applications. |
ISCAS |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Jin Sun, Jiahao Hu, Ziqi Song, Qing Li, Dian He, Hujun Jia |
A Low Jitter Current-Mode Multiplying Delay-Locked Loop Applied to High-Precision TDC. |
ASICON |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Simone Mattia Dartizio |
Design of small-footprint, high-spectral purity and low-jitter digitally-intensive frequency synthetizers |
|
2023 |
RDF |
|
16 | Hyojun Kim, Woosong Jung, Kwandong Kim, Sungwoo Kim, Woo-Seok Choi, Deog-Kyoon Jeong |
A Low-Jitter 8-GHz RO-Based ADPLL With PVT-Robust Replica-Based Analog Closed Loop for Supply Noise Compensation. |
IEEE J. Solid State Circuits |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Hangi Park, Chanwoong Hwang, Taeho Seong, Jaehyouk Choi |
A Low-Jitter Ring-DCO-Based Fractional-N Digital PLL With a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector. |
IEEE J. Solid State Circuits |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Woorham Bae |
Benchmark Figure of Merit Extensions for Low Jitter Phase Locked Loops Inspired by New PLL Architectures. |
IEEE Access |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Yuan Cheng Qian, Yen-Yu Chao, Shen-Iuan Liu |
A Low-Jitter Sub-Sampling PLL With a Sub-Sampling DLL. |
IEEE Trans. Circuits Syst. II Express Briefs |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Shuxiang Song, Zefa Liu, Mingcan Cen, Chaobo Cai |
A 9.8-12.5 Gb/s Low-Jitter Reference-Less Clock and Data Recovery Circuit. |
J. Circuits Syst. Comput. |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal |
A low jitter and fast locking all digital phase locked loop with flash based time to digital converter and gain calibrated voltage controlled oscillator. |
Int. J. Circuit Theory Appl. |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Tianxiang Wu, Xi Wang, Yong Chen 0005, Junyan Ren, Shunli Ma |
A 10-MHz to 50-GHz low-jitter multiphase clock generator for high-speed oscilloscope in 0.15-μm GaAs technology. |
Int. J. Circuit Theory Appl. |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Jiyun Tong, Sha Wang, Shuang Zhang, Mengdi Zhang, Ye Zhao, Fazhan Zhao |
A Low-Jitter Harmonic-Free All-Digital Delay-Locked Loop for Multi-Channel Vernier TDC. |
Sensors |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Chengxian Pan, Chunqi Shi, Guoliang Zhao, Boxiao Liu, Leilei Huang, Runxi Zhang |
A 21.3-24.5Gb/s low jitter PLL-based clock and data recovery circuit with cascode-coupled quadrature LC-VCO. |
IEICE Electron. Express |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Sheng Xie, Chengkui Jia, Luhong Mao, Gaolei Zhou, Naibo Zhang, Ruiliang Song |
Low jitter design for quarter-rate CDR of 100Gb/s PAM4 optical receiver. |
IEICE Electron. Express |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Jiahao Hu, Zhongxian Huang, Baoxing Duan, Qing Li, Ziqi Song, Dian He |
A Multiplying Delay-Locked Loop design with low jitter and high linearity. |
ICTA |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Wanghua Wu, Chih-Wei Yao, Chengkai Guo, Pei-Yuan Chiang, Lei Chen, Pak-Kim Lau, Zhanjun Bai, Sang Won Son, Thomas Byunghak Cho |
A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO. |
IEEE J. Solid State Circuits |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Shahram Modanlou, Gholamreza Ardeshir, Mohammad Gholami |
Analysis and design of a low jitter delay-locked loop using lock state detector. |
Int. J. Circuit Theory Appl. |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Chia-Chen Chang, Yu-Tung Chin, Hossameldin A. Ibrahim, Kang-Yu Chang, Shyh-Jye Jou |
A Low-Jitter ADPLL with Adaptive High-Order Loop Filter and Fine Grain Varactor Based DCO. |
ISCAS |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Woorham Bae |
State-of-the-Art Circuit Techniques for Low-Jitter Phase-Locked Loops: Advanced Performance Benchmark FOM Based on an Extensive Survey. |
ISCAS |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Junghoon Jin, Seungjun Kim, Sunguk Choi, Pil-Ho Lee, Sang-jae Rhee, Ki-hwan Choi, Jongsun Kim |
A 7.68 GHz Fast-Lock Low-Jitter Digital MDLL. |
ISOCC |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Souradip Sen, Utkarsh Upadhyaya, Krishna Reddy Kondreddy, Arun Goyal, Sandeep Goyal, Shalabh Gupta |
A Low Jitter Digital Loop CDR Based 8-16 Gbps SerDes in 65 nm CMOS Technology. |
VLSID |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Sarang Kazeminia, Arefeh Soltani |
A low-jitter leakage-free digitally calibrated phase locked loop. |
Comput. Electr. Eng. |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal |
A Wide Frequency Range Low Jitter Integer PLL with Switch and Inverter Based CP in 0.18 μm CMOS Technology. |
J. Circuits Syst. Comput. |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Jin Wu, Shuang Chen, Kang Hu, Lixia Zheng, Weifeng Sun |
A low jitter multiplying delay-locked loop with static phase offset elimination applied to time-to-digital converter. |
Microelectron. J. |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Youngbog Yoon, Hyunsu Park, Chulwoo Kim |
A DLL-Based Quadrature Clock Generator With a 3-Stage Quad Delay Unit Using the Sub-Range Phase Interpolator for Low-Jitter and High-Phase Accuracy DRAM Applications. |
IEEE Trans. Circuits Syst. |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Wei Zou, Daming Ren, Xuecheng Zou |
A wideband low-jitter PLL with an optimized Ring-VCO. |
IEICE Electron. Express |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Pierre Bisiaux, Elena Blokhina, Eugene Koskin, Teerachot Siriburanon, Dimitri Galayko |
Design of a 1.5 GHz Low jitter DCO Ring in 28 nm CMOS Process. |
ECCTD |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Zeeshan Ali, Makwana Harshit R, Shalabh Gupta |
A Low Jitter Double-Tailed Strong-Arm Latch Based Digital-to-Time Converter (DTC). |
ICECS |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Mengshuai Wang, Yingmei Chen, Jinlei Yuan |
A low jitter 50Gb/s PAM4 CDR of Receiver in 40nm CMOS Technology. |
WCSP |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Juyeop Kim, Younghyun Lim, Heein Yoon, Yongsun Lee, Hangi Park, Yoonseo Cho, Taeho Seong, Jaehyouk Choi |
An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators. |
IEEE J. Solid State Circuits |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Heein Yoon, Suneui Park, Jaehyouk Choi |
A Low-Jitter Injection-Locked Multi-Frequency Generator Using Digitally Controlled Oscillators and Time-Interleaved Calibration. |
IEEE J. Solid State Circuits |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Seojin Choi, Seyeon Yoo, Yongsun Lee, Yongwoo Jo, Jeonghyun Lee, Younghyun Lim, Jaehyouk Choi |
An Ultra-Low-Jitter 22.8-GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier With a Multiplication Factor of 114. |
IEEE J. Solid State Circuits |
2019 |
DBLP DOI BibTeX RDF |
|
Displaying result #1 - #100 of 308 (100 per page; Change: ) Pages: [ 1][ 2][ 3][ 4][ >>] |
|