Search results for "low-swing"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
65	Fei Qiao, Huazhong Yang, Gang Huang, Hui Wang 0004	Implementation of low-swing differential interface circuits for high-speed on-chip asynchronous interconnection.	Sci. China Ser. F Inf. Sci.	2008	DBLP DOI BibTeX RDF	low-swing interface, differential signaling, tapered-buffer, interconnect, asynchronous circuit, low power circuit
65	José C. García 0001, Juan A. Montiel-Nelson, Saeid Nooshabadi	Adaptive Low/High Voltage Swing CMOS Driver for On-Chip Interconnects.	ISCAS	2007	DBLP DOI BibTeX RDF
65	Rohini Krishnan, José Pineda de Gyvez, Harry J. M. Veendrick	Encoded-Low Swing Technique for Ultra Low Power Interconnect.	FPL	2003	DBLP DOI BibTeX RDF
65	Zhiyu Liu, Volkan Kursun	High Speed Low Swing Dynamic Circuits with Multiple Supply and Threshold Voltages.	ISVLSI	2006	DBLP DOI BibTeX RDF
63	Davide Bertozzi, Luca Benini, Bruno Riccò	Parametric timing and power macromodels for high level simulation of low-swing interconnects.	ISLPED	2002	DBLP DOI BibTeX RDF	delay, interconnect, power, macromodel, low-swing
60	Volkan Kursun, Eby G. Friedman	Low swing dual threshold voltage domino logic.	ACM Great Lakes Symposium on VLSI	2002	DBLP DOI BibTeX RDF
58	Volkan Kursun, Siva G. Narendra, Vivek De, Eby G. Friedman	Monolithic DC-DC Converter Analysis And Mosfet Gate Voltage Optimization.	ISQED	2003	DBLP DOI BibTeX RDF
57	Shuming Chen, Xiangyuan Liu	A Low-Latency and Low-Power Hybrid Insertion Methodology for Global Interconnects in VDSM Designs.	NOCS	2007	DBLP DOI BibTeX RDF	differential-signaling, insertion methodology, on-chip interconnects, low-swing
54	Xiangyuan Liu, Shuming Chen	Delay and Power Estimation Models of Low-Swing Interconnects for Design Planning.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	low-swing interconnect, delay, power, estimation model
52	Abdoul Rjoub, M. Alrousan, Omar M. Al-Jarrah, Odysseas G. Koufopavlou	Multi-level low swing voltage values for low power design applications.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
48	Kwang-Il Oh, Seunghyun Cho, Lee-Sup Kim	A low power SoC bus with low-leakage and low-swing technique.	ISCAS	2006	DBLP DOI BibTeX RDF
48	Zhiyu Liu, Volkan Kursun	Robust Dynamic Node Low Voltage Swing Domino Logic with Multiple Threshold Voltages.	ISQED	2006	DBLP DOI BibTeX RDF	Low Voltage Swing, Gate Oxide Leakage, Domino Logic, Subthreshold Leakage, Dual Threshold Voltage
47	Ashok Narasimhan, Manish Kasotiya, Ramalingam Sridhar	A Low-Swing Differential Signaling Scheme for On-Chip Global Interconnects.	VLSI Design	2005	DBLP DOI BibTeX RDF
43	Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang	Low-swing clock domino logic incorporating dual supply and dual threshold voltages.	DAC	2002	DBLP DOI BibTeX RDF	low swing clock, low power, domino logic, dual supply voltage, dual threshold voltage
39	Davide Bertozzi, Luca Benini, Bruno Riccò	Energy-efficient and reliable low-swing signaling for on-chip buses based on redundant coding.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
38	Hui Zhang 0008, George Varghese, Jan M. Rabaey	Low-swing on-chip signaling techniques: effectiveness and robustness.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
37	Jae-Joon Kim, Kaushik Roy 0001	A Leakage-Tolerant Low-Swing Circuit Style in Partially Depleted Silicon-on-Insulator CMOS Technologies.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
32	Ling Zhang, Jianhua Liu, Haikun Zhu, Chung-Kuan Cheng, Masanori Hashimoto	High performance current-mode differential logic.	ASP-DAC	2008	DBLP DOI BibTeX RDF
32	Rohini Krishnan, José Pineda de Gyvez, Martijn T. Bennebroek	Low energy FPGA interconnect design.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	FPGA, low power, interconnect, encoding
31	Tiago Borges, Ernesto Ventura Martins, Luis Nero Alves	Understanding large swing and low swing operation in DyCML gates.	ICECS	2012	DBLP DOI BibTeX RDF
31	Giacomo Paci, Davide Bertozzi, Luca Benini	Variability compensation for full-swing against low-swing on-chip communication.	IET Comput. Digit. Tech.	2011	DBLP DOI BibTeX RDF
31	Giacomo Paci, Davide Bertozzi, Luca Benini	Effectiveness of adaptive supply voltage and body bias as post-silicon variability compensation techniques for full-swing and low-swing on-chip communication channels.	DATE	2009	DBLP DOI BibTeX RDF
31	Tushar Krishna, Amit Kumar 0002, Patrick Chiang 0001, Mattan Erez, Li-Shiuan Peh	NoC with Near-Ideal Express Virtual Channels Using Global-Line Communication.	Hot Interconnects	2008	DBLP DOI BibTeX RDF	Hybrid interconnects, Networks-on-chip, Packet-switching
30	Ashok Narasimhan, Bhooma Srinivasaraghavan, Ramalingam Sridhar	A Low-Power Asymmetric Source Driver Level Converter Based Current-Mode Signaling Scheme for Global Interconnects.	VLSI Design	2006	DBLP DOI BibTeX RDF
30	Abdoul Rjoub, Odysseas G. Koufopavlou	Low voltage swing gates for low power consumption.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
29	Woopyo Jeong, Bipul Chandra Paul, Kaushik Roy 0001	Adaptive supply voltage technique for low swing interconnects.	ASP-DAC	2004	DBLP DOI BibTeX RDF
26	Nuno Dias, Marcelino B. Santos, Floriberto A. Lima, Beatriz Vieira Borges, Júlio Paisana	Monolithic Multi-mode DC-DC Converter with Gate Voltage Optimization.	PATMOS	2008	DBLP DOI BibTeX RDF	DC-DC power conversion, light-load efficiency, Step-Down, Buck, low swing
26	Srinivasa R. Sridhara, Naresh R. Shanbhag	Coding for system-on-chip networks: a unified framework.	DAC	2004	DBLP DOI BibTeX RDF	bus coding, crosstalk avoidance, low-power, error-correcting codes, low-swing
26	George Varghese, Hui Zhang 0008, Jan M. Rabaey	The design of a low energy FPGA.	ISLPED	1999	DBLP DOI BibTeX RDF	low swing signalling, FPGA, low power
26	Eric Kusse, Jan M. Rabaey	Low-energy embedded FPGA structures.	ISLPED	1998	DBLP DOI BibTeX RDF	dual voltage, pass-transistors, FPGAs, interconnect network, embedded, power, low energy, low swing
24	Sumeer Goel, Ashok Kumar 0001, Magdy A. Bayoumi	Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
24	Rohini Krishnan, José Pineda de Gyvez, Martijn T. Bennebroek	Low energy FPGA interconnect design.	FPGA	2004	DBLP DOI BibTeX RDF
22	Bahman Kheradmand Boroujeni, Fatemeh Aezinia, Ali Afzali-Kusha	High performance circuit techniques for dynamic OR gates.	ISCAS	2006	DBLP DOI BibTeX RDF
21	Jaydeep P. Kulkarni, Andres Malavasi, Charles Augustine, Carlos Tokunaga, Jim Tschanz, Muhammad M. Khellah, Vivek De	Low Swing and Column Multiplexed Bitline Techniques for Low-Vmin, Noise-Tolerant, High-Density, 1R1W 8T-Bitcell SRAM in 10nm FinFET CMOS.	VLSI Circuits	2020	DBLP DOI BibTeX RDF
21	Ragh Kuttappa, Scott Lerner, Leo Filippini, Baris Taskin	Low Swing - Low Frequency Rotary Traveling Wave Oscillators.	ISCAS	2019	DBLP DOI BibTeX RDF
21	Hossein Rezaei, Soodeh Aghli Moghaddam, Abdolreza Rahmati	High-speed low-power on-chip global interconnects using low-swing self-timed regenerators.	Microelectron. J.	2016	DBLP DOI BibTeX RDF
21	Prashant Upadhyay, Rajib Kar, Durbadal Mandal, Sakti Prasad Ghoshal	A design of low swing and multi threshold voltage based low power 12T SRAM cell.	Comput. Electr. Eng.	2015	DBLP DOI BibTeX RDF
21	Do-Gyoon Song, Jaeha Kim	A low-power high-radix switch fabric based on low-swing signaling and partially-activated input lines.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
21	Byung-Do Yang, Yong-Kyu Lee, Si-Woo Sung, Jae-Joong Min, Jae-Mun Oh, Hyeong-Ju Kang	A Low Power Content Addressable Memory Using Low Swing Search Lines.	IEEE Trans. Circuits Syst. I Regul. Pap.	2011	DBLP DOI BibTeX RDF
21	Chia-Hsin Owen Chen, Sunghyun Park 0002, Tushar Krishna, Li-Shiuan Peh	A low-swing crossbar and link generator for low-power networks-on-chip.	ICCAD	2011	DBLP DOI BibTeX RDF
21	Jose Carlos Garcia-Montesdeoca, Juan A. Montiel-Nelson, Saeid Nooshabadi	CMOS Driver-Receiver Pair for Low-Swing Signaling for Low Energy On-Chip Interconnects.	IEEE Trans. Very Large Scale Integr. Syst.	2009	DBLP DOI BibTeX RDF
21	Abdoul Rjoub, Odysseas G. Koufopavlou	Multithreshold voltage low-swing/low-voltage techniques in logic gates.	Integr.	2004	DBLP DOI BibTeX RDF
21	Abdoul Rjoub, M. Alrousan, Omar M. Al-Jarrah, Odysseas G. Koufopavlou	An Efficient Low-Swing Multithreshold-Voltage Low-Power Design Technique.	J. Circuits Syst. Comput.	2004	DBLP DOI BibTeX RDF
21	Abdoul Rjoub, Odysseas G. Koufopavlou	Efficient Low Power/Low Swing Bus Design Architectures.	VLSI Design	2001	DBLP DOI BibTeX RDF
21	Abdoul Rjoub, Odysseas G. Koufopavlou	Low-swing/low power driver architecture.	ICECS	1999	DBLP DOI BibTeX RDF
21	Abdoul Rjoub, Odysseas G. Koufopavlou	Low-power domino logic multiplier using low-swing technique.	ICECS	1998	DBLP DOI BibTeX RDF
21	Srinivasa R. Sridhara, Naresh R. Shanbhag	Coding for Reliable On-Chip Buses: A Class of Fundamental Bounds and Practical Codes.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
21	Yijun Liu, Pinghua Chen, Wenyan Wang, Zhenkun Li	The Design and Implementation of a Power Efficient Embedded SRAM.	PATMOS	2007	DBLP DOI BibTeX RDF
21	Maurice Meijer, Rohini Krishnan, Martijn T. Bennebroek	Energy-efficient FPGA interconnect design.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
21	Pong-Fei Lu, Nianzheng Cao, Leon J. Sigal, Pieter Woltgens, Raphael Robertazzi, David F. Heidel	A pulsed low-voltage swing latch for reduced power dissipation in high-frequency microprocessors.	ISLPED	2006	DBLP DOI BibTeX RDF	pulse latch, low-power, latch
21	Houman Zarrabi, Haydar Saaied, Asim J. Al-Khalili, Yvon Savaria	Zero skew differential clock distribution network.	ISCAS	2006	DBLP DOI BibTeX RDF
21	Deepak C. Sekar	Clock trees: differential or single ended?.	ISQED	2005	DBLP DOI BibTeX RDF
21	Srinivasa R. Sridhara, Naresh R. Shanbhag	Coding for Reliable On-Chip Buses: Fundamental Limits and Practical Codes.	VLSI Design	2005	DBLP DOI BibTeX RDF
21	Paolo Ienne, Patrick Thiran, Giovanni De Micheli, Frederic Worm	An Adaptive Low-Power Transmission Scheme for On-Chip Networks.	ISSS	2002	DBLP DOI BibTeX RDF	low-power, systems-on-chip, networks-on-chip
19	Atul Maheshwari, Wayne P. Burleson	Differential current-sensing for on-chip interconnects.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
19	Panduka Wijetunga	High-performance crossbar design for system-on-chip.	IWSOC	2003	DBLP DOI BibTeX RDF
17	Muhammad Waqas Chaudhary, Andy Heinig, Bhaskar Choubey	Interconnect Aware Power Optimization of Low Swing Driver for Multi-Chip Interfaces.	ICECS	2020	DBLP DOI BibTeX RDF
17	Ragh Kuttappa, Baris Taskin	FinFET - Based Low Swing Rotary Traveling Wave Oscillators.	ISCAS	2020	DBLP DOI BibTeX RDF
17	Viveka Konandur Rajanna, Massimo Alioto	Low-Swing Links with Dynamic Energy-Quality Trade-off for Error-Resilient Applications.	CICC	2019	DBLP DOI BibTeX RDF
17	José C. García 0001, Juan A. Montiel-Nelson, Saeid Nooshabadi	Low Swing Charge Recycling Driver for On-Chip Interconnect.	J. Low Power Electron.	2018	DBLP DOI BibTeX RDF
17	Eleni Maragkoudaki, Przemyslaw Mroszczyk, Vasilis F. Pavlidis	Energy Efficiency of Low Swing Signaling for Emerging Interposer Technologies.	NANOARCH	2018	DBLP DOI BibTeX RDF
17	Przemyslaw Mroszczyk, Vasilis F. Pavlidis	Ultra-low swing CMOS transceiver for 2.5-D integrated systems.	ISQED	2018	DBLP DOI BibTeX RDF
17	Naveen Kadayinti, Maryam Shojaei Baghini, Dinesh Kumar Sharma	A Clock Retiming Circuit for Repeaterless Low Swing On-Chip Interconnects.	VLSID	2017	DBLP DOI BibTeX RDF
17	Jianfei Jiang 0001, Zhigang Mao, Weiguang Sheng, Qin Wang 0009, Weifeng He	Delay Analysis and Design Optimization for Low-Swing RC-Limited Global Interconnects.	J. Circuits Syst. Comput.	2016	DBLP DOI BibTeX RDF
17	Naveen Kadayinti, Amitalok J. Budkuley, Dinesh Kumar Sharma	Settling Time of Mesochronous Clock Retiming Circuits for Low Swing Interconnects.	CoRR	2016	DBLP BibTeX RDF
17	Sayeh Sharifymoghaddam, Ali Sheikholeslami	Low-Swing Signaling for FPGA Power Reduction (Abstract Only).	FPGA	2016	DBLP DOI BibTeX RDF
17	K. Naveen, Dinesh Kumar Sharma	Testable design of repeaterless low swing on-chip interconnect.	DATE	2016	DBLP BibTeX RDF
17	Can Sitik, Emre Salman, Leo Filippini, Sung-Jun Yoon, Baris Taskin	FinFET-Based Low-Swing Clocking.	ACM J. Emerg. Technol. Comput. Syst.	2015	DBLP DOI BibTeX RDF
17	Naveen Kadayinti, Dinesh Kumar Sharma	Testable Design of Repeaterless Low Swing On-Chip Interconnect.	CoRR	2015	DBLP BibTeX RDF
17	Naveen Kadayinti, Maryam Shojaei Baghini, Dinesh Kumar Sharma	A Clock Synchronizer for Repeaterless Low Swing On-Chip Links.	CoRR	2015	DBLP BibTeX RDF
17	He Qi, Oluseyi A. Ayorinde, Yu Huang 0015, Benton H. Calhoun	Optimizing energy efficient low-swing interconnect for sub-threshold FPGAs.	FPL	2015	DBLP DOI BibTeX RDF
17	Somnath Kundu, Bongjin Kim, Chris H. Kim	Two-step beat frequency quantizer based ADC with adaptive reference control for low swing bio-potential signals.	CICC	2015	DBLP DOI BibTeX RDF
17	Shiwei Fang, Emre Salman	Low swing TSV signaling using novel level shifters with single supply voltage.	ISCAS	2015	DBLP DOI BibTeX RDF
17	Mallika Rathore, Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin	A Novel Static D-Flip-Flop Topology for Low Swing Clocking.	ACM Great Lakes Symposium on VLSI	2015	DBLP DOI BibTeX RDF
17	Mu-Shan Lin, Chien-Chun Tsai, Chih-Hsien Chang, Wen-Hung Huang, Ying-Yu Hsu, Shu-Chun Yang, Chin-Ming Fu, Mao-Hsuan Chou, Tien-Chien Huang, Ching-Fang Chen, Tze-Chiang Huang, Saman Adham, Min-Jer Wang, William Wu Shen, Ashok Mehta	A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application.	IEEE J. Solid State Circuits	2014	DBLP DOI BibTeX RDF
17	Can Sitik, Baris Taskin	Iterative skew minimization for low swing clocks.	Integr.	2014	DBLP DOI BibTeX RDF
17	Seok Kim, Youngkyun Jeong, Mira Lee, Kee-Won Kwon, Jung-Hoon Chun	A 5.2-Gb/s Low-Swing Voltage-Mode Transmitter With an AC-/DC-Coupled Equalizer and a Voltage Offset Generator.	IEEE Trans. Circuits Syst. I Regul. Pap.	2014	DBLP DOI BibTeX RDF
17	Can Sitik, Leo Filippini, Emre Salman, Baris Taskin	High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design.	ISVLSI	2014	DBLP DOI BibTeX RDF
17	Chao-Kuei Chung, Chien-Yu Lu, Zhi-Hao Chang, Shyh-Jye Jou, Ching-Te Chuang, Ming-Hsien Tu, Yu-Hsian Chen, Yong-Jyun Hu, Paul-Sen Kan, Huan-Shun Huang, Kuen-Di Lee, Yung-Shin Kao	A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip-tracking and negative source-line write-assists.	SoCC	2014	DBLP DOI BibTeX RDF
17	Sunghyun Park 0002, Masood Qazi, Li-Shiuan Peh, Anantha P. Chandrakasan	40.4fJ/bit/mm low-swing on-chip signaling with self-resetting logic repeaters embedded within a mesh NoC in 45nm SOI CMOS.	DATE	2013	DBLP DOI BibTeX RDF
17	Can Sitik, Baris Taskin	Skew-bounded low swing clock tree optimization.	ACM Great Lakes Symposium on VLSI	2013	DBLP DOI BibTeX RDF
17	Seyed Ebrahim Esmaeili, Asim J. Al-Khalili, Glenn E. R. Cowan	Low-Swing Differential Conditional Capturing Flip-Flop for LC Resonant Clock Distribution Networks.	IEEE Trans. Very Large Scale Integr. Syst.	2012	DBLP DOI BibTeX RDF
17	Vijaya Sankara Rao Pasupureddi, Pradip Mandal	Active-terminated transmitter and receiver circuits for high-speed low-swing duobinary signaling.	Int. J. Circuit Theory Appl.	2012	DBLP DOI BibTeX RDF
17	Nor Muzlifah Mahyuddin, Gordon Russell 0002, E. Graeme Chester	Design and analysis of a low-swing driver scheme for long interconnects.	Microelectron. J.	2011	DBLP DOI BibTeX RDF
17	Fengfeng Wu, Song Jia, Yuan Wang 0001, Ganggang Zhang	Low swing drivers based on charge redistribution.	Sci. China Inf. Sci.	2010	DBLP DOI BibTeX RDF
17	Chia-Hsin Owen Chen, Niket Agarwal, Tushar Krishna, Kyung-Hoae Koo, Li-Shiuan Peh, Krishna Saraswat	Physical vs. Virtual Express Topologies with Low-Swing Links for Future Many-Core NoCs.	NOCS	2010	DBLP DOI BibTeX RDF
17	Yiannis Moisiadis, Yiorgos Tsiatouhas	A Receiver Circuit for Low-Swing Interconnect Schemes.	ISVLSI	2010	DBLP DOI BibTeX RDF
17	Joseph F. Ryan 0002, Benton H. Calhoun	A sub-threshold FPGA with low-swing dual-VDD interconnect in 90nm CMOS.	CICC	2010	DBLP DOI BibTeX RDF
17	Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian	Non-uniform power access in large caches with low-swing wires.	HiPC	2009	DBLP DOI BibTeX RDF
17	José C. García 0001, Juan A. Montiel-Nelson, Saeid Nooshabadi	Efficient CMOS driver-receiver pair with low-swing signaling for on-chip interconnects.	ECCTD	2007	DBLP DOI BibTeX RDF
17	Lei Luo 0006, John M. Wilson 0002, Stephen E. Mick, Jian Xu, Liang Zhang 0038, Paul D. Franzon	3 gb/s AC coupled chip-to-chip communication using a low swing pulse receiver.	IEEE J. Solid State Circuits	2006	DBLP DOI BibTeX RDF
17	Ilham Hassoune, François Macé, Denis Flandre, Jean-Didier Legat	Low-swing current mode logic (LSCML): A new logic style for secure and robust smart cards against power analysis attacks.	Microelectron. J.	2006	DBLP DOI BibTeX RDF
17	Ethiopia Nigussie, Juha Plosila, Jouni Isoaho	Delay-Insensitive On-Chip Communication Link using Low-Swing Simultaneous Bidirectional Signaling.	ISVLSI	2006	DBLP DOI BibTeX RDF
17	Vishak Venkatraman, Mark A. Anders 0001, Himanshu Kaul, Wayne P. Burleson, Ram Krishnamurthy 0001	A Low-swing Signaling Circuit Technique for 65nm On-chip Interconnects.	SoCC	2006	DBLP DOI BibTeX RDF
17	Peter Caputa, Mark A. Anders 0001, Christer Svensson, Ram K. Krishnamurthy, Shekhar Borkar	A low-swing single-ended L1 cache bus technique for sub-90nm technologies.	ESSCIRC	2004	DBLP DOI BibTeX RDF
17	Chulwoo Kim, Sung-Mo Kang	A low-swing clock double-edge triggered flip-flop.	IEEE J. Solid State Circuits	2002	DBLP DOI BibTeX RDF
17	Abdoul Rjoub, Odysseas G. Koufopavlou	Multiple low swing voltage values for CPL, CVSL and domino logic families.	ICECS	2000	DBLP DOI BibTeX RDF
17	Henrik O. Johansson, Christer Svensson	Time resolution of NMOS sampling switches used on low-swing signals.	IEEE J. Solid State Circuits	1998	DBLP DOI BibTeX RDF
17	Hui Zhang 0008, Jan M. Rabaey	Low-swing interconnect interface circuits.	ISLPED	1998	DBLP DOI BibTeX RDF
13	Eisse Mensink, Daniël Schinkel, Eric A. M. Klumperink, Ed van Tuijl, Bram Nauta	Optimal Positions of Twists in Global On-Chip Differential Interconnects.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF