Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
118 | Anish Muttreja, Anand Raghunathan, Srivaths Ravi 0001, Niraj K. Jha |
Automated energy/performance macromodeling of embedded software. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
data serialization, genetic programming, regression, embedded software, symbolic, macromodeling |
110 | Tat Kee Tan, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha |
High-level energy macromodeling of embedded software. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
96 | Felipe Klein, Guido Araujo, Rodolfo Azevedo, Roberto Leao, Luiz C. V. dos Santos |
A multi-model power estimation engine for accuracy optimization. |
ISLPED |
2007 |
DBLP DOI BibTeX RDF |
power macromodeling, powerSC, low power design, systemC, power estimation |
81 | Giuseppe Bernacchia, Marios C. Papaefthymiou |
Analytical macromodeling for high-level power estimation. |
ICCAD |
1999 |
DBLP DOI BibTeX RDF |
|
66 | Anish Muttreja, Anand Raghunathan, Srivaths Ravi 0001, Niraj K. Jha |
Automated Energy/Performance Macromodeling of Embedded Software. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
66 | Felipe Klein, Guido Araujo, Rodolfo Azevedo, Roberto Leao, Luiz C. V. dos Santos |
On the Limitations of Power Macromodeling Techniques. |
ISVLSI |
2007 |
DBLP DOI BibTeX RDF |
|
66 | Mengmeng Ding, Ranga Vemuri |
A Two-Level Modeling Approach to Analog Circuit Performance Macromodeling. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
59 | Min Zhao 0001, Rajendran Panda, Savithri Sundareswaran, Shu Yan, Yuhong Fu |
A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
sequence of linear programming, macromodeling, budgeting, decoupling capacitance |
59 | Yuantao Peng, Xun Liu |
Power macromodeling of global interconnects considering practical repeater insertion. |
ACM Great Lakes Symposium on VLSI |
2004 |
DBLP DOI BibTeX RDF |
low power, interconnect, macromodeling, repeater insertion |
59 | Yongjun Xu, Zuying Luo, Zhiguo Chen, Xiaowei Li 0001 |
Average Leakage Current Macromodeling for Dual-Threshold Voltage Circuits. |
Asian Test Symposium |
2003 |
DBLP DOI BibTeX RDF |
stack effect, leakage current simulation, propagation of signal probability, macromodeling |
52 | Xiaolue Lai, Jaijeet S. Roychowdhury |
Advanced tools for simulation and design of oscillators/PLLs. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
jitter analysis, automated oscillator, macromodeling technique, amplitude macromodels, injection locking prediction, coupled oscillating systems, SPICE, PLL |
52 | Jinwoo Choi, Sung-Hwan Min, Joong-Ho Kim, Madhavan Swaminathan, Wendemagegnehu T. Beyene, Chuck Yuan |
Modeling and Analysis of Power Distribution Networks for Gigabit Applications. |
IEEE Trans. Mob. Comput. |
2003 |
DBLP DOI BibTeX RDF |
transmission matrix method, power bus, decoupling, macromodeling, Power distribution network |
51 | Hai Wang 0002, Hao Yu 0001, Sheldon X.-D. Tan |
Fast analysis of nontree-clock network considering environmental uncertainty by parameterized and incremental macromodeling. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
51 | Zhe Wang, Rajeev Murgai, Jaijeet S. Roychowdhury |
ADAMIN: automated, accurate macromodeling of digital aggressors for power and ground supply noise prediction. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
51 | Tat Kee Tan, Anand Raghunathan, Niraj K. Jha |
Energy macromodeling of embedded operating systems. |
ACM Trans. Embed. Comput. Syst. |
2005 |
DBLP DOI BibTeX RDF |
Linux, energy consumption, characterization |
51 | Xun Liu, Marios C. Papaefthymiou |
Incorporation of input glitches into power macromodeling. |
ISCAS (4) |
2002 |
DBLP DOI BibTeX RDF |
|
51 | Qinwei Xu, Pinaki Mazumder, Li Ding 0002 |
Novel macromodeling for on-chip RC/RLC interconnects. |
ISCAS (4) |
2002 |
DBLP DOI BibTeX RDF |
|
51 | Aditya D. Sathe, Michael L. Bushnell, Vishwani D. Agrawal |
Analog Macromodeling of Capacitive Coupling Faults in Digital Circuit Interconnects. |
ITC |
2002 |
DBLP DOI BibTeX RDF |
|
51 | Qinwei Xu, Pinaki Mazumder |
Efficient Macromodeling for On-Chip Interconnects. |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
|
45 | Ning Dong 0002, Jaijeet S. Roychowdhury |
Automated nonlinear Macromodelling of output buffers for high-speed digital applications. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
I/O buffer macromodeling, nonlinear macromodeling |
45 | Mirko Loghi, Luca Benini, Massimo Poncino |
Power macromodeling of MPSoC message passing primitives. |
ACM Trans. Embed. Comput. Syst. |
2007 |
DBLP DOI BibTeX RDF |
multiprocessor, system-on-chip, macromodeling, Communication primitives |
45 | Boyuan Yan, Sheldon X.-D. Tan, Pu Liu, Bruce McGaughy |
Passive Interconnect Macromodeling Via Balanced Truncation of Linear Systems in Descriptor Form. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
moment-matching methods, passive interconnect macromodeling, descriptor form, passive model order reduction, projection-based truncated balanced realization method, large RLC interconnect circuits, Lur'e equation, algebraic Riccati equations, generalized Lyapunov equations, passivity preservation, congruence transformation, large scale interconnect circuit, linear systems, structure information, Krylov-subspace methods, block structure, balanced truncation |
45 | Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi |
PRIMA: passive reduced-order interconnect macromodeling algorithm. |
ICCAD |
1997 |
DBLP DOI BibTeX RDF |
MPVL, PRIMA, RLC interconnect circuits, block Arnoldi technique, driver-load models, guaranteed passivity, macromodel passivity, macromodel stability, passive reduced-order interconnect macromodeling algorithm, path tracing algorithm, reduced order N-port models, simulation, CAD, integrated circuit layout, frequency domain, circuit stability |
45 | Chen-Yang Pan, Kwang-Ting Cheng, Sandeep Gupta 0001 |
Fault macromodeling and a testing strategy for opamps. |
J. Electron. Test. |
1996 |
DBLP DOI BibTeX RDF |
catastrophic fault model, operational amplifier design for testability, analog test, macromodeling, parametric faults |
44 | Bing Zhong, Tao Hu, Dawei Fu, Steven L. Dvorak, John L. Prince |
A study of a hybrid phase-pole macromodel for transient simulation of complex interconnects structures. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
37 | Mengmeng Ding, Ranga Vemuri |
A combined feasibility and performance macromodel for analog circuits. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
feasibility models, performance macromodeling, active learning |
37 | Shubhankar Basu, Balaji Kommineni, Ranga Vemuri |
Variation-Aware Macromodeling and Synthesis of Analog Circuits Using Spline Center and Range Method and Dynamically Reduced Design Space. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
37 | Changzhong Chen, Dharmendra Saraswat, Ramachandra Achar, Emad Gad, Michel S. Nakhla, Mustapha Chérif-Eddine Yagoub |
A Robust Algorithm for Passive Reduced-Order Macromodeling of MTLs With FD-PUL Parameters Using Integrated Congruence Transform. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
37 | Chi-Un Lei, Hing-Kit Kwan, Yansong Liu, Ngai Wong |
Efficient linear macromodeling via least-squares response approximation. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
37 | Chi-Un Lei, Ngai Wong |
Efficient Linear Macromodeling via Discrete-Time Time-Domain Vector Fitting. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
37 | Yaseer Arafat Durrani, Ana Abril, Teresa Riesgo |
Efficient Power Macromodeling Technique for IP-Based Digital System. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
37 | Jian Wang, Xin Li 0001, Lawrence T. Pileggi |
Parameterized Macromodeling for Analog System-Level Design Exploration. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
37 | Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla |
Circuit Compatible Macromodeling of High-Speed VLSI Modules Characterized by Scattering Parameters. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
37 | Mengmeng Ding, Ranga Vemuri |
Efficient Analog Performance Macromodeling via Sequential Design Space Decomposition. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
37 | Xun Liu, Marios C. Papaefthymiou |
A Markov chain sequence generator for power macromodeling. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
37 | Alper Demir 0001, Jaijeet S. Roychowdhury |
A reliable and efficient procedure for oscillator PPV computation, with phase noise macromodeling applications. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
37 | Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla |
Passive macromodeling of subnetworks characterized by measured data. |
ISCAS (3) |
2003 |
DBLP DOI BibTeX RDF |
|
37 | Xun Liu, Marios C. Papaefthymiou |
A Markov chain sequence generator for power macromodeling. |
ICCAD |
2002 |
DBLP DOI BibTeX RDF |
|
37 | Roberto Zafalon, Massimo Rossello, Enrico Macii, Massimo Poncino |
Power Macromodeling for a High Quality RT-Level Power Estimation. |
ISQED |
2000 |
DBLP DOI BibTeX RDF |
|
37 | Zhanping Chen, Kaushik Roy 0001 |
A Power Macromodeling Technique Based on Power Sensitivity. |
DAC |
1998 |
DBLP DOI BibTeX RDF |
reconfigurable computing, event-driven simulation |
37 | Jianfeng Shao, Ramesh Harjani |
Macromodeling of analog circuits for hierarchical circuit design. |
ICCAD |
1994 |
DBLP DOI BibTeX RDF |
|
37 | Lynne Michelle Brocco, Steven Paul McCormick, Jonathan Allen |
Macromodeling CMOS circuits for timing simulation. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1988 |
DBLP DOI BibTeX RDF |
|
37 | Mark D. Matson |
Macromodeling of digital MOS VLSI Circuits. |
DAC |
1985 |
DBLP DOI BibTeX RDF |
|
29 | Yung-Ta Li, Zhaojun Bai, Yangfeng Su, Xuan Zeng 0001 |
Model Order Reduction of Parameterized Interconnect Networks via a Two-Directional Arnoldi Process. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
29 | Shubhankar Basu, Balaji Kommineni, Ranga Vemuri |
Variation Aware Spline Center and Range Modeling for Analog Circuit Performance. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
Center and Range, Process Variation, Analog, Spline |
29 | Anish Muttreja, Anand Raghunathan, Srivaths Ravi 0001, Niraj K. Jha |
Hybrid Simulation for Energy Estimation of Embedded Software. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Hao Yu 0001, Chunta Chu, Lei He 0001 |
Off-chip Decoupling Capacitor Allocation for Chip Package Co-Design. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Hao Yu 0001, Joanna Ho, Lei He 0001 |
Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity. |
ACM Trans. Design Autom. Electr. Syst. |
2009 |
DBLP DOI BibTeX RDF |
Thermal and power integrity, parametric 3D-IC design, macromodeling |
23 | Rick Salay, John Mylopoulos, Steve M. Easterbrook |
Using Macromodels to Manage Collections of Related Models. |
CAiSE |
2009 |
DBLP DOI BibTeX RDF |
Modeling, Mappings, Metamodeling, Relationships, Macromodeling |
23 | Jorgen Peddersen, Sri Parameswaran |
Low-Impact Processor for Dynamic Runtime Power Management. |
IEEE Des. Test Comput. |
2008 |
DBLP DOI BibTeX RDF |
low-impact processor, runtime power management, power estimation, energy aware, macromodeling, counters |
23 | Fabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino |
Power Estimation of Behavioral Descriptions. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
Behavioral power estimation, macromodeling, design exploration |
22 | Fatemeh Charoosaei, Amin Faraji, Sayed Alireza Sadrossadat, Ali Mirvakili, Weicong Na, Feng Feng, Qi-Jun Zhang |
High-Speed Nonlinear Circuit Macromodeling Using Hybrid-Module Clockwork Recurrent Neural Network. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
|
22 | Amin Faraji, Sayed Alireza Sadrossadat, Weicong Na, Feng Feng, Qi-Jun Zhang |
A New Macromodeling Method Based on Deep Gated Recurrent Unit Regularized With Gaussian Dropout for Nonlinear Circuits. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2023 |
DBLP DOI BibTeX RDF |
|
22 | Amin Faraji, Sayed Alireza Sadrossadat, Mahdi Yazdian Dehkordi, Morteza Nabavi, Yvon Savaria |
A Hybrid Approach Based on Recurrent Neural Network for Macromodeling of Nonlinear Electronic Circuits. |
IEEE Access |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Faisal Siddiq, Yaseer Arafat Durrani |
Efficient power macromodeling approach for an IP-based SoC system using discrete water cycle algorithm. |
Turkish J. Electr. Eng. Comput. Sci. |
2021 |
DBLP DOI BibTeX RDF |
|
22 | Ning Wang, Shiyou Yang, Zhuoxiang Ren, Huifang Wang |
An Improved Structure-Preserving Reduced-Order Interconnect Macromodeling for Large-Scale Equation Sets of Transient Interconnect Circuit Problems. |
IEEE Access |
2021 |
DBLP DOI BibTeX RDF |
|
22 | Harry Weber, Harun Baran, Fabian Utermöhlen, Christian Schuster |
Macromodeling of Mutual Inductance for Displaced Coils Based on Laplace's Equation. |
IEEE Trans. Instrum. Meas. |
2021 |
DBLP DOI BibTeX RDF |
|
22 | Nahid Mirzaie, Ron Rohrer |
A Macromodeling Approach for Analog Behavior of Digital Integrated Circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Paolo Manfredi, Stefano Grivet-Talocia |
Rational Polynomial Chaos Expansions for the Stochastic Macromodeling of Network Responses. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Utkarsh R. Patel, Piero Triverio, Sean V. Hum |
A Fast Macromodeling Approach to Efficiently Simulate Inhomogeneous Electromagnetic Surfaces. |
CoRR |
2019 |
DBLP BibTeX RDF |
|
22 | Aswini P. Reghu, R. V. Sanjika Devi, K. Vrinda, Dhanesh G. Kurup |
Macromodeling of High Frequency Interconnects Based on Accurate Delay Identification. |
ICACCI |
2018 |
DBLP DOI BibTeX RDF |
|
22 | Hao Yu 0001, Guoyong Shi |
Symbolic Circuit Reduction for Multistage Amplifier Macromodeling. |
APCCAS |
2018 |
DBLP DOI BibTeX RDF |
|
22 | Utkarsh R. Patel, Piero Triverio, Sean V. Hum |
A Macromodeling Approach to Efficiently Compute Scattering from Large Arrays of Complex Scatterers. |
CoRR |
2017 |
DBLP BibTeX RDF |
|
22 | Marwan Kanaan, Roni Khazaka |
Nonlinear time-domain macromodeling using proper orthogonal decomposition and feedforward neural networks. |
CCECE |
2017 |
DBLP DOI BibTeX RDF |
|
22 | Leibin Ni, Sai Manoj P. D., Yang Song, Chenjie Gu, Hao Yu 0001 |
A Zonotoped Macromodeling for Eye-Diagram Verification of High-Speed I/O Links With Jitter and Parameter Variations. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2016 |
DBLP DOI BibTeX RDF |
|
22 | Fábio Passos, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández 0001, Y. Ye, Domenico Spina, Tom Dhaene |
Frequency-dependent parameterized macromodeling of integrated inductors. |
SMACD |
2016 |
DBLP DOI BibTeX RDF |
|
22 | Zuochang Ye, Tianshi Wang, Yang Li 0183 |
Domain-Alternated Optimization for Passive Macromodeling. |
IEEE Trans. Very Large Scale Integr. Syst. |
2015 |
DBLP DOI BibTeX RDF |
|
22 | H. Herrmann, W. Horchler, S. Schwarz, Philipp Schröter, Frank Klotz, Marco Brignone, Franco Fiori |
Smart power IC macromodeling for DPI analysis. |
EMC Compo |
2015 |
DBLP DOI BibTeX RDF |
|
22 | Ying-Chih Wang, Shihui Yin, Minhee Jun, Xin Li 0001, Lawrence T. Pileggi, Tamal Mukherjee, Rohit Negi |
Accurate passivity-enforced macromodeling for RF circuits via iterative zero/pole update based on measurement data. |
ASP-DAC |
2015 |
DBLP DOI BibTeX RDF |
|
22 | Ehsan Ali, Wenceslas Rahajandraibe, Fayrouz Haddad, Ndiogou Tall, Christian Hangmann, Christian Hedayat |
Simulation and validation of arbitrary ordered VSCP-PLLs using event-driven macromodeling. |
ISCAS |
2015 |
DBLP DOI BibTeX RDF |
|
22 | Yi Qing Xiao, Muhammad Kabir, Marco T. Kassis, Roni Khazaka |
Passive Reduced Order Macromodeling Based on Admittance Parameter Using Hamiltonian-Symplectic Matrix Pencil Perturbation. |
ICUWB |
2015 |
DBLP DOI BibTeX RDF |
|
22 | Chao Ma, Shuguo Xie, Yunfeng Jia, Guanyu Lin |
Macromodeling of the memristor using piecewise volterra series. |
Microelectron. J. |
2014 |
DBLP DOI BibTeX RDF |
|
22 | Ehsan Ali, Wenceslas Rahajandraibe, Fayrouz Haddad, Christian Hangmann, Christian Hedayat |
Simulations of 3rd order voltage switched CP-PLL using a fast event switching macromodeling. |
MWSCAS |
2014 |
DBLP DOI BibTeX RDF |
|
22 | Sai Manoj Pudukotai Dinakarrao, Hao Yu 0001, Chenjie Gu, Cheng Zhuo |
A zonotoped macromodeling for reachability verification of eye-diagram in high-speed I/O links with jitter. |
ICCAD |
2014 |
DBLP DOI BibTeX RDF |
|
22 | Zuochang Ye |
Noise Companion State-Space Passive Macromodeling for RF/mm-Wave Circuit Design. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2013 |
DBLP DOI BibTeX RDF |
|
22 | Paolo Maffezzoni |
Nonlinear Phase-Domain Macromodeling of Injection-Locked Frequency Dividers. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2013 |
DBLP DOI BibTeX RDF |
|
22 | Alessandro Magnani, Vincenzo d'Alessandro, Niccolò Rinaldi, Massimiliano de Magistris, Klaus Aufinger |
Dynamic electrothermal macromodeling techniques for thermal-aware design of circuits and systems. |
PATMOS |
2013 |
DBLP DOI BibTeX RDF |
|
22 | Yang Zhang, Neric Fong, Ngai Wong |
Piecewise-polynomial associated transform macromodeling algorithm for fast nonlinear circuit simulation. |
ASP-DAC |
2013 |
DBLP DOI BibTeX RDF |
|
22 | Chenjie Gu |
Algorithmic nonlinear macromodeling: Challenges, solutions and applications in Analog/Mixed-Signal validation. |
CICC |
2013 |
DBLP DOI BibTeX RDF |
|
22 | Elizabeth Rita Samuel, Luc Knockaert, Tom Dhaene |
Parametric Macromodeling using Interpolation of Sylvester based State-space Realizations. |
ICINCO (1) |
2013 |
DBLP DOI BibTeX RDF |
|
22 | Zuochang Ye |
Pmm: A Matlab toolbox for passive macromodeling in RF/mm-wave circuit design. |
ASICON |
2013 |
DBLP DOI BibTeX RDF |
|
22 | Bin Wu |
A statistically optimal macromodeling framework with application in process variation analysis of MEMS devices. |
NEWCAS |
2012 |
DBLP DOI BibTeX RDF |
|
22 | Pilin Junsangsri, Fabrizio Lombardi, Jie Han 0001 |
Macromodeling a phase change memory (PCM) cell by HSPICE. |
NANOARCH |
2012 |
DBLP DOI BibTeX RDF |
|
22 | Joon Hyung Chung |
Efficient and physically consistent electromagnetic macromodeling of high-speed interconnects exhibiting geometric uncertainties |
|
2012 |
RDF |
|
22 | Ting Zhu 0002, Mustafa Berke Yelten, Michael B. Steer, Paul D. Franzon |
Variation-Aware Circuit Macromodeling and Design Based on Surrogate Models. |
SIMULTECH (Selected Papers) |
2011 |
DBLP DOI BibTeX RDF |
|
22 | Yaseer Arafat Durrani |
Efficient power macromodeling technique for conventional MOS transistors. |
ICEEI |
2011 |
DBLP DOI BibTeX RDF |
|
22 | Dimitri de Jonghe, Georges G. E. Gielen |
Efficient analytical macromodeling of large analog circuits by Transfer Function Trajectories. |
ICCAD |
2011 |
DBLP DOI BibTeX RDF |
|
22 | Hao Yu 0001, Chunta Chu, Yiyu Shi 0001, David Smart, Lei He 0001, Sheldon X.-D. Tan |
Fast Analysis of a Large-Scale Inductive Interconnect by Block-Structure-Preserved Macromodeling. |
IEEE Trans. Very Large Scale Integr. Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
22 | Ádám Rák, György Cserey |
Macromodeling of the Memristor in SPICE. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
22 | Xiaoda Pan, Fan Yang 0001, Xuan Zeng 0001, Yangfeng Su |
An efficient transistor-level piecewise-linear macromodeling approach for model order reduction of nonlinear circuits. |
DATE |
2010 |
DBLP DOI BibTeX RDF |
|
22 | Chi-Un Lei, Ngai Wong |
VISA: versatile impulse structure approximation for time-domain linear macromodeling. |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
|
22 | Chenjie Gu, Jaijeet S. Roychowdhury |
Generalized nonlinear timing/phase macromodeling: Theory, numerical methods and applications. |
ICCAD |
2010 |
DBLP DOI BibTeX RDF |
|
22 | Paolo Maffezzoni, Dario D'Amore |
Compact Electrothermal Macromodeling of Photovoltaic Modules. |
IEEE Trans. Circuits Syst. II Express Briefs |
2009 |
DBLP DOI BibTeX RDF |
|
22 | Ting Zhu 0002, Paul D. Franzon |
An enhanced macromodeling approach for differential output drivers. |
BMAS |
2009 |
DBLP DOI BibTeX RDF |
|
22 | Ying Wei 0002, Alex Doboli |
Structural Macromodeling of Analog Circuits Through Model Decoupling and Transformation. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Tatsuya Koyagi, Masahiro Fukui, Resve A. Saleh |
Delay macromodeling and estimation for RTL. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Ginés Doménech-Asensi, Juan Hinojosa, Ramón Ruiz Merino, José Ángel Díaz-Madrid |
Accurate and reusable macromodeling technique using a fuzzy-logic approach. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Rick Salay, John Mylopoulos, Steve M. Easterbrook |
Managing Models through Macromodeling. |
ASE |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Shubhankar Basu, Balaji Kommineni, Ranga Vemuri |
Mismatch Aware Analog Performance Macromodeling Using Spline Center and Range Regression on Adaptive Samples. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Zhigang Hao, Guoyong Shi |
New approaches to interconnect macromodeling with explicit delay extraction. |
APCCAS |
2008 |
DBLP DOI BibTeX RDF |
|