Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
106 | Yao-Joe Joseph Yang, Chi-Wei Kuo |
Generating Scalable and Modular Macromodels for Microchannels Using the Galerkin-Based Technique. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
92 | Ting Mei, Jaijeet S. Roychowdhury |
PPV-HB: harmonic balance for oscillator/PLL phase macromodels. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
|
82 | Saket Srivastava, Sanjukta Bhanja |
Hierarchical Probabilistic Macromodeling for QCA Circuits. |
IEEE Trans. Computers |
2007 |
DBLP DOI BibTeX RDF |
QCA computing, QCA macromodel, Bayesian networks, Quantum-dot Cellular Automata, probabilistic computing |
68 | Xiaolue Lai, Jaijeet S. Roychowdhury |
TP-PPV: piecewise nonlinear, time-shifted oscillator macromodel extraction for fast, accurate PLL simulation. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
|
66 | Xiaolue Lai, Jaijeet S. Roychowdhury |
Advanced tools for simulation and design of oscillators/PLLs. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
jitter analysis, automated oscillator, macromodeling technique, amplitude macromodels, injection locking prediction, coupled oscillating systems, SPICE, PLL |
65 | Ying Wei 0002, Alex Doboli |
Library of structural analog cell macromodels for design of continuous-time reconfigurable Delta Sigma modulators. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
65 | Xin Li 0001, Peng Li 0001, Yang Xu 0017, Lawrence T. Pileggi |
Analog and RF circuit macromodels for system-level analysis. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
analog/RF circuits, macromodel |
65 | Seok-Yoon Kim, Nanda Gopal, Lawrence T. Pillage |
Time-domain macromodels for VLSI interconnect analysis. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1994 |
DBLP DOI BibTeX RDF |
|
65 | K. K. Low, Stephen W. Director |
An efficient methodology for building macromodels of IC fabrication processes. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1989 |
DBLP DOI BibTeX RDF |
|
54 | Xiaolue Lai, Jaijeet S. Roychowdhury |
Macromodelling oscillators using Krylov-subspace methods. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
54 | Ning Dong 0002, Jaijeet S. Roychowdhury |
Automated nonlinear Macromodelling of output buffers for high-speed digital applications. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
I/O buffer macromodeling, nonlinear macromodeling |
54 | Xiaolue Lai, Jaijeet S. Roychowdhury |
Automated oscillator macromodelling techniques for capturing amplitude variations and injection locking. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
54 | Jeong-Taek Kong, David Overhauser |
Methods to improve digital MOS macromodel accuracy. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1995 |
DBLP DOI BibTeX RDF |
|
54 | Ayman I. Kayssi, Karem A. Sakallah |
Timing models for gallium arsenide direct-coupled FET logic circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1995 |
DBLP DOI BibTeX RDF |
|
51 | Xiaoji Ye, Min Zhao 0001, Rajendran Panda, Peng Li 0001, Jiang Hu |
Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
clock mesh, dynamic time step rounding, simulation, macromodel |
51 | Saurabh K. Tiwary, Rob A. Rutenbar |
Faster, parametric trajectory-based macromodels via localized linear reductions. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
|
51 | Mengmeng Ding, Glenn Wolfe, Ranga Vemuri |
An error-driven adaptive grid refinement algorithm for automatic generation of analog circuit performance macromodels. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
51 | Stefano Grivet-Talocia, Igor S. Stievano, Ivan A. Maio, Flavio G. Canavero |
Linear and nonlinear macromodels for power/signal integrity. |
ISCAS (6) |
2005 |
DBLP DOI BibTeX RDF |
|
51 | Roberto Corgnati, Enrico Macii, Massimo Poncino |
Clustered Table-Based Macromodels for RTL Power Estimation. |
Great Lakes Symposium on VLSI |
1999 |
DBLP DOI BibTeX RDF |
|
49 | S. Dabas, Ning Dong 0002, Jaijeet S. Roychowdhury |
Automated Extraction of Accurate Delay/Timing Macromodels of Digital Gates and Latches using Trajectory Piecewise Methods. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
gate delay modelling, accurate delay/timing macromodels, digital gates, trajectory-piecewise automated nonlinear macromodelling methods, mixed-signal/RF domain, SPICE-level netlists, transparent retargetability, NAND gates, NOR gates, sequential latch, latches, full adder, current-source models, XOR gates |
41 | Zhe Wang, Rajeev Murgai, Jaijeet S. Roychowdhury |
ADAMIN: automated, accurate macromodeling of digital aggressors for power and ground supply noise prediction. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
41 | Mengmeng Ding, Ranga Vemuri |
A combined feasibility and performance macromodel for analog circuits. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
feasibility models, performance macromodeling, active learning |
41 | Jimmy Shinn-Hwa Wang, Wayne Wei-Ming Dai |
Transient analysis of coupled transmission lines characterized with the frequency-dependent losses using scattering-parameter based macromodel. |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
coupled transmission lines, frequency-dependent losses, scattering-parameter based macromodel, S-parameter macromodel based simulator, circuit analysis computing, transient analysis, transient analysis, transmission lines, losses, S-parameters |
39 | José Vicente Calvano, Vladimir Castro Alves, Marcelo Lubaszewski |
Testing a PWM circuit using functional fault models and compact test vectors for operational amplifiers. |
Asian Test Symposium |
2000 |
DBLP DOI BibTeX RDF |
PWM circuit, compact test vectors, analog VLSI technology, functional fault macromodels, compact test vector construction, open loop gain, CMMR, analog circuit simulation complexity, VLSI, integrated circuit testing, design for testability, automatic test pattern generation, fault modeling, fault simulation, fault simulation, operational amplifiers, operational amplifiers, test pattern, functional fault models, analogue circuits, fault dictionary, pulse width modulation, slew-rate |
39 | Ayman I. Kayssi |
Macromodeling C- and RC-loaded CMOS inverters for timing analysis. |
Great Lakes Symposium on VLSI |
1996 |
DBLP DOI BibTeX RDF |
RC-loaded CMOS inverters, C-loaded CMOS inverters, series-resistor shunt-capacitor circuit, capacitive load case, input wave shape, transistor drive, timing, logic CAD, timing analysis, circuit analysis computing, CMOS logic circuits, circuit simulation, table lookup, macromodels, logic gates, lookup table, integrated circuit modelling |
39 | Anirudh Devgan, Ronald A. Rohrer |
Efficient simulation of interconnect and mixed analog-digital circuits in ACES. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
adaptively controlled explicit simulation, mixed analog-digital circuits, analog circuit simulation, interconnect circuit simulation, AWE macromodels, nonlinear terminations, variable accuracy device models, circuit topology constraints removal, timing, circuit analysis computing, transient analysis, analogue integrated circuits, integrated circuit interconnections, mixed analogue-digital integrated circuits, ACES, transient simulation, timing simulation |
39 | Wolfgang Borutzky |
Combining Behavioral Block Diagram Modelling with Circuit Simulation. |
EUROCAST |
1989 |
DBLP DOI BibTeX RDF |
mixed behavioral, circuit-level modelling, electrical macromodels, continuous system simulation, electronic control systems, circuit simulation, functional simulation, block diagrams, signal processing systems |
38 | Rick Salay, John Mylopoulos, Steve M. Easterbrook |
Using Macromodels to Manage Collections of Related Models. |
CAiSE |
2009 |
DBLP DOI BibTeX RDF |
Modeling, Mappings, Metamodeling, Relationships, Macromodeling |
38 | Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla |
Fast Passivity Verification and Enforcement via Reciprocal Systems for Interconnects With Large Order Macromodels. |
IEEE Trans. Very Large Scale Integr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
38 | Ying Wei 0002, Alex Doboli |
Systematic development of nonlinear analog circuit macromodels through successive operator composition and nonlinear model decoupling. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
nonlinear macromodel, structural macromodel, analog circuits |
38 | Xiaolue Lai, Jaijeet S. Roychowdhury |
A multilevel technique for robust and efficient extraction of phase macromodels of digitally controlled oscillators. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
DCO, PPV, simulation, PLL, macromodel, VCO, DPLL |
38 | Xiaolue Lai, Yayun Wan, Jaijeet S. Roychowdhury |
Fast PLL simulation using nonlinear VCO macromodels for accurate prediction of jitter and cycle-slipping due to loop non-idealities and supply noise. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla |
On passivity enforcement for macromodels of S-parameter based tabulated subnetworks. |
ISCAS (4) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Ying Wei 0002, Alex Doboli |
Systematic development of analog circuit structural macromodels through behavioral model decoupling. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
structural macromodel, analog circuits |
38 | Davide Bertozzi, Luca Benini, Bruno Riccò |
Parametric timing and power macromodels for high level simulation of low-swing interconnects. |
ISLPED |
2002 |
DBLP DOI BibTeX RDF |
delay, interconnect, power, macromodel, low-swing |
38 | Anil Samavedam, Kartikeya Mayaram, Terri S. Fiez |
Design-oriented substrate noise coupling macromodels for heavily doped CMOS processes. |
ISCAS (6) |
1999 |
DBLP DOI BibTeX RDF |
|
38 | Yun-Cheng Ju, Vasant B. Rao, Resve A. Saleh |
Consistency checking and optimization of macromodels. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1991 |
DBLP DOI BibTeX RDF |
|
27 | Kanupriya Gulati, Sunil P. Khatri, Peng Li 0001 |
Closed-loop modeling of power and temperature profiles of FPGAs. |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
sub-threshold leakage, dynamic power |
27 | António Gusmão, L. Miguel Silveira, José Monteiro 0001 |
Parameter tuning in SVM-based power macro-modeling. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
|
27 | Ning Dong 0002, Jaijeet S. Roychowdhury |
General-Purpose Nonlinear Model-Order Reduction Using Piecewise-Polynomial Representations. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Shubhankar Basu, Balaji Kommineni, Ranga Vemuri |
Variation Aware Spline Center and Range Modeling for Analog Circuit Performance. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
Center and Range, Process Variation, Analog, Spline |
27 | Shubhankar Basu, Balaji Kommineni, Ranga Vemuri |
Mismatch Aware Analog Performance Macromodeling Using Spline Center and Range Regression on Adaptive Samples. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Anish Muttreja, Anand Raghunathan, Srivaths Ravi 0001, Niraj K. Jha |
Automated Energy/Performance Macromodeling of Embedded Software. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
27 | José Carlos S. Palma, Leandro Soares Indrusiak, Fernando Gehm Moraes, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis |
Inserting Data Encoding Techniques into NoC-Based Systems. |
ISVLSI |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Wei Dong 0002, Zhuo Feng, Peng Li 0001 |
Efficient VCO phase macromodel generation considering statistical parametric variations. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Jian Wang, Xin Li 0001, Lawrence T. Pileggi |
Parameterized Macromodeling for Analog System-Level Design Exploration. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man |
SWAN: high-level simulation methodology for digital substrate noise generation. |
IEEE Trans. Very Large Scale Integr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
27 | José Carlos S. Palma, Leandro Soares Indrusiak, Fernando Gehm Moraes, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis |
Adaptive Coding in Networks-on-Chip: Transition Activity Reduction Versus Power Overhead of the Codec Circuitry. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
27 | José Carlos S. Palma, Ricardo A. L. Reis, Leandro Soares Indrusiak, Alberto García Ortiz, Manfred Glesner, Fernando Gehm Moraes |
Evaluating the Impact of Data Encoding Techniques on the Power Consumption in Networks-on-Chip. |
ISVLSI |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Shweta Chary, Michael L. Bushnell |
Analog Macromodeling for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Tat Kee Tan, Anand Raghunathan, Niraj K. Jha |
Energy macromodeling of embedded operating systems. |
ACM Trans. Embed. Comput. Syst. |
2005 |
DBLP DOI BibTeX RDF |
Linux, energy consumption, characterization |
27 | Roland W. Freund |
SPRIM: structure-preserving reduced-order interconnect macromodeling. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Mirko Loghi, Luca Benini, Massimo Poncino |
Analyzing Power Consumption of Message Passing Primitives in a Single-Chip Multiprocessor. |
ICCD |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Anish Muttreja, Anand Raghunathan, Srivaths Ravi 0001, Niraj K. Jha |
Automated energy/performance macromodeling of embedded software. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
data serialization, genetic programming, regression, embedded software, symbolic, macromodeling |
27 | Subodh Gupta, Farid N. Najm |
Energy and peak-current per-cycle estimation at RTL. |
IEEE Trans. Very Large Scale Integr. Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Peng Li 0001, Xin Li 0001, Yang Xu 0017, Lawrence T. Pileggi |
A Hybrid Approach to Nonlinear Macromodel Generation for Time-Varying Analog Circuits. |
ICCAD |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla |
Passive macromodeling of subnetworks characterized by measured data. |
ISCAS (3) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Min Zhao 0001, Rajendran Panda, Sachin S. Sapatnekar, David T. Blaauw |
Hierarchical analysis of power distribution networks. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
27 | Tat Kee Tan, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha |
High-level energy macromodeling of embedded software. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
27 | Aditya D. Sathe, Michael L. Bushnell, Vishwani D. Agrawal |
Analog Macromodeling of Capacitive Coupling Faults in Digital Circuit Interconnects. |
ITC |
2002 |
DBLP DOI BibTeX RDF |
|
27 | Min Zhao 0001, Rajendran Panda, Sachin S. Sapatnekar, Tim Edwards, Rajat Chaudhry, David T. Blaauw |
Hierarchical analysis of power distribution networks. |
DAC |
2000 |
DBLP DOI BibTeX RDF |
|
27 | Kenneth L. Shepard, Vinod Narayanan, Ron Rose |
Harmony: static noise analysis of deep submicron digital integrated circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1999 |
DBLP DOI BibTeX RDF |
|
27 | Kenneth L. Shepard, Vinod Narayanan, Peter C. Elmendorf, Gutuan Zheng |
Global harmony: coupled noise analysis for full-chip RC interconnect networks. |
ICCAD |
1997 |
DBLP DOI BibTeX RDF |
interconnect, noise, static timing analysis |
27 | Giorgio Casinovi, Alberto L. Sangiovanni-Vincentelli |
A macromodeling algorithm for analog circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1991 |
DBLP DOI BibTeX RDF |
|
27 | Veronika Eisele, Bernhard Hoppe, Oliver Kiehl |
Transmission gate delay models for circuit optimization. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
25 | Joel Coburn, Srivaths Ravi 0001, Anand Raghunathan |
Power emulation: a new paradigm for power estimation. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
simulation, FPGA, design, design methodologies, emulation, hardware acceleration, power estimation, register-transfer level, macromodels |
25 | Anish Muttreja, Anand Raghunathan, Srivaths Ravi 0001, Niraj K. Jha |
Hybrid simulation for embedded software energy estimation. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
energy macromodels, embedded software, pointers analysis, energy estimation, hybrid simulation |
25 | Rex Min, Anantha P. Chandrakasan |
A framework for energy-scalable communication in high-density wireless networks. |
ISLPED |
2002 |
DBLP DOI BibTeX RDF |
?AMPS, distributed microsensors, energy scalability, transmit power, wireless sensor networks, dynamic voltage scaling, forward error correction, power awareness, macromodels, energy models, API design |
25 | Michael Eiermann, Walter Stechele |
Novel modeling techniques for RTL power estimation. |
ISLPED |
2002 |
DBLP DOI BibTeX RDF |
RTL macromodels, low power, power estimation, power modeling |
24 | Ziweihua Du, Ning Dong, Yan-Zhao Xie |
Behavioral Modeling Method of Macromodels for Interconnected Systems With Frequency Characteristics and Nonlinear Termination Networks. |
IEEE Trans. Circuits Syst. II Express Briefs |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Guoyong Shi |
Automatic generation of macromodels and design equations for application to Op Amp design. |
Int. J. Circuit Theory Appl. |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Tommaso Bradde, Stefano Grivet-Talocia, Alessandro Zanco, Giuseppe Carlo Calafiore |
Data-Driven Extraction of Uniformly Stable and Passive Parameterized Macromodels. |
IEEE Access |
2022 |
DBLP DOI BibTeX RDF |
|
24 | Alessandro Zanco, Stefano Grivet-Talocia, Tommaso Bradde, Marco De Stefano |
Enforcing Passivity of Parameterized LTI Macromodels via Hamiltonian-Driven Multivariate Adaptive Sampling. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2020 |
DBLP DOI BibTeX RDF |
|
24 | Marco De Stefano, Stefano Grivet-Talocia, Torben Wendt, Cheng Yang, Christian Schuster |
A Multi-Stage Adaptive Sampling Scheme for Passivity Characterization of Large-Scale Macromodels. |
CoRR |
2020 |
DBLP BibTeX RDF |
|
24 | Stefano Grivet-Talocia |
A Perturbation Scheme for Passivity Verification and Enforcement of Parameterized Macromodels. |
CoRR |
2017 |
DBLP BibTeX RDF |
|
24 | Aleksei V. Batov, Vladimir V. Breer, Dmitry A. Novikov, Andrey D. Rogatkin |
Micro- and macromodels of social networks. II. Identification and simulation experiments. |
Autom. Remote. Control. |
2016 |
DBLP DOI BibTeX RDF |
|
24 | Vladimir V. Breer, Dmitry A. Novikov, Andrey D. Rogatkin |
Micro- and macromodels of social networks. I. Theory fundamentals. |
Autom. Remote. Control. |
2016 |
DBLP DOI BibTeX RDF |
|
24 | Lokesh Garg, Vineet Sahula |
Macromodels for Static Virtual Ground Voltage Estimation in Power-Gated Circuits. |
IEEE Trans. Circuits Syst. II Express Briefs |
2016 |
DBLP DOI BibTeX RDF |
|
24 | Wenjian Yu, Bolong Zhang, Chao Zhang, Haiquan Wang, Luca Daniel |
Utilizing macromodels in floating random walk based capacitance extraction. |
DATE |
2016 |
DBLP BibTeX RDF |
|
24 | Mike Brinson, Vadim Kuznetsov |
Current conveyor macromodels for wideband RF circuit design. |
MIXDES |
2016 |
DBLP DOI BibTeX RDF |
|
24 | Paolo Maffezzoni, Bichoy Bahr, Zheng Zhang 0005, Luca Daniel |
Analysis and Design of Weakly Coupled LC Oscillator Arrays Based on Phase-Domain Macromodels. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Katarzyna Opalska |
Generation of parameterized macromodels of two-port RF circuits for SPICE simulator. |
ECCTD |
2015 |
DBLP DOI BibTeX RDF |
|
24 | A. Ubolli, Stefano Grivet-Talocia, M. Bandinu, Alessandro Chinea |
Sensitivity-based weighting for passivity enforcement of linear macromodels in power integrity applications. |
DATE |
2014 |
DBLP DOI BibTeX RDF |
|
24 | Ginés Doménech-Asensi, José Ángel Díaz-Madrid, Ramón Ruiz Merino |
Synthesis of CMOS analog circuit VHDL-AMS descriptions using parameterizable macromodels. |
Int. J. Circuit Theory Appl. |
2013 |
DBLP DOI BibTeX RDF |
|
24 | Muhammad Umer Farooq, Likun Xia |
Local approximation improvement of trajectory piecewise linear macromodels through Chebyshev interpolating polynomials. |
ASP-DAC |
2013 |
DBLP DOI BibTeX RDF |
|
24 | Shivam Priyadarshi, T. Robert Harris, Samson Melamed, Carlos Tadeo Ortega Otero, Nikhil Kriplani, Carlos E. Christoffersen, Rajit Manohar, Steven R. Dooley, W. Rhett Davis, Paul D. Franzon, Michael B. Steer |
Dynamic electrothermal simulation of three-dimensional integrated circuits using standard cell macromodels. |
IET Circuits Devices Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
24 | L. Gobbato, Alessandro Chinea, Stefano Grivet-Talocia |
A parallel Hamiltonian eigensolver for passivity characterization and enforcement of large interconnect macromodels. |
DATE |
2011 |
DBLP DOI BibTeX RDF |
|
24 | Alessandro Chinea, Stefano Grivet-Talocia, Dirk Deschrijver, Tom Dhaene, Luc Knockaert |
On the construction of guaranteed passive macromodels for high-speed channels. |
DATE |
2010 |
DBLP DOI BibTeX RDF |
|
24 | Changzhong Chen, Dharmendra Saraswat, Ramachandra Achar, Emad Gad, Michel S. Nakhla, Mustapha Chérif-Eddine Yagoub |
Passivity Compensation Algorithm for Method-of-Characteristics-Based Multiconductor Transmission Line Interconnect Macromodels. |
IEEE Trans. Very Large Scale Integr. Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
24 | Davit Harutyunyan, Joost Rommes, E. Jan W. ter Maten, Wil H. A. Schilders |
Simulation of Mutually Coupled Oscillators Using Nonlinear Phase Macromodels. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
24 | Stefano Grivet-Talocia |
On driving non-passive macromodels to instability. |
Int. J. Circuit Theory Appl. |
2009 |
DBLP DOI BibTeX RDF |
|
24 | Georges G. E. Gielen, Dimitri de Jonghe, Johan Loeckx |
Towards automated extraction of EMC-aware trajectory-based macromodels for analog circuits. |
ECCTD |
2009 |
DBLP DOI BibTeX RDF |
|
24 | Ritochit Chakraborty, Arun V. Sathanur, Vikram Jandhyala |
Active-passive co-synthesis of multi-GigaHertz radio frequency circuits with broadband parametric macromodels of on-chip passives. |
ICCAD |
2009 |
DBLP DOI BibTeX RDF |
|
24 | Vladimir S. Lerner |
Cooperative information space distributed macromodels. |
Int. J. Control |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Zhichun Wang, Jaijeet S. Roychowdhury |
Obtaining Frequency Sensitivities to Variations Analytically from Parameterized Nonlinear Oscillator Phase Macromodels. |
CICC |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Zhichun Wang, Xiaolue Lai, Jaijeet S. Roychowdhury |
PV-PPV: Parameter Variability Aware, Automatically Extracted, Nonlinear Time-Shifted Oscillator Macromodels. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Wataru Kuroki, Kiyotaka Yamamura |
A SPICE-Oriented Method for Finding DC Operating Points of Nonlinear Circuits Containing Piecewise-Linear Macromodels. |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Prashant Goyal, Xiaolue Lai, Jaijeet S. Roychowdhury |
A fast methodology for first-time-correct design of PLLs using nonlinear phase-domain VCO macromodels. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Saurabh K. Tiwary, Rob A. Rutenbar |
On-the-Fly Fidelity Assessment for Trajectory-Based Circuit Macromodels. |
CICC |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Min Ma, Alfred Tze-Mun Leung, Roni Khazaka |
Sparse macromodels for parametric networks. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|