Search results for "mesochronous"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
182	Suryanarayana Tatapudi, José G. Delgado-Frias	A mesochronous pipeline scheme for high performance low power digital systems.	ISCAS	2006	DBLP DOI BibTeX RDF
117	Daniele Mangano, G. Falconeri, Carlo Pistritto, Alberto Scandurra	Effective full-duplex Mesochronous Link Architecture for Network-on-Chip Data-Link layer.	DSD	2007	DBLP DOI BibTeX RDF
73	Igor Loi, Federico Angiolini, Luca Benini	Developing Mesochronous Synchronizers to Enable 3D NoCs.	DATE	2008	DBLP DOI BibTeX RDF
51	Francesco Vitullo, Nicola E. L'Insalata, Esa Petri, Sergio Saponara, Luca Fanucci, Michele Casula, Riccardo Locatelli, Marcello Coppola	Low-Complexity Link Microarchitecture for Mesochronous Communication in Networks-on-Chip.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
51	Sergio Saponara, Francesco Vitullo, Riccardo Locatelli, Philippe Teninge, Marcello Coppola, Luca Fanucci	LIME: A Low-latency and Low-complexity On-chip Mesochronous Link with Integrated Flow Control.	DSD	2008	DBLP DOI BibTeX RDF
51	Wade L. Williams, Philip E. Madrid, Scott C. Johnson	Low Latency Clock Domain Transfer for Simultaneously Mesochronous, Plesiochronous and Heterochronous Interfaces.	ASYNC	2007	DBLP DOI BibTeX RDF
51	Seokjin Kim, Ramalingam Sridhar	Self-Timed Mesochronous Interconnection for High-Speed VLSI Systems.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
44	Tobias Bjerregaard, Mikkel Bystrup Stensgaard, Jens Sparsø	A scalable, timing-safe, network-on-chip architecture with an integrated clock distribution method.	DATE	2007	DBLP DOI BibTeX RDF
36	Ran Ginosar	Metastability and Synchronizers: A Tutorial.	IEEE Des. Test Comput.	2011	DBLP DOI BibTeX RDF	FIFO synchronizer, mesochronous, multisynchronous, synchronizer, asynchronous, design and test, metastability
30	Fateme Sadat Ayatollahi, M. B. Ghaznavi-Ghoushchi, Naser Mohammadzadeh, Seyedeh Fatemeh Ghamkhari	AMPS: An Automated Mesochronous Pipeline Scheduler and Design Space Explorer for High Performance Digital Circuits.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
30	Giorgos Dimitrakopoulos, Anastasios Psarras, Chrysostomos Nicopoulos	Virtual-Channel Flow Control Across Mesochronous Clock Domains.	MOCAST	2022	DBLP DOI BibTeX RDF
30	Dimitrios Konstantinou, Anastasios Psarras, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos	The Mesochronous Dual-Clock FIFO Buffer.	IEEE Trans. Very Large Scale Integr. Syst.	2020	DBLP DOI BibTeX RDF
30	Johannes Ax, Nils Kucza, Marten Vohrmann, Thorsten Jungeblut, Mario Porrmann, Ulrich Rückert 0001	Comparing Synchronous, Mesochronous and Asynchronous NoCs for GALS Based MPSoCs.	MCSoC	2017	DBLP DOI BibTeX RDF
30	Naveen Kadayinti, Amitalok J. Budkuley, Dinesh Kumar Sharma	Settling time of mesochronous clock re-timing circuits in the presence of timing jitter.	ISCAS	2017	DBLP DOI BibTeX RDF
30	Naveen Kadayinti, Amitalok J. Budkuley, Dinesh Kumar Sharma	Settling Time of Mesochronous Clock Retiming Circuits for Low Swing Interconnects.	CoRR	2016	DBLP BibTeX RDF
30	Dmitry Verbitsky, Rostislav (Reuven) Dobkin, Ran Ginosar, Salomon Beer	StarSync: An extendable standard-cell mesochronous synchronizer.	Integr.	2014	DBLP DOI BibTeX RDF
30	Mounir Zid, Rached Tourki, Alberto Scandurra, Carlo Pistritto	A mesochronous outfit for Network-on-Chip's interconnects retiming.	DTIS	2012	DBLP DOI BibTeX RDF
30	Sanquan Song, Vladimir Stojanovic	A 6.25 Gb/s Voltage-Time Conversion Based Fractionally Spaced Linear Receive Equalizer for Mesochronous High-Speed Links.	IEEE J. Solid State Circuits	2011	DBLP DOI BibTeX RDF
30	Jean-Michel Chabloz, Ahmed Hemani	Low-Latency and Low-Overhead Mesochronous and Plesiochronous Synchronizers.	DSD	2011	DBLP DOI BibTeX RDF
30	Daniele Ludovici, Alessandro Strano, Georgi Nedeltchev Gaydadjiev, Davide Bertozzi	Mesochronous NoC technology for power-efficient GALS MPSoCs.	INA-OCMC@HiPEAC	2011	DBLP DOI BibTeX RDF
30	Daniele Ludovici, Alessandro Strano, Georgi Nedeltchev Gaydadjiev, Luca Benini, Davide Bertozzi	Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs.	DATE	2010	DBLP DOI BibTeX RDF
30	Daniele Ludovici, Alessandro Strano, Davide Bertozzi, Luca Benini, Georgi Gaydadjiev	Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture.	NOCS	2009	DBLP DOI BibTeX RDF
30	Suryanarayana Tatapudi, José G. Delgado-Frias	A mesochronous pipelining scheme for high-performance digital systems.	IEEE Trans. Circuits Syst. I Regul. Pap.	2006	DBLP DOI BibTeX RDF
30	Behzad Mesgarzadeh, Christer Svensson, Atila Alvandpour	A new mesochronous clocking scheme for synchronization in SoC.	ISCAS (2)	2004	DBLP BibTeX RDF
30	Ingemar Söderquist	Globally updated mesochronous design style.	IEEE J. Solid State Circuits	2003	DBLP DOI BibTeX RDF
30	Junji Ogawa, Mark Horowitz	A 64Mbit Mesochronous Hybrid Wave Pipelined Multibank DRAM Macro.	Intelligent Memory Systems	2000	DBLP DOI BibTeX RDF
22	Mahdi Nazm Bojnordi, Nariman Moezzi Madani, Mehdi Semsarzadeh, Ali Afzali-Kusha	An Efficient Clocking Scheme for On-Chip Communications.	APCCAS	2006	DBLP DOI BibTeX RDF
22	Se-Joong Lee, Kangmin Lee, Hoi-Jun Yoo	Analysis and Implementation of Practical, Cost-Effective Networks on Chips.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	Network connectivity chips, VLSI, Advanced technologies
22	Yaron Semiat, Ran Ginosar	Timing Measurements of Synchronization Circuits.	ASYNC	2003	DBLP DOI BibTeX RDF
22	Fenghao Mu, Christer Svensson	High speed interface for system-on-chip design by self-tested self-synchronization.	ISCAS (2)	1999	DBLP DOI BibTeX RDF