Search results for "micro-architecture"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
51	Allon Adir, Hezi Azatchi, Eyal Bin, Ofer Peled, Kirill Shoikhet	A generic micro-architectural test plan approach for microprocessor verification.	DAC	2005	DBLP DOI BibTeX RDF	generic test plan, test generation, coverage, micro-architecture, dynamic verification
41	Shai Erez, Guy Even	An improved micro-architecture for function approximation using piecewise quadratic interpolation.	ICCD	2008	DBLP DOI BibTeX RDF
39	Ashok Jagannathan, Hannah Honghua Yang, Kris Konigsfeld, Dan Milliron, Mosur Mohan, Michail Romesis, Glenn Reinman, Jason Cong	Microarchitecture evaluation with floorplanning and interconnect pipelining.	ASP-DAC	2005	DBLP DOI BibTeX RDF
38	Pramod Ramarao, Akhilesh Tyagi	An Adiabatic Framework for a Low Energy µ-Architecture & Compiler.	Interaction between Compilers and Computer Architectures	2003	DBLP DOI BibTeX RDF
36	Heon-Mo Koo, Prabhat Mishra 0001, Jayanta Bhadra, Magdy S. Abadir	Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study.	MTV	2006	DBLP DOI BibTeX RDF
34	Dmitry G. Korzun, Andrei V. Gurtov	A local equilibrium model for P2P resource ranking.	SIGMETRICS Perform. Evaluation Rev.	2009	DBLP DOI BibTeX RDF
34	Bill Lin 0001, Jun (Jim) Xu, Nan Hua, Hao Wang 0006, Haiquan (Chuck) Zhao	A randomized interleaved DRAM architecture for the maintenance of exact statistics counters.	SIGMETRICS Perform. Evaluation Rev.	2009	DBLP DOI BibTeX RDF
34	Sipat Triukose, Zhihua Wen, Michael Rabinovich	Content delivery networks: how big is big enough?	SIGMETRICS Perform. Evaluation Rev.	2009	DBLP DOI BibTeX RDF
34	Alma Riska, Erik Riedel	Evaluation of disk-level workloads at different time scales.	SIGMETRICS Perform. Evaluation Rev.	2009	DBLP DOI BibTeX RDF
34	Mathew S. Thoennes, Charles C. Weems	Exploration of the Performance of a Data Mining Application via Hardware Based Monitoring.	J. Supercomput.	2003	DBLP DOI BibTeX RDF	simulation, data mining, performance, monitoring, application, tuning, micro-architecture
32	Faye A. Briggs, Suresh Chittor, Kai Cheng	Micro-architecture techniques in the intel E8870 scalable memory controller.	WMPI	2004	DBLP DOI BibTeX RDF	distributed coherency, transaction flows, scalability, memory latency
31	Eric Schnarr, Mark D. Hill, James R. Larus	Facile: A Language and Compiler for High-Performance Processor Simulators.	PLDI	2001	DBLP DOI BibTeX RDF	micro-architecture simulation, out-of-order processor simulation, partial evaluation, memoization
30	Wai Sum Mong, Jianwen Zhu	A retargetable micro-architecture simulator.	DAC	2003	DBLP DOI BibTeX RDF
30	Chris R. Jesshope, Bing Luo	Micro-Threading: A New Approach to Future RISC.	ACAC	2000	DBLP DOI BibTeX RDF
29	Lucanus J. Simonson, Lei He 0001	Micro-architecture Performance Estimation by Formula.	SAMOS	2005	DBLP DOI BibTeX RDF
29	Lev Kirischian, Irina Terterian, Pil Woo Chun, Vadim Geurkov	Re-Configurable Parallel Stream Processor with Self-Assembling and Self-Restorable Micro-Architecture.	PARELEC	2004	DBLP DOI BibTeX RDF
29	Wonbok Lee, Kimish Patel, Massoud Pedram	B2Sim: : a fast micro-architecture simulator based on basic block characterization.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	basic block, micro-architecture simulation, program behavior
26	Hala A. Farouk, Magdy Saeb	An Improved FPGA Implementation of the Modified Hybrid Hiding Encryption Algorithm (MHHEA) for Data Communication Security.	DATE	2005	DBLP DOI BibTeX RDF
25	David A. Dunn, Wei-Chung Hsu	Instruction Scheduling for the HP PA-8000.	MICRO	1996	DBLP DOI BibTeX RDF	HP PA-8000, instruction polarity cache interfaces, memory dependences, production compiler, scheduling, latency, compiler optimization, instruction scheduling, resource constraints, micro-architecture
24	Antti Evesti, Susanna Pantsar-Syväniemi	Towards micro architecture for security adaptation.	ECSA Companion Volume	2010	DBLP DOI BibTeX RDF	quality, smart space, run-time
24	Eyal Bin, Laurent Fournier	Micro-Architecture Verification for Microprocessors.	MTV	2004	DBLP DOI BibTeX RDF
24	Khushwinder Jasrotia, Jianwen Zhu	Stacked FSMD: A Power Efficient Micro-Architecture for High Level Synthesis.	ISQED	2004	DBLP DOI BibTeX RDF
24	J. H. Jacobs, Augustus K. Uht, R. C. Ord	Modeling the effects of instruction queue loading on a static instruction stream micro-architecture.	MICRO	1988	DBLP BibTeX RDF
23	Shu-Lin Hwang, Feipei Lai	Two Cache Lines Prediction for a Wide-Issue Micro-architecture.	ACSAC	2001	DBLP DOI BibTeX RDF
22	Steven Balensiefer, Lucas Kreger-Stickles, Mark Oskin	An Evaluation Framework and Instruction Set Architecture for Ion-Trap Based Quantum Micro-Architectures.	ISCA	2005	DBLP DOI BibTeX RDF
22	James Burns, Jean-Luc Gaudiot	Quantifying the SMT Layout Overhead-Does SMT Pull Its Weight?	HPCA	2000	DBLP DOI BibTeX RDF	Simultaneous Multi-Threading (SMT)
22	Alina Toma	Joint super-resolution/segmentation approaches for the tomographic images analysis of the bone micro-architecture. (Approches conjointes de super-résolution / segmentation pour l'analyse des images tomographiques de la micro-architecture osseuse).		2016	RDF
21	Liwen Shih	Microprogramming heritage of RISC design.	MICRO	1990	DBLP BibTeX RDF
19	Samarjit Chakraborty, Tulika Mitra, Abhik Roychoudhury, Lothar Thiele	Cache-aware timing analysis of streaming applications.	Real Time Syst.	2009	DBLP DOI BibTeX RDF	Timing analysis, Instruction cache, Streaming applications
19	Douglas Samuel Kirk, Marc Roper, Murray Wood	Identifying and addressing problems in object-oriented framework reuse.	Empir. Softw. Eng.	2007	DBLP DOI BibTeX RDF	Framework reuse, Empirical study, Documentation, Object-oriented frameworks, Qualitative study, Software comprehension
19	Kostas Bousias, Chris R. Jesshope	The Challenges of Massive On-Chip Concurrency.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
18	Friman Sánchez, Esther Salamí, Alex Ramírez, Mateo Valero	Performance Analysis of Sequence Alignment Applications.	IISWC	2006	DBLP DOI BibTeX RDF
18	Carl J. Mauer, Mark D. Hill, David A. Wood 0001	Full-system timing-first simulation.	SIGMETRICS	2002	DBLP DOI BibTeX RDF
18	Victor V. Zyuban, Peter M. Kogge	Optimization of high-performance superscalar architectures for energy efficiency.	ISLPED	2000	DBLP DOI BibTeX RDF
18	Susanna Pantsar-Syväniemi, Eila Ovaska, Susanna Ferrari, Tullio Salmon Cinotti, Guido Zamagni, Luca Roffia, Sandra Mattarozzi, Valerio Nannini	Case Study: Context-Aware Supervision of a Smart Maintenance Process.	SAINT	2011	DBLP DOI BibTeX RDF	adaptation, context-awareness, smart environment, run-time, micro-architecture
18	Rohit Sunkam Ramanujam, Vassos Soteriou, Bill Lin 0001, Li-Shiuan Peh	Design of a High-Throughput Distributed Shared-Buffer NoC Router.	NOCS	2010	DBLP DOI BibTeX RDF	Router micro-architecture, On-chip interconnection networks
18	Siddhesh S. Mhambrey, Lawrence T. Clark, Satendra Kumar Maurya, Krzysztof S. Berezowski	Out-of-order issue logic using sorting networks.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	out-of-order processing, ILP, micro-architecture, issue queue, high speed circuits
18	Thomas Baumann, Doris Schmitt-Landsiedel, Christian Pacha	Architectural assessment of design techniques to improve speed and robustness in embedded microprocessors.	DAC	2009	DBLP DOI BibTeX RDF	variability-aware design, robustness, micro-architecture
18	Tay-Jyi Lin, Shin-Kai Chen, Yu-Ting Kuo, Chih-Wei Liu, Pi-Chen Hsiao	Design and Implementation of a High-Performance and Complexity-Effective VLIW DSP for Multimedia Applications.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	register organization, VLIW, digital signal processor, micro-architecture, instruction encoding
17	Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou 0001	Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning.	ASP-DAC	2007	DBLP DOI BibTeX RDF	graph-based approach, microarchitecture pipelining optimization, throughput-aware floorplanning, block pipelining, interconnect pipelining, graph-based algorithm, mixed integer linear programming, wire pipelining
17	Zhenyu Qi, Matthew M. Ziegler, Stephen V. Kosonocky, Jan M. Rabaey, Mircea R. Stan	Multi-Dimensional Circuit and Micro-Architecture Level Optimization.	ISQED	2007	DBLP DOI BibTeX RDF
17		Intel® XScale® Micro-Architecture.	Encyclopedia of Multimedia	2006	DBLP DOI BibTeX RDF
17	Hala A. Farouk, Magdy Saeb	Design and implementation of a secret key steganographic micro-architecture employing FPGA.	ASP-DAC	2004	DBLP DOI BibTeX RDF
17	Kolin Paul, Parimal Pal Chaudhuri, Dipanwita Roy Chowdhury	Scalable Pipelined Micro-Architecture for Wavelet Transform.	VLSI Design	2000	DBLP DOI BibTeX RDF
17	Umesh Krishnaswamy, Isaac D. Scherson	Micro-Architecture Evaluation Using Performance Vectors.	SIGMETRICS	1996	DBLP DOI BibTeX RDF
17	Forrest Brewer, Daniel Gajski	Knowledge Based Control in Micro-Architecture Design.	DAC	1987	DBLP DOI BibTeX RDF
17	Vangalur S. Alagar, Ralf Lämmel	Three-Tiered Specification of Micro-architectures.	ICFEM	2002	DBLP DOI BibTeX RDF	UML, interaction, formal methods, frameworks, design patterns, reuse, evolution, object-oriented design, micro-architectures
17		A D&T Roundtable: Power Delivery and Distribution.	IEEE Des. Test Comput.	2000	DBLP DOI BibTeX RDF
15	Maria Mushtaq	Software-based Detection and Mitigation of Microarchitectural Attacks on Intel's x86 Architecture. (Mise en oeuvre de mécanismes logiciels pour la détection et la prévention des attaques exploitant la micro-architecture des processeurs Intel x86).		2019	RDF
15	Leszek Siwik, Kamil Wlodarczyk, Mateusz Kluczny	Staged event-driven architecture as a micro-architecture of distributed and pluginable crawling platform.	Comput. Sci.	2013	DBLP DOI BibTeX RDF
14	Yong-Kyu Jung	Fault-recovery Non-FPGA-based Adaptable Computing System Design.	AHS	2007	DBLP DOI BibTeX RDF
13	Donglai Dai, Aniruddha S. Vaidya, Roy Saharoy, Seungjoon Park, Dongkook Park, Hariharan L. Thantry, Ralf Plate, Elmar Maas, Akhilesh Kumar, Mani Azimi	FPGA-based prototyping of a 2D MESH / TORUS on-chip interconnect (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, routing algorithm, on-chip interconnect, router architecture
13	Mohammad Hossein Neishaburi, Zeljko Zilic	Reliability aware NoC router architecture using input channel buffer sharing.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	system on chip, network on chip, virtual channel
13	Ram Srinivasan, Jeanine E. Cook, Olaf M. Lubeck	Performance modeling using Monte Carlo simulation.	IEEE Comput. Archit. Lett.	2006	DBLP DOI BibTeX RDF
13	Avi Mendelson	Memory management challenges in the power-aware computing era.	ISMM	2006	DBLP DOI BibTeX RDF
13	Steve Carr 0001, Soner Önder	A case for a working-set-based memory hierarchy.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	cache design, loop tiling
13	Michael A. Howland, Robert A. Mueller, Philip H. Sweany	Trace scheduling optimization in a retargetable microcode compiler.	MICRO	1987	DBLP DOI BibTeX RDF
12	Håkon Ording Bugge	An evaluation of Intel's core i7 architecture using a comparative approach.	Comput. Sci. Res. Dev.	2009	DBLP DOI BibTeX RDF	SPEC MPI2007, Nehalem, iCore7, Harpertown, Quad-Core, QuickPath Interconnect, Moore’s Law, Benchmarking, Stream, Micro-benchmarks
12	Anmol Mathur, Qi Wang	Power Reduction Techniques and Flows at RTL and System Level.	VLSI Design	2009	DBLP DOI BibTeX RDF
12	Nathan Chong, Samin Ishtiaq	Reasoning about the ARM weakly consistent memory model.	MSPC	2008	DBLP DOI BibTeX RDF	weakly consistent memory model, ARM
12	Ludovic L'Hours	Generating Efficient Custom FPGA Soft-Cores for Control-Dominated Applications.	ASAP	2005	DBLP DOI BibTeX RDF
12	Yong-Joon Park, Gyungho Lee	Repairing return address stack for buffer overflow protection.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	computer architecture, computer security, buffer overflow, intrusion tolerance
12	Alex C.-Y. Chang, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang	G-MAC: An Application-Specific MAC/Co-Processor Synthesizer.	DATE	2003	DBLP DOI BibTeX RDF
12	Stamatis Vassiliadis, Nikitas J. Dimopoulos, Jean-Francois Collard, Arndt Bode	Topic Introduction.	Euro-Par	2003	DBLP DOI BibTeX RDF
12	Hans M. Mulder, P. Stravers	A flexible VLSI core for an adaptable architecture.	MICRO	1989	DBLP DOI BibTeX RDF
11	Maryam Esmaeilian, Hakem Beitollahi	Experimental evaluation of RISC-V micro-architecture against fault injection attack.	Microprocess. Microsystems	2024	DBLP DOI BibTeX RDF
11	Folkert de Ronde, Matti Dreef, Stephan Wong, David Elkouss	Micro-architecture and Control Electronics Simulation of Modular Color Center-Based Quantum Computers.	SAMOS	2023	DBLP DOI BibTeX RDF
11	Xiaoxiao Ma, Fan Yang, Zhan Wang, Ning Kang 0007, Xunjun An	Understanding the Scalability Problem of RNIC Cache at the Micro-architecture Level.	ICC	2023	DBLP DOI BibTeX RDF
11	Giuseppe Maria Sarda, Nimish Shah, Debjyoti Bhattacharjee, Peter Debacker, Marian Verhelst	Optimising GPGPU Execution Through Runtime Micro-Architecture Parameter Analysis.	IISWC	2023	DBLP DOI BibTeX RDF
11	Satyajit Bora, Roy Paily	A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low Power Applications.	IEEE Trans. Circuits Syst. II Express Briefs	2021	DBLP DOI BibTeX RDF
11	Pruthvy Yellu, Landon Buell, Miguel Mark, Michel A. Kinsy, Dongpeng Xu 0001, Qiaoyan Yu	Security Threat Analyses and Attack Models for Approximate Computing Systems: From Hardware and Micro-architecture Perspectives.	ACM Trans. Design Autom. Electr. Syst.	2021	DBLP DOI BibTeX RDF
11	Sumesh Kumar, Fahad Saeed	Communication-avoiding micro-architecture to compute Xcorr scores for peptide identification.	CoRR	2021	DBLP BibTeX RDF
11	Qilin Si, M. Imtiaz Rashid, Benjamin Carrión Schäfer	Micro-architecture Tuning for Dynamic Frequency Scaling in Coarse-Grain Runtime Reconfigurable Arrays with Adaptive Clock Domain Support.	ISVLSI	2021	DBLP DOI BibTeX RDF
11	Sumesh Kumar, Fahad Saeed	Communication-avoiding micro-architecture to compute Xcorr scores for peptide identification.	FPL	2021	DBLP DOI BibTeX RDF
11	Zahra Kazemi, Amin Norollah, Afef Kchaou, Mahdi Fazeli, David Hély, Vincent Beroulle	An In-Depth Vulnerability Analysis of RISC-V Micro-Architecture Against Fault Injection Attack.	DFT	2021	DBLP DOI BibTeX RDF
11	Poulami Das 0005, Christopher A. Pattison, Srilatha Manne, Douglas M. Carmean, Krysta M. Svore, Moinuddin K. Qureshi, Nicolas Delfosse	A Scalable Decoder Micro-architecture for Fault-Tolerant Quantum Computing.	CoRR	2020	DBLP BibTeX RDF
11	Lauren De Meyer, Elke De Mulder, Michael Tunstall	On the Effect of the (Micro)Architecture on the Development of Side-Channel Resistant Software.	IACR Cryptol. ePrint Arch.	2020	DBLP BibTeX RDF
11	Juan Escobedo, Mingjie Lin	DOMIS: Dual-Bank Optimal Micro-Architecture for Iterative Stencils.	FPGA	2020	DBLP DOI BibTeX RDF
11	Liang Zhu, Chao Chen 0022, Zihao Su, Weiguang Chen, Tao Li 0006, Zhibin Yu 0001	BBS: Micro-Architecture Benchmarking Blockchain Systems through Machine Learning and Fuzzy Set.	HPCA	2020	DBLP DOI BibTeX RDF
11	Linda Wang, Alexander Wong	Enabling Computer Vision Driven Assistive Devices for the Visually Impaired via Micro-architecture Design Exploration.	CoRR	2019	DBLP BibTeX RDF
11	Jilin W. J. L. Wang, Fabrizio Lombardi, Xiyun Zhang, Christelle Anaclet, Plamen Ch. Ivanov	Non-equilibrium critical dynamics of bursts in θ and δ rhythms as fundamental characteristic of sleep and wake micro-architecture.	PLoS Comput. Biol.	2019	DBLP DOI BibTeX RDF
11	Andrés Rainiero Hernández Coronado, Wonjun Lee 0003	Are We Referring to the Same x86 64?: Detection of Cache Events in AMD's Zen Micro-architecture.	ICDCS	2019	DBLP DOI BibTeX RDF
11	Khoi Minh Huynh, Tiantian Xu, Ye Wu 0001, Geng Chen 0001, Kim-Han Thung, Haiyong Wu, Weili Lin, Dinggang Shen, Pew-Thian Yap	Probing Brain Micro-architecture by Orientation Distribution Invariant Identification of Diffusion Compartments.	MICCAI (3)	2019	DBLP DOI BibTeX RDF
11	Sraman Choudhury, Srikar Chundury, Subramaniam Kalambur, Dinkar Sitaram	Poster Paper Impact Of Software Stack Version On Micro-architecture.	ICPE Companion	2019	DBLP DOI BibTeX RDF
11	Fang Li, Jinrong Han, Ziyuan Zhu, Dan Meng	Spatial-Temporal Attention Network for Malware Detection Using Micro-architecture Features.	IJCNN	2019	DBLP DOI BibTeX RDF
11	Yu-Zhe Wang, Jingjie Wu, Shi-Hao Chen, Mango Chia-Tso Chao, Chia-Hsiang Yang	Micro-Architecture Optimization for Low-Power Bitcoin Mining ASICs.	VLSI-DAT	2019	DBLP DOI BibTeX RDF
11	Hoda Ahmadinejad, Omid Fatemi	Moving towards grey-box predictive models at micro-architecture level by investigating inherent program characteristics.	IET Comput. Digit. Tech.	2018	DBLP DOI BibTeX RDF
11	Hadi Mardani Kamali, Kimia Zamiri Azar, Shaahin Hessabi	DuCNoC: A High-Throughput FPGA-Based NoC Simulator Using Dual-Clock Lightweight Router Micro-Architecture.	IEEE Trans. Computers	2018	DBLP DOI BibTeX RDF
11	Shun Wang, Xiaojuan Li, Yong Guan, Rui Wang 0024, Jie Zhang 0074	Executable Micro-Architecture Modeling and Automatic Verification of EtherCAT.	SmartWorld/SCALCOM/UIC/ATC/CBDCom/IOP/SCI	2018	DBLP DOI BibTeX RDF
11	Chikun Yuan, Letian Huang, Junshi Wang, Qiang Li 0021	Micro-Architecture Design for Low Overhead Fault Tolerant Network-on-Chip.	ISCAS	2018	DBLP DOI BibTeX RDF
11	P. Harsha	A Novel Micro-Architecture Using a Simplified Logistic Map for Embedded Security.	IEEE Embed. Syst. Lett.	2017	DBLP DOI BibTeX RDF
11	Sander De Pestel, Stijn Eyerman, Lieven Eeckhout	Linear Branch Entropy: Characterizing and Optimizing Branch Behavior in a Micro-Architecture Independent Way.	IEEE Trans. Computers	2017	DBLP DOI BibTeX RDF
11	Zhiguo Liu, Ni Zhang, Qiu Tang, Ningning Song, Zengming Yu, Hongbin Zhang	Saving Energy on Processor Micro-Architecture Level for Big Data Stream Mobile Computing.	DSC	2017	DBLP DOI BibTeX RDF
11	Don Kurian Dennis, Ayushi Priyam, Sukhpreet Singh Virk, Sajal Agrawal, Tanuj Sharma, Arijit Mondal, Kailash Chandra Ray	Single cycle RISC-V micro architecture processor and its FPGA prototype.	ISED	2017	DBLP DOI BibTeX RDF
11	Siyuan Xu, Benjamin Carrión Schäfer	Approximate Reconfigurable Hardware Accelerator: Adapting the Micro-Architecture to Dynamic Workloads.	ICCD	2017	DBLP DOI BibTeX RDF
11	Yun Long Lan, V. Muthukumar	Efficient virtual channel allocator for NoC router micro-architecture.	SoCC	2017	DBLP DOI BibTeX RDF
11	Sam Van den Steen, Stijn Eyerman, Sander De Pestel, Moncef Mechri, Trevor E. Carlson, David Black-Schaffer, Erik Hagersten, Lieven Eeckhout	Analytical Processor Performance and Power Modeling Using Micro-Architecture Independent Characteristics.	IEEE Trans. Computers	2016	DBLP DOI BibTeX RDF
11	Haecheon Kim, Seungmin Lim, Junkee Yoon, Seungjae Baek, Jongmoo Choi, Seong-je Cho	Analysis of micro-architecture resources interference on multicore NUMA systems.	SAC	2016	DBLP DOI BibTeX RDF
11	Meenakshi Sundaram Bhaskaran	Micro-Architecture and Systems Support for Emerging Non-Volatile Memories.		2016	RDF
11	Zakaria Lakhdara, Salah Merniz	A SysML and CLEAN Based Methodology for RISC Processor Micro-Architecture Design.	Int. J. Embed. Real Time Commun. Syst.	2015	DBLP DOI BibTeX RDF