Search results for "microprocessor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
88	Carlos Montemayor, Marie Sullivan, Jen-Tien Yen, Pete Wilson, Richard Evers, K. R. Kishore	The PowerPC 603e microprocessor: an enhanced, low-power, superscalar microprocessor.	ICCD	1995	DBLP DOI BibTeX RDF	PowerPC 603e microprocessor, low-power superscalar microprocessor, portable products, on-chip instruction, cache associativity, bus modes, 120 SPECint92, 105 SPECfp92, die size, software controllable power-down modes, power saving capability, 16 Kbyte, performance evaluation, performance, computer architecture, system design, power consumption, data cache, cache storage, microprocessor chips, frequency, system buses, portable computers, portable computers, transistors, 100 MHz
76	William Lloyd Bircher, Lizy K. John	Complete System Power Estimation: A Trickle-Down Approach Based on Performance Events.	ISPASS	2007	DBLP DOI BibTeX RDF	power sensing hardware, complete system power estimation, microprocessor performance event, microprocessor performance counter, online measurement, complete system power consumption, microprocessor power, on-chip performance event counter, system power consumption estimation, power model
62	Shlomi Dolev, Yinnon A. Haviv	Self-Stabilizing Microprocessor: Analyzing and Overcoming Soft Errors.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Self-stabilization, microprocessor, soft errors, single event upset
57	Junichi Hirase, Shinichi Yoshimura	Faster processing for microprocessor functional ATPG.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	microprocessor functional ATPG, fault coverage improvement, short test pattern, processing speed increase, logic testing, integrated circuit testing, automatic test pattern generation, identification, test pattern generation, functional testing, microprocessor chips, instruction sets, instruction sets, microprocessor tests
57	Matthew Wilding, David A. Greve, Raymond J. Richards, David S. Hardin	Formal Verification of Partition Management for the AAMP7G Microprocessor.	Design and Verification of Microprocessor Systems for High-Assurance Applications	2010	DBLP DOI BibTeX RDF
56	Hyun-Gyu Kim, Hyeong-Cheol Oh	A DSP-Enhanced 32-Bit Embedded Microprocessor.	EUC	2005	DBLP DOI BibTeX RDF	DSP-enhanced microprocessor, hardware address generator, register extension, embedded microprocessor, SIMD
50	Thomas D. Burd, Robert W. Brodersen	Energy efficient CMOS microprocessor design.	HICSS (1)	1995	DBLP DOI BibTeX RDF	energy efficient CMOS microprocessor design, portable electronics, battery weight, battery size, heat dissipation, computation modes, power analysis methodology, energy efficiency quantification, computer architecture, computer architectures, throughput, parallel machines, energy consumption, energy conservation, microprocessor chips, design principles, power dissipation, CMOS digital integrated circuits, integrated circuit modelling, cooling, figures of merit, desktop computers
50	Jaime H. Moreno	Chip-level integration: the new frontier for microprocessor architecture.	SPAA	2006	DBLP DOI BibTeX RDF	chip-level integration, microprocessor architecture
50	Ioannis Panagopoulos, Christos Pavlatos, George K. Papakonstantinou	An Embedded Microprocessor for Intelligent Control.	J. Intell. Robotic Syst.	2005	DBLP DOI BibTeX RDF	embedded systems, logic programming, microprocessor, intelligent control, RISC, declarative programs
50	Seokkee Kim, Soo-Ik Chae	Implementation of a simple 8-bit microprocessor with reversible energy recovery logic.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	clocked power generator (CPG), nMOS reversible energy recovery logic (nRERL), phase scheduling, reversibility breaking, microprocessor
50	Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng	On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set.	VTS	2000	DBLP DOI BibTeX RDF	Microprocessor self-testing, Path delay fault classification, Functionally testable paths, Functional tests, Delay fault testing
50	S. M. Yuen, K. P. Lam	A Knowledge-based Approach for Worst-case Timing Analysis of Microprocessor Systems.	COMPSAC	1995	DBLP DOI BibTeX RDF	Microprocessor Systems Diagnosis, Time Range Reasoning, Knowledge-based Systems
49	Oleg Maslennikow, Juri Shevtshenko, Anatoli Sergyienko	Configurable Microprocessor Array for DSP Applications.	PPAM	2003	DBLP DOI BibTeX RDF
45	David M. Russinoff	A Mechanically Verified Commercial SRT Divider.	Design and Verification of Microprocessor Systems for High-Assurance Applications	2010	DBLP DOI BibTeX RDF
45	Anthony C. J. Fox, Michael J. C. Gordon, Magnus O. Myreen	Specification and Verification of ARM Hardware and Software.	Design and Verification of Microprocessor Systems for High-Assurance Applications	2010	DBLP DOI BibTeX RDF
45	Konrad Slind, Guodong Li, Scott Owens	Compiling Higher Order Logic by Proof.	Design and Verification of Microprocessor Systems for High-Assurance Applications	2010	DBLP DOI BibTeX RDF
45	Michael W. Whalen, David A. Greve, Lucas G. Wagner	Model Checking Information Flow.	Design and Verification of Microprocessor Systems for High-Assurance Applications	2010	DBLP DOI BibTeX RDF
45	Warren A. Hunt Jr., Sol Swords, Jared Davis, Anna Slobodová	Use of Formal Verification at Centaur Technology.	Design and Verification of Microprocessor Systems for High-Assurance Applications	2010	DBLP DOI BibTeX RDF
45	Raymond J. Richards	Modeling and Security Analysis of a Commercial Real-Time Operating System Kernel.	Design and Verification of Microprocessor Systems for High-Assurance Applications	2010	DBLP DOI BibTeX RDF
45	Torben Amtoft, John Hatcliff, Edwin Rodríguez, Robby, Jonathan Hoag, David A. Greve	Specification and Checking of Software Contracts for Conditional Information Flow.	Design and Verification of Microprocessor Systems for High-Assurance Applications	2010	DBLP DOI BibTeX RDF
45	Sally Browning, Philip Weaver	Designing Tunable, Verifiable Cryptographic Hardware Using Cryptol.	Design and Verification of Microprocessor Systems for High-Assurance Applications	2010	DBLP DOI BibTeX RDF
45	David A. Greve	Information Security Modeling and Analysis.	Design and Verification of Microprocessor Systems for High-Assurance Applications	2010	DBLP DOI BibTeX RDF
45	Gerwin Klein, Thomas Sewell, Simon Winwood	Refinement in the Formal Verification of the seL4 Microkernel.	Design and Verification of Microprocessor Systems for High-Assurance Applications	2010	DBLP DOI BibTeX RDF
45	Panagiotis Manolios, Sudarshan K. Srinivasan	Verifying Pipelines with BAT.	Design and Verification of Microprocessor Systems for High-Assurance Applications	2010	DBLP DOI BibTeX RDF
45	Matt Kaufmann, J Strother Moore	ACL2 and Its Applications to Digital System Verification.	Design and Verification of Microprocessor Systems for High-Assurance Applications	2010	DBLP DOI BibTeX RDF
44	Murat Aydos, Tugrul Yanik, Çetin Kaya Koç	An High-Speed ECC-based Wireless Authentication Protocol on an ARM Microprocessor.	ACSAC	2000	DBLP DOI BibTeX RDF	high-speed ECC-based wireless authentication, ARM microprocessor, elliptic curve digital signature algorithm, ARM7TDMI processor, core processor, 80 MHz, 160 bit, mobile computing, elliptic curve cryptography, public key cryptography, software libraries, software library, authorisation, microprocessor chips, message authentication, portable computers, ECDSA, 32 bit, wireless applications
44	Shannon V. Morton, Sam S. Appleton, Michael J. Liebelt	ECSTAC: a fast asynchronous microprocessor.	ASYNC	1995	DBLP DOI BibTeX RDF	asynchronous microprocessor, ECSTAC, two-phase communication, processor pipeline, register tagging, branch techniques, block simulation, caches, logic design, asynchronous circuits, microprocessor chips
44	Noriyuki Ito, Hideaki Katagiri, Ryoichi Yamashita, Hiroshi Ikeda, Hiroyuki Sugiyama, Hiroaki Komatsu, Yoshiyasu Tanamura, Akihiro Yoshitake, Kazuhiro Nonomura, Kinya Ishizaka, Hiroaki Adachi, Yutaka Mori, Yutaka Isoda, Yaroku Sugiyama	Diagonal routing in high performance microprocessor design.	ASP-DAC	2006	DBLP DOI BibTeX RDF	diagonal routing, manhattan routing, microprocessor
44	Rodrigo Possamai Bastos, Fernanda Lima Kastensmidt, Ricardo Reis 0001	Design at high level of a robust 8-bit microprocessor to soft errors by using only standard gates.	SBCCI	2006	DBLP DOI BibTeX RDF	fault-tolerant microprocessor, soft errors, single event upsets, single event transients
44	Seokkee Kim, Soo-Ik Chae	Complexity reduction in an nRERL microprocessor.	ISLPED	2005	DBLP DOI BibTeX RDF	buffer skipping, clocked power generator (CPG), nMOS reversible energy recovery logic (nRERL), reversibility breaking, microprocessor, complexity reduction
44	Sumit Gupta, Nick Savoiu, Nikil D. Dutt, Rajesh K. Gupta 0001, Alexandru Nicolau, Timothy Kam, Michael Kishinevsky, Shai Rotem	Coordinated transformations for high-level synthesis of high performance microprocessor blocks.	DAC	2002	DBLP DOI BibTeX RDF	high-level synthesis, microprocessor design
43	Fu-Ching Yang, Wen-Kai Huang, Jing-Kun Zhong, Ing-Jer Huang	Automatic Verification of External Interrupt Behaviors for Microprocessor Design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
43	Jesse Zhixi Fang	A Generation Ahead of Microprocessor: Where Software Can Drive uArchitecture To?	Asia-Pacific Computer Systems Architecture Conference	2004	DBLP DOI BibTeX RDF
43	Mehdi M. Mechaik	Effects of Package Stackups on Microprocessor Performance.	ISQED	2000	DBLP DOI BibTeX RDF
43	Philip Heng Wai Leong, P. K. Tsang, T. K. Lee	A FPGA Based Forth Microprocessor.	FCCM	1998	DBLP DOI BibTeX RDF
43	Pramod V. Argade, David K. Charles, Craig Taylor	A Technique for Monitoring Run-Time Dynamics of an Operating System and a Microprocessor Executing User Applications.	ASPLOS	1994	DBLP DOI BibTeX RDF
43	Tony Zingale	Distributed processing with iAPX 186 microprocessor systems.	AFIPS National Computer Conference	1982	DBLP DOI BibTeX RDF
38	S. Srivastava, S. C. Bose, B. P. Mathur, Arti Noor, Raj Singh, A. S. Mandal, K. Prabhakaran, Arindam Karmakar, Chandra Shekhar 0001, Sudhir Kumar, Amit K. Agarwal	Evolution of Architectural Concepts and Design Methods of Microprocessors.	VLSI Design	1998	DBLP DOI BibTeX RDF	Microprocessor Evolution, Synthesis, VHDL, Microprocessor Design
38	Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante	A genetic algorithm-based system for generating test programs for microprocessor IP cores.	ICTAI	2000	DBLP DOI BibTeX RDF	industrial property, genetic algorithm based system, test program generation, microprocessor IP cores, digital systems design trend, design-and-reuse paradigm, intellectual property cores, encrypted gate-level netlist, testability problems, automatic approach, processor cores, fault coverage figures, random approach, genetic algorithms, genetic algorithms, microprocessor chips, automatic test software, test program, electronic engineering computing
38	Christian Piguet, Thierry Schneider, Jean-Marc Masgonty, Claude Arm, Serge Durand, M. Stegers	Low-Power Embedded Microprocessor Design.	EUROMICRO	1996	DBLP DOI BibTeX RDF	low-power embedded microprocessor design, low-power RISC-like architectures, gated clock techniques, power savings, microprocessor chips, CMOS technology, hierarchical memories, clock cycles
38	Hong Hao, Kanti Bhabuthmal	Clock controller design in SuperSPARC II microprocessor.	ICCD	1995	DBLP DOI BibTeX RDF	SuperSPARC II, internal clock pulses, internal clock, free running mode, IEEE 1149.1 interface, microprocessor, clocks, microprocessor chips, clock controller
38	Charles P. Roth, Frank E. Levine, Edward H. Welbon	Performance monitoring on the PowerPC 604 microprocessor.	ICCD	1995	DBLP DOI BibTeX RDF	PowerPC 604 microprocessor, multichip processors, Groupe Bull, performance evaluation, integrated circuit testing, workstations, performance monitoring, microprocessor chips, PCs, Microsoft, IBM, computer testing, Apple, Motorola
38	Steven Wallace, Nirav Dagli, Nader Bagherzadeh	Design and implementation of a 100 MHz centralized instruction window for a superscalar microprocessor.	ICCD	1995	DBLP DOI BibTeX RDF	centralized instruction window, four instructions per cycle, compact layout, full-custom design, computer architecture, microprocessor chips, superscalar architecture, superscalar microprocessor, out-of-order issue, 100 MHz
38	Veljko M. Milutinovic, David A. Fura, Walter A. Helbig	Pipeline Design Tradeoffs in a 32-bit Gallium Arsenide Microprocessor.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	instruction pipeline design, single-chip GaAs microprocessor, application-related parameters, pipelined memory pipeline, III-V semiconductors, performance evaluation, microprocessor chips, instruction sets, 32 bit, GaAs, gallium arsenide
38	Veljko M. Milutinovic, Mark Bettinger, Walter A. Helbig	Multiplier/Shifter Design Tradeoffs in a 32-bit Microprocessor.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	full barrel shifter, large register file, GaAs microprocessor, logic design, microprocessors, microprocessor chips, design tradeoffs, 32 bits, single chip, bit-serial multiplier
38	Robert P. Roesser	Two-Dimensional Microprocessor Pipelines for Image Processing.	IEEE Trans. Computers	1978	DBLP DOI BibTeX RDF	two-dimensional pipeline, Digital image processor, microprocessor array, microprocessor pipeline, space-domain processing, state-space processing, parallel processors, microcomputers
38	Cecilia Metra, Stefano Di Francescantonio, Bruno Riccò, T. M. Mak	Evaluation of Clock Distribution Networks' Most Likely Faults and Produced Effects.	DFT	2001	DBLP DOI BibTeX RDF	clock faults, testing, microprocessor, Clock distribution network
37	Rupesh S. Shelar, Marek Patyra	Impact of local interconnects on timing and power in a high performance microprocessor.	ISPD	2010	DBLP DOI BibTeX RDF	CAD, delay, interconnects, power, microprocessor
37	Noriyuki Ito, Akira Kanuma, Daisuke Maruyama, Hitoshi Yamanaka, Tsuyoshi Mochizuki, Osamu Sugawara, Chihiro Endoh, Masahiro Yanagida, Takeshi Kono, Yutaka Isoda, Kazunobu Adachi, Takahisa Hiraide, Shigeru Nagasawa, Yaroku Sugiyama, Eizo Ninoi	Delay defect screening for a 2.16GHz SPARC64 microprocessor.	ASP-DAC	2006	DBLP DOI BibTeX RDF	delay defect, microprocessor, screening, at-speed
37	Ernesto Sánchez 0001, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante	Automatic generation of test sets for SBST of microprocessor IP cores.	SBCCI	2005	DBLP DOI BibTeX RDF	FPGA, hardware accelerator, automatic test generation, pipelined architectures, microprocessor test, test programs
37	Mohammad H. Tehranipour, Mehrdad Nourani	Signal Integrity Loss in SoC's Interconnects: A Diagnosis Approach Using Embedded Microprocessor.	ITC	2002	DBLP DOI BibTeX RDF	Embedded Microprocessor, Integrity Loss, System-on-Chip, Diagnosis, Test Pattern Generation, Signal Integrity, Interconnect Testing, Noise Detection
37	Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Paula K. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, Nobuo Kojima, Ohsang Kwon, Kyung T. Lee, David Meltzer, Kevin J. Nowka, J. Park, J. Peter, Joel Silberman, Osamu Takahashi, Paul Villarrubia	"Timing closure by design, " a high frequency microprocessor design methodology.	DAC	2000	DBLP DOI BibTeX RDF	chip integration, dynamic circuits0, CAD, methodology, microprocessor, timing analysis, PLA, timing closure
37	John Matthews, Byron Cook, John Launchbury	Microprocessor Specification in Hawk.	ICCL	1998	DBLP DOI BibTeX RDF	Microprocessor Verification, Domain-Specific Language, Functional Language, Hardware Verification
37	Michael Nicolaidis	Efficient UBIST implementation for microprocessor sequencing parts.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	strongly code disjoint checkers, signature analyser, UBIST, microprocessor sequencing part, BIST, LFSR, self-checking circuits, totally self-checking circuits
37	Fu-Ching Yang, Jing-Kun Zhong, Ing-Jer Huang	Verifying external interrupts of embedded microprocessor in SoC with on-chip bus.	ICCAD	2008	DBLP DOI BibTeX RDF
37	Masatoshi Shima 0001	The Birth, Evolution and Future of the Microprocessor.	CIT	2005	DBLP DOI BibTeX RDF
37	Seokkee Kim, Jun-Ho Kwon, Soo-Ik Chae	An 8-b nRERL microprocessor for ultra-low-energy applications.	ASP-DAC	2001	DBLP DOI BibTeX RDF
37	Bartomeu Alorda, Ivan de Paúl, Jaume Segura 0001, T. Miller	On-Line Current Testing for a Microprocessor Based Application with an Off-Chip Sensor.	IOLTW	2000	DBLP DOI BibTeX RDF
37	Bill Huston	Practical CMOS microprocessor systems.	AFIPS National Computer Conference	1982	DBLP DOI BibTeX RDF
32	Tom Thomas, Brian W. Anthony	Area, Performance, and Yield Implications of Redundancy in On-Chip Caches.	ICCD	1999	DBLP DOI BibTeX RDF	cache, redundancy, microprocessor, yield, SRAM, yield enhancement, microprocessor design, embedded SRAM
32	Sam S. Appleton, Shannon V. Morton, Michael J. Liebelt	Two-Phase Asynchronous Pipeline Control.	ASYNC	1997	DBLP DOI BibTeX RDF	two-phase asynchronous pipeline control, bounded-delay model, prototype microprocessor, microprocessor chips
32	James O. Bondi, Ashwini K. Nanda, Simonjit Dutta	Integrating a Misprediction Recovery Cache (MRC) into a Superscalar Pipeline.	MICRO	1996	DBLP DOI BibTeX RDF	branch target buffer technology, deep pipelines, misprediction recovery cache integration, performance loss, residual misprediction penalty, superscalar pipeline, microprocessor chips, microprocessor designs, CISC, multiple instructions
32	Thomas W. Lynch, Ashraf Ahmed, Michael J. Schulte, Thomas K. Callaway, Robert Tisdale	The K5 transcendental functions.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	K5 transcendental functions, AMD x86 compatible superscalar microprocessor, multi-level development cycle, design schedule, table-driven reductions, multiprecision arithmetic operations, encoding, polynomials, floating point arithmetic, microprocessor chips, approximation theory, polynomial approximations
32	Michael S. Allen, W. Kurt Lewchuk, J. D. Coddington	A high performance bus and cache controller for PowerPC multiprocessing systems.	ICCD	1995	DBLP DOI BibTeX RDF	high performance bus, cache controller, PowerPC 620 microprocessor, system bus interface, ECC protected, server-class systems, physical address bus, data bus, address transfer rates, address snoop response, direct cache-to-cache data transfers, 2 GByte/s, 133 MHz, 128 MB, performance evaluation, pipelining, multiprocessing systems, multiprocessing systems, pipeline processing, cache storage, microprocessor chips, coprocessors, cache coherency protocol, data transfer, PowerPC, system buses, co-processor
32	Louis Monier, Ramsey W. Haddad, Jeremy Dion	Recursive layout generation.	ARVLSI	1995	DBLP DOI BibTeX RDF	BiCMOS digital integrated circuits, recursive layout generation, layout directives, netlist description, hand-drawn layout, synthesized layout, overall layout, dense VLSI, VLSI, logic CAD, circuit layout CAD, microprocessor chips, microprocessor chips, VLSI chips, seamless integration
32	Yatin Vasant Hoskote, Jacob A. Abraham, Donald S. Fussell	Automated verification of temporal properties specified as state machines in VHDL.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	automated verification methodology, correctness specifications, Viper microprocessor, Mealy FSM, compatible states, formal specification, formal verification, high level synthesis, finite state machines, VHDL, sequential circuits, state machines, hardware description languages, microprocessor chips, synchronous sequential circuit, temporal properties, liveness properties
32	O. A. Petlin, Stephen B. Furber	Scan testing of micropipelines.	VTS	1995	DBLP DOI BibTeX RDF	asynchronous VLSI circuit design, AMULET1 microprocessor, scan test technique, data processing blocks, combinational processing logic, state holding elements, test generation techniques, VLSI, logic testing, delays, integrated circuit testing, design for testability, logic design, asynchronous circuits, fault location, integrated circuit design, microprocessor chips, delay faults, boundary scan testing, computer testing, test patterns, single stuck-at faults, micropipelines
31	Pinkesh J. Shah, Yoni Aizik, Muhammad K. Mhameed, Gila Kamhi	Challenges and methodologies for efficient power budgeting across the die.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	simulation, performance, energy-efficient, management, power, microprocessor, budget
31	Ernesto Sánchez 0001, Matteo Sonza Reorda, Giovanni Squillero	Efficient Techniques for Automatic Verification-Oriented Test Set Optimization.	Int. J. Parallel Program.	2006	DBLP DOI BibTeX RDF	test-set optimization, evolutionary algorithm, Validation, microprocessor
31	Ed Grochowski, David Ayers, Vivek Tiwari	Microarchitectural Simulation and Control of di/dt-induced Power Supply Voltage Variation.	HPCA	2002	DBLP DOI BibTeX RDF	Power delivery, supply voltage drop, simulation, microprocessor, inductive noise, di/dt
31	Victor S. Foster	MIDAS: A MID-level language for microprocessors.	ACM Annual Conference (2)	1978	DBLP DOI BibTeX RDF	Microprocessor languages, Mid-level languages, Languages, Microprocessors, MIDAS
31	Charles F. Webb	IBM z10: The Next-Generation Mainframe Microprocessor.	IEEE Micro	2008	DBLP DOI BibTeX RDF	high-frequency design, decimal floating-point, reliability, pipeline, microprocessor, branch prediction, accelerators, symmetric multiprocessor (SMP), mainframe, Hot Chips 19
31	Da Wang, Yu Hu 0001, Huawei Li 0001, Xiaowei Li 0001	Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor.	J. Comput. Sci. Technol.	2008	DBLP DOI BibTeX RDF	microprocessor design-for-testability, built-in self-test, test generation, at-speed testing
31	Desta Tadesse, R. Iris Bahar, Joel Grodstein	Fast Measurement of the "Non-Deterministic Zone" in Microprocessor Debug Using Maximum Likelihood Estimation.	VTS	2008	DBLP DOI BibTeX RDF	Microprocessor Diagnosis, Pass/Fail Region, Maximum Likelihood Estimation, Silicon Debug
31	Fu-Ching Yang, Ing-Jer Huang	An Embedded Low Power/Cost 16-Bit Data/Instruction Microprocessor Compatible with ARM7 Software Tools.	ASP-DAC	2007	DBLP DOI BibTeX RDF	16 bit, ARM7 software tools, THUMB instruction set microprocessor, short-precision computing
31	Wei Li, Daniel Blakely, Scott Van Sooy, Keven Dunn, David Kidd, Robert Rogenmoser, Dian Zhou	LVS verification across multiple power domains for a quad-core microprocessor.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	LVS, multi-core microprocessor, physical verification
31	Koichi Sato, Brian L. Evans, J. K. Aggarwal	Designing an Embedded Video Processing Camera Using a 16-bit Microprocessor for a Surveillance System.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	temporal spatio-velocity transform, embedded system, interaction, tracking, video, recognition, microprocessor, surveillance, DRAM, velocity, Ptolemy
31	Eric S. Fetzer	Using Adaptive Circuits to Mitigate Process Variations in a Microprocessor Design.	IEEE Des. Test Comput.	2006	DBLP DOI BibTeX RDF	dual core, Itanium microprocessor, Montecito, adaptive circuits, cache safe technology, active clock deskew, process variation, power measurement
31	Yue Luo, Lizy Kurian John, Lieven Eeckhout	SMA: A Self-Monitored Adaptive Cache Warm-Up Scheme for Microprocessor Simulation.	Int. J. Parallel Program.	2005	DBLP DOI BibTeX RDF	Microprocessor simulation, cache warm-up, simulation time reduction, sampling
31	Luca Benini, Francesco Menichelli, Mauro Olivieri	A Class of Code Compression Schemes for Reducing Power Consumption in Embedded Microprocessor Systems.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	Microprocessor/microcomputer applications, low-power design, code compression
31	Fadi Busaba, Timothy J. Slegel, Steven R. Carlough, Christopher A. Krygowski, John G. Rell	The design of the fixed point unit for the z990 microprocessor.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	superscalar FXU, microprocessor
31	Mark D. Aagaard, Byron Cook, Nancy A. Day, Robert B. Jones	A framework for superscalar microprocessor correctness statements.	Int. J. Softw. Tools Technol. Transf.	2003	DBLP DOI BibTeX RDF	Microprocessor correctness, Commuting diagrams, Formal verification, Pipelines
31	Nguyen Quang Trung, Artur Kokoszka, Krystyna Siekierska, Adam Pawlak, Dariusz Obrebski, Norbert Lugowski	Organization of a Microprocessor Design Process Using Internet-Based Interoperable Workflows.	ISQED	2002	DBLP DOI BibTeX RDF	Virtual Component, Interoperability, Workflow, VHDL, IP, Microprocessor, Microcontroller, Collaborative Engineering
31	Yuichiro Takamizawa, Kouhei Nadehara, Max Boegli, Masao Ikekawa, Ichiro Kuroda	MPEG-2 AAC 5.1-Channel Decoder Software for a Low-Power Embedded RISC Microprocessor.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	microprocessor, decoder, MPEG, AAC
31	Stanislav Polonsky, Moyra K. McManus, Daniel R. Knebel, Steve Steen, Pia N. Sanda	Non-invasive timing analysis of IBM G6 microprocessor L1 cache using picosecond imaging circuit analysis.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	imaging circuit analysis, IBM G6 microprocessor, non-invasive backside timing, Picosecond Imaging Circuit Analysis, waveform extraction, integrated circuit testing, timing analysis, race condition, circuit switching, integrated memory circuits, hazards and race conditions, L1 cache
31	Nandu Tendolkar, Robert F. Molyneaux, Carol Pyron, Rajesh Raina	At-Speed Testing of Delay Faults for Motorola's MPC7400, a PowerPC(tm) Microprocessor.	VTS	2000	DBLP DOI BibTeX RDF	delay testing, at-speed testing, microprocessor testing
31	Erik A. McShane, Krishna Shenai, Leon Alkalai, E. Kolawa, Victor Boyadzhyan, Brent R. Blaes, Wai-Chi Fang	Monolithic Microprocessor and RF Transceiver in 0.25-micron FDSOI CMOS.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF	Mixed-signal VLSI, VLSI circuits process for mixed-signal VLSI in a die size measuring 2.2 mm x 2.2 mm, low-power, microprocessor, RF
31	Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda	EXFI: a low-cost fault injection system for embedded microprocessor-based boards.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	microprocessor systems, software-implemented fault injection, trace exception mode, fault injection, fault coverage
31	Marc Renaudin, Pascal Vivet, Frédéric Robin	ASPRO-216: A Standard-Cell Q.D.I. 16-Bit RISC Asynchronous Microprocessor.	ASYNC	1998	DBLP DOI BibTeX RDF	asynchronous microprocessor, quasi-delay-insensitive circuits, standard-cell asynchronous design
31	Kåre Tais Christensen, Peter Jensen, Peter Korger, Jens Sparsø	The Design of an Asynchronous TinyRISCTM TR4101 Microprocessor Core.	ASYNC	1998	DBLP DOI BibTeX RDF	Asynchronous circuits and systems, low-power, microprocessor design
31	Daniel Audet, Steve Masson, Yvon Savaria	Reducing Fault Sensitivity of Microprocessor-Based Systems by Modifying Workload Structure.	DFT	1998	DBLP DOI BibTeX RDF	bit flip, fault-tolerance, memory, microprocessor, fault injection, software fault-tolerance, transient faults
31	Toshihiro Hattori, Yusuke Nitta, Mitsuho Seki, Susumu Narita, Kunio Uchiyama, Tsuyoshi Takahashi, Ryuichi Satomura	Design Methodology of a 200MHz Superscalar Microprocessor: SH-4.	DAC	1998	DBLP DOI BibTeX RDF	verification, timing, design methodology, microprocessor
31	Bogdan Kasztenny, Eugeniusz Rosolowski	A digital protective relay as a real-time microprocessor system.	ECBS	1997	DBLP DOI BibTeX RDF	power system protection, digital protective relay, real-time microprocessor system, protection system, hardware, power system, software structures
31	D. L. Grundy, M. Bozic, John V. Hatfield	Development of an Analogue Microprocessor.	VLSI Design	1997	DBLP DOI BibTeX RDF	Analogue array, Analogue microprocessor, Analogue signal processing, Programmable Logarithmic, Instruction set
31	Po-Ching Hsu, Sying-Jyan Wang	Testing And Diagnosis Of Board Interconnects In Microprocessor-Based Systems.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	multiple-board system, bus emulator, wiring interconnect, testing, fault detection, diagnosis, microprocessor, printed circuit board, printed circuit testing, hierarchical testing
31	Suresh Rajgopal	Challenges in Low Power Microprocessor Design.	VLSI Design	1996	DBLP DOI BibTeX RDF	power benchmarks, latch power, idle power, active power, clock enabling, max power, thermal power, transient power, low-power, clock gating, microprocessor design, di/dt
31	Alexander Dalal, Lavi Lev, Sundari Mitra	Design of an efficient power distribution network for the UltraSPARC-I microprocessor.	ICCD	1995	DBLP DOI BibTeX RDF	computer power supplies, UltraSPARC-I, simulation method, exact layout locations, excessive voltage drop, floorplanning constraints, power interconnections, reduced time-to-market, circuit analysis computing, circuit layout CAD, microprocessor chips, electromigration, CAD tools, power distribution network
31	Francis Y. L. Chin, Francis Wu	A microprocessor-based optical character recognition check reader.	ICDAR	1995	DBLP DOI BibTeX RDF	microprocessor-based optical character recognition check reader, Magnetic Ink Character Recognition, check reader, lens system, colour image, hardware limitations, optical character recognition, floating point arithmetics, recognition algorithm, software solution
31	Lei Wang 0011, Hongyi Lu, Kui Dai, Zhiying Wang 0003	TengYue-1TengYue: In Chinese means jump over.: A High Performance Embedded SoC.	Asia-Pacific Computer Systems Architecture Conference	2004	DBLP DOI BibTeX RDF
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