Search results for "microprocessors"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
59	Bernard J. Carey, George F. MacLachlan	Automated design based upon Microprogrammable Bit Slice Microprocessors.	Design Automation and Microprocessors	1977	DBLP BibTeX RDF
55	Masatoshi Shima 0001	The Birth, Evolution and Future of the Microprocessor.	CIT	2005	DBLP DOI BibTeX RDF
52	Anthony C. J. Fox, Neal A. Harman	Algebraic Models of Correctness for Microprocessors.	Formal Aspects Comput.	2000	DBLP DOI BibTeX RDF	Formal Verification, Microprocessors, Algebraic Models
49	Corinna G. Lee, Derek J. DeVries	Initial Results on the Performance and Cost of Vector Microprocessors.	MICRO	1997	DBLP DOI BibTeX RDF
47	Uwe Brinkschulte, Mathias Pacher	A Control Theory Approach to Improve the Real-Time Capability of Multi-Threaded Microprocessors.	ISORC	2008	DBLP DOI BibTeX RDF	Control theory in high-end microprocessors, real-time microprocessors, IPC rate
45	Yedidya Hilewitz, Ruby B. Lee	Fast Bit Gather, Bit Scatter and Bit Permutation Instructions for Commodity Microprocessors.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	Bit scatter, Bit gather, Parallel deposit, Unpack, Algorithm acceleration, Bioinformatics, Compression, Pattern matching, Steganography, Microprocessors, Permutations, Pack, Instruction set architecture, Cryptology, ISA, Parallel extract, Bit manipulations
44	William M. van Cleemput, John C. Foster, Donald C. S. Allison (eds.)	Proceedings of the Symposium on Design Automation and Microprocessors, Palo Alto, California, February 24-25, 1977.	Design Automation and Microprocessors	1977	DBLP BibTeX RDF
44	Robert I. Gardner	State of the implementation of SARA.	Design Automation and Microprocessors	1977	DBLP BibTeX RDF
44	John Grason	Design aids and hardware testing of microprocessor system circuit packs.	Design Automation and Microprocessors	1977	DBLP BibTeX RDF
44	W. Werner, W. Minnick	User requirements for digital design verification simulators.	Design Automation and Microprocessors	1977	DBLP BibTeX RDF
44	William T. Overman, Gerald Estrin	Developing a SARA building block - the 8080.	Design Automation and Microprocessors	1977	DBLP BibTeX RDF
44	Will Sherwood	Simulation hierarchy for microprocessor design.	Design Automation and Microprocessors	1977	DBLP BibTeX RDF
44	Charles W. Rose	N.mPc: An adaptable software system to support the development of microprocessor-based systems.	Design Automation and Microprocessors	1977	DBLP BibTeX RDF
44	Lawrence A. O'Neill	Computer aids for the design of manufacturable microcomputer-based systems.	Design Automation and Microprocessors	1977	DBLP BibTeX RDF
44	Todd J. Wagner	Verification of hardware designs thru symbolic manipulation.	Design Automation and Microprocessors	1977	DBLP BibTeX RDF
44	B. A. Prasad	Modelling techniques for dynamic logic and test pattern generation of a microprocessor.	Design Automation and Microprocessors	1977	DBLP BibTeX RDF
44	Robert I. Gardner	Multi-level modeling in SARA.	Design Automation and Microprocessors	1977	DBLP BibTeX RDF
44	John Teets, Charles W. Rose, Edward J. McCluskey	Panel Discussions.	Design Automation and Microprocessors	1977	DBLP BibTeX RDF
44	Will Sherwood	PLATO - PLA Translator/Optimizer - "a ROM is a PLA in no uncertain terms.".	Design Automation and Microprocessors	1977	DBLP BibTeX RDF
44	Rami R. Razouk, Gerald Estrin	The graph model of behavior simulator.	Design Automation and Microprocessors	1977	DBLP BibTeX RDF
44	R. J. Smith II, M. N. Matelan	Practical considerations in implementing a real-time controller design automation system.	Design Automation and Microprocessors	1977	DBLP BibTeX RDF
44	Ivan M. Campos, Gerald Estrin	Specialization of SARA for software synthesis.	Design Automation and Microprocessors	1977	DBLP BibTeX RDF
44	Gerald Estrin	Modeling for synthesis - the gap between intent and behavior.	Design Automation and Microprocessors	1977	DBLP BibTeX RDF
44	Will Sherwood	Some applications of the Stanford University Drawing System for LSI microprocessor - "a picture is worth a thousand bytes.".	Design Automation and Microprocessors	1977	DBLP BibTeX RDF
44	Hoo-Min D. Toong	Automatic design of multiprocessor microprocessor systems.	Design Automation and Microprocessors	1977	DBLP BibTeX RDF
44	Paul J. Drongowski	Capability requirements in a multimicro processor, hardware/software simulation environment.	Design Automation and Microprocessors	1977	DBLP BibTeX RDF
44	Neal A. Harman	Algebraic Models of Simultaneous Multithreaded and Multi-core Processors.	CALCO	2007	DBLP DOI BibTeX RDF	many-sorted algebra, verification, microprocessors, correctness, threaded
42	Antonio González 0001	Key Microarchitectural Innovations for Future Microprocessors.	ARCS	2009	DBLP DOI BibTeX RDF
42	Todd J. Foster, Dennis L. Lastor, Padmaraj Singh	First Silicon Functional Validation and Debug of Multicore Microprocessors.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
42	Jianfeng An, Xiaoya Fan, Shengbing Zhang, Danghui Wang, Yi Wang 0016	VMSIM: Virtual Machine Based a Full System Simulation Platform for Microprocessors' Functional Verification.	ITNG	2006	DBLP DOI BibTeX RDF
42	Norman P. Jouppi	The Future Evolution of High-Performance Microprocessors.	MICRO	2005	DBLP DOI BibTeX RDF
42	Miroslav N. Velev	Automatic Abstraction of Memories in the Formal Verification of Superscalar Microprocessors.	TACAS	2001	DBLP DOI BibTeX RDF
42	Rajesh Kannah, C. P. Ravikumar	Functional Testing of Microprocessors with Graded Fault Coverage.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF
42	S. Srivastava, S. C. Bose, B. P. Mathur, Arti Noor, Raj Singh, A. S. Mandal, K. Prabhakaran, Arindam Karmakar, Chandra Shekhar 0001, Sudhir Kumar, Amit K. Agarwal	Evolution of Architectural Concepts and Design Methods of Microprocessors.	VLSI Design	1998	DBLP DOI BibTeX RDF	Microprocessor Evolution, Synthesis, VHDL, Microprocessor Design
41	Philip Heidelberger, M. Seetha Lakshmi	A Performance Comparison of Multi-Micro and Mainframe Database Architectures.	SIGMETRICS	1987	DBLP DOI BibTeX RDF
40	Seongbae Park, SangMin Shim, Soo-Mook Moon	Evaluation of Scheduling Techniques on a SPARC-based VLIW Testbed.	MICRO	1997	DBLP DOI BibTeX RDF	SPARC-based VLIW testbed, VLIW microprocessors, Very Long Instruction Word microprocessors, all-path speculation, gcc-generated optimized SPARC code, high-performance VLIW code, nongreedy enhanced pipeline scheduling, nonspeculative operations, profile-based all-path speculation, restricted speculative loads, scheduling compiler, speculative operations, trace-based speculation, performance, compiler, computer architecture, parallel machines, software pipelining, loop unrolling, renaming, memory disambiguation, copies, scheduling techniques
38	Yiu-Hing Chan, Prabhakar Kudva, Lisa B. Lacey, Gregory A. Northrop, Thomas E. Rosser	Physical synthesis methodology for high performance microprocessors.	DAC	2003	DBLP DOI BibTeX RDF	synthesis, microprocessors, high-performance
38	John D. Bunda, Donald S. Fussell, William C. Athas	Energy-efficient instruction set architecture for CMOS microprocessors.	HICSS (1)	1995	DBLP DOI BibTeX RDF	energy-efficient instruction set architecture, CMOS microprocessors, portable battery-based applications, performance-driven designs, processor architecture tradeoffs, program encoding size, instruction set richness, energy cost, speculative instruction fetching, execution resources, instruction-level parallel machines, multiple-path instruction fetching, high execution bandwidth, power management, microprocessor chips, instruction sets, power dissipation, CMOS digital integrated circuits, reduced instruction set computing, cooling, design constraint, instruction delivery, code density
35	DiaaEldin Khalil, Yehea I. Ismail	A global interconnect link design for many-core microprocessors.	IFMT	2008	DBLP DOI BibTeX RDF	interconnect, link, bus, repeater insertion
35	Jason D. Lee, Praveen Bhojwani, Rabi N. Mahapatra	A Safety Analysis Framework for COTS Microprocessors in Safety-Critical Applications.	HASE	2007	DBLP DOI BibTeX RDF
35	Norman P. Jouppi	The Future Evolution of High-Performance Microprocessors.	HiPC	2004	DBLP DOI BibTeX RDF
35	Jianfeng An, Xiaoya Fan, Shengbing Zhang, Danghui Wang	An Efficient Verification Method for Microprocessors Based on the Virtual Machine.	ICESS	2004	DBLP DOI BibTeX RDF
35	Carlo Brandolese, Fabio Salice, William Fornaciari, Donatella Sciuto	Static power modeling of 32-bit microprocessors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
35	Yi-Ping You, Chingren Lee, Jenq Kuen Lee	Compiler Analysis and Supports for Leakage Power Reduction on Microprocessors.	LCPC	2002	DBLP DOI BibTeX RDF
35	Al Crouch, Jeff Freeman	Designing and Verifying Embedded Microprocessors.	IEEE Des. Test Comput.	1997	DBLP DOI BibTeX RDF
35	Chen-Shang Lin, Hong-Fa Ho	Automatic Functional Test Program Generation for Microprocessors.	DAC	1988	DBLP BibTeX RDF
31	Skyler Schneider, Daniel Y. Deng, Daniel Lo, Greg Malysa, G. Edward Suh	Implementing dynamic information flow tracking on microprocessors with integrated FPGA fabric (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	dynamic inspection, reconfigurable microprocessors, fpga
31	Adam Waksman, Simha Sethumadhavan	Tamper Evident Microprocessors.	IEEE Symposium on Security and Privacy	2010	DBLP DOI BibTeX RDF	microprocessors, hardware security, backdoors
31	Nikolaos Kavvadias, Spiridon Nikolaidis 0001	Elimination of Overhead Operations in Complex Loop Structures for Embedded Microprocessors.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Optimization, Microprocessors, Hardware description languages, Real-time and embedded systems, Pipeline processors, Control design
31	Giovanni Squillero	Ea-based test and verification of microprocessors.	GECCO (Companion)	2008	DBLP DOI BibTeX RDF	post-sysnthesis verification, pre-sysnthesis verification, test, evolutionary algorithm, microprocessors
31	David Van Campenhout, Trevor N. Mudge, John P. Hayes	High-Level Test Generation for Design Verification of Pipelined Microprocessors.	DAC	1999	DBLP DOI BibTeX RDF	high-level test generation, pipelined microprocessors, sequential test generation, design verification
31	Li Shen, Stephen Y. H. Su	A Functional Testing Method for Microprocessors.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	functional testing method, control fault model, register transfer language, k-out-of-m codes, test generation time, microprocessors, microprocessor chips, computer testing, testing requirements
31	Thirumalai Sridhar, John P. Hayes	A Functional Approach to Testing Bit-Sliced Microprocessors.	IEEE Trans. Computers	1981	DBLP DOI BibTeX RDF	Bit-sliced processors, test generation, fault modeling, microprocessors, testability, iterative logic arrays
31	Victor S. Foster	MIDAS: A MID-level language for microprocessors.	ACM Annual Conference (2)	1978	DBLP DOI BibTeX RDF	Microprocessor languages, Mid-level languages, Languages, Microprocessors, MIDAS
30	Csaba Andras Moritz, Donald Yeung, Anant Agarwal	SimpleFit: A Framework for Analyzing Design Trade-Offs in Raw Architectures.	IEEE Trans. Parallel Distributed Syst.	2001	DBLP DOI BibTeX RDF	modeling, architecture, Multiprocessors, microprocessors
30	Marco Ferretti	Multi-Media Extensions in Super-Pipelined Micro-Architectures. A New Case for SIMD Processing?	CAMP	2000	DBLP DOI BibTeX RDF	super-pipelined microarchitectures, general purpose microprocessors, Von-Neumann paradigm, image processing, parallel architectures, associated memory, instruction set architectures, massively parallel processors, multimedia extensions, SIMD processing
29	Laurent Fournier, Yaron Arbetman, Moshe Levinger	Functional Verification Methodology for Microprocessors Using the Genesys Test-Program Generator-Application to the x86 Microprocessors Family.	DATE	1999	DBLP DOI BibTeX RDF
28	Rui Gong, Kui Dai, Zhiying Wang 0003	A Framework to Evaluate the Trade-off among AVF Performance and Area of Soft Error Tolerant Microprocessors.	DFT	2008	DBLP DOI BibTeX RDF
28	Kamran Zarrineh	Design for Test Challenges of High Performance/Low Power Microprocessors.	DFT	2008	DBLP DOI BibTeX RDF
28	Dimitris Gizopoulos, Robert C. Aitken, Sandip Kundu	Guest Editorial: Special Section on "Autonomous Silicon Validation and Testing of Microprocessors and Microprocessor-Based Systems".	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
28	Srinivas Vadlamani, Stephen F. Jenks	Architectural Considerations for Efficient Software Execution on Parallel Microprocessors.	IPDPS	2007	DBLP DOI BibTeX RDF
28	Dietmar Fey, Marcus Komann, Frank Schurz, Andreas Loos	An Organic Computing architecture for visual microprocessors based on Marching Pixels.	ISCAS	2007	DBLP DOI BibTeX RDF
28	Wen-mei W. Hwu, Shane Ryoo, Sain-Zee Ueng, John H. Kelm, Isaac Gelado, Sam S. Stone, Robert E. Kidd, Sara S. Baghsorkhi, Aqeel Mahesri, Stephanie C. Tsao, Nacho Navarro, Steven S. Lumetta, Matthew I. Frank, Sanjay J. Patel	Implicitly Parallel Programming Models for Thousand-Core Microprocessors.	DAC	2007	DBLP DOI BibTeX RDF
28	Jason A. Blome, Shantanu Gupta, Shuguang Feng, Scott A. Mahlke	Cost-efficient soft error protection for embedded microprocessors.	CASES	2006	DBLP DOI BibTeX RDF	reliability, embedded processors, soft errors
28	Jayanta Bhadra, Magdy S. Abadir, David Burgess, Ekaterina Trofimova	Automatic Generation of High Performance Embedded Memory Models for PowerPC Microprocessors.	MTV	2005	DBLP DOI BibTeX RDF
28	Andre L. R. Pouponnot	Strategic Use of SEE Mitigation Techniques for the Development of the ESA Microprocessors: Past, Present and Future.	IOLTS	2005	DBLP DOI BibTeX RDF
28	Eyal Bin, Laurent Fournier	Micro-Architecture Verification for Microprocessors.	MTV	2004	DBLP DOI BibTeX RDF
28	Sumeet Kumar, Prateek Pujara, Aneesh Aggarwal	Bit-Sliced Datapath for Energy-Efficient High Performance Microprocessors.	PACS	2004	DBLP DOI BibTeX RDF
28	Lieven Eeckhout	Efficient architectural design of high performance microprocessors.	ISPASS	2004	DBLP DOI BibTeX RDF
28	Nobuyuki Ohba, Kohji Takano	An SoC design methodology using FPGAs and embedded microprocessors.	DAC	2004	DBLP DOI BibTeX RDF	mixed-level verification, SoC, ASIC, FPGA prototyping
28	Shuvendu K. Lahiri, Randal E. Bryant	Deductive Verification of Advanced Out-of-Order Microprocessors.	CAV	2003	DBLP DOI BibTeX RDF
28	Chris R. Jesshope	Multi-threaded Microprocessors - Evolution or Revolution.	Asia-Pacific Computer Systems Architecture Conference	2003	DBLP DOI BibTeX RDF
28	Shuvendu K. Lahiri, Sanjit A. Seshia, Randal E. Bryant	Modeling and Verification of Out-of-Order Microprocessors in UCLID.	FMCAD	2002	DBLP DOI BibTeX RDF
28	Toshinori Sato, Itsujiro Arita	Evaluating Low-Cost Fault-Tolerance Mechanism for Microprocessors on Multimedia Applications.	PRDC	2001	DBLP DOI BibTeX RDF
28	Wen Ching Wu, Chung-Len Lee 0001, Ming Shae Wu, Jwu E. Chen, Magdy S. Abadir	Oscillation Ring Delay Test for High Performance Microprocessors.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	oscillation ring testing, sensitized path, robust path dealy fault, hazard-free path delay fault, multiple reconvergent fanout, flunk lines, stuck at fault, delay fault testing, gate delay fault
28	Yutao He, Algirdas Avizienis	Assessment of the Applicability of COTS Microprocessors in High-Confidence Computing Systems: A Case Study.	DSN	2000	DBLP DOI BibTeX RDF
28	Kanad Ghose	Reducing energy requirements for instruction issue and dispatch in superscalar microprocessors (poster session).	ISLPED	2000	DBLP DOI BibTeX RDF	instruction dispatching, instruction issue, window buffer, superscalar processor, power minimization
28	Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto	An instruction-level functionally-based energy estimation model for 32-bits microprocessors.	DAC	2000	DBLP DOI BibTeX RDF
28	Takashi Takenaka, Junji Kitamichi, Teruo Higashino, Kenichi Taniguchi	Formal Design Verification for Correctness of Pipelined Microprocessors with Out-of-order Instruction Execution.	ASP-DAC	1999	DBLP DOI BibTeX RDF
28	Shantanu Ganguly, Daksh Lehther, Satyamurthy Pullela	Clock Distribution Methodology for PowerPCTM Microprocessors.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
28	Hélène Collavizza	Functional semantics of microprocessors at the microprogram level and correspondence with the machine instruction level.	EURO-DAC	1990	DBLP DOI BibTeX RDF
28	Michael J. Flynn, Robert I. Winner	ASIC microprocessors.	MICRO	1989	DBLP DOI BibTeX RDF
28	Paul M. Russo	Microprocessors at work: session overview.	AFIPS National Computer Conference	1975	DBLP DOI BibTeX RDF
28	Erika Gunadi, Mikko H. Lipasti	Power-aware operand delivery.	ISLPED	2007	DBLP DOI BibTeX RDF	power, microarchitecture, renaming
28	Toshinori Sato	Exploiting Instruction Redundancy for Transient Fault Tolerance.	DFT	2003	DBLP DOI BibTeX RDF
28	James Laudon, Anoop Gupta, Mark Horowitz	Interleaving: A Multithreading Technique Targeting Multiprocessors and Workstations.	ASPLOS	1994	DBLP DOI BibTeX RDF
23	Mondira (Mandy) Deb Pant	Microprocessor power delivery challenges in the Nano-Era.	ISLPED	2010	DBLP DOI BibTeX RDF	power delivery, power, microprocessors
23	Deniz Balkan, Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghose	Predicting and Exploiting Transient Values for Reducing Register File Pressure and Energy Consumption.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	General, Microprocessors, Pipeline processors, Performance attributes
23	Nicholas J. Wang, Aqeel Mahesri, Sanjay J. Patel	Examining ACE analysis reliability estimates using fault-injection.	ISCA	2007	DBLP DOI BibTeX RDF	fault tolerance, microprocessors, soft errors, measurement techniques
23	Patricio Bulic, Veselko Gustin	An efficient way to filter out data dependences with a sufficiently large distance between memory references.	ACM SIGPLAN Notices	2005	DBLP DOI BibTeX RDF	SIMD microprocessors, vectorizing compilers, data dependence analysis
23	Michael B. Taylor, Walter Lee, Saman P. Amarasinghe, Anant Agarwal	Scalar Operand Networks.	IEEE Trans. Parallel Distributed Syst.	2005	DBLP DOI BibTeX RDF	microprocessors, distributed architectures, Interconnection architectures
23	Fred A. Bower, Sule Ozev, Daniel J. Sorin	Autonomic Microprocessor Execution via Self-Repairing Arrays.	IEEE Trans. Dependable Secur. Comput.	2005	DBLP DOI BibTeX RDF	Logic design reliability and testing, microprocessors and microcomputers
23	William Lloyd Bircher, M. Valluri, J. Law, Lizy K. John	Runtime identification of microprocessor energy saving opportunities.	ISLPED	2005	DBLP DOI BibTeX RDF	speculative microprocessors, modeling, energy efficiency, power
23	Xiuli Sun, Jinzhao Wu, Xiaoyu Song, Mila E. Majster-Cederbaum	Formal Specification of an Asynchronous Processor via Action Refinement.	MTV	2004	DBLP DOI BibTeX RDF	pipelines, microprocessors, asynchronous circuits, Action refinement
23	Johnson Kin, Munish Gupta, William H. Mangione-Smith	The Filter Cache: An Energy Efficient Memory Structure.	MICRO	1997	DBLP DOI BibTeX RDF	direct mapped 256-byte filter cache, energy efficient memory structure, on-chip caches, static RAM, microprocessors, microprocessor chips, power reduction, embedded applications, L2 cache, filter cache, L1 cache
23	Juha Plosila, Kaisa Sere	Action Systems in Pipelined Processor Design.	ASYNC	1997	DBLP DOI BibTeX RDF	pipelined processor design, asynchronous pipelined microprocessors, hazard situations, verifying refinement steps, circuit implementation, speed-independent techniques, refinement calculus, refinement calculus, action systems
23	Shoji Suzuki, Kang G. Shin	On memory protection in real-time OS for small embedded systems.	RTCSA	1997	DBLP DOI BibTeX RDF	real-time OS, small embedded systems, region enlargement, memory consumption, processing overhead, intermediate-level skip multi-size paging, multi-level paging, short-circuit segment tree, real-time systems, reliability, safety, microprocessors, paged segmentation, hardware support, memory protection
23	Georg Färber, Franz Fischer, Thomas Kolloch, Annette Muth	Improving processor utilization with a task classification model based application specific hard real-time architecture.	RTCSA	1997	DBLP DOI BibTeX RDF	task classification model, application specific hard real-time architecture, real-time architecture, target architecture framework, tightly coupled heterogeneous multiprocessor system, rapid prototyping platform, caches, pipelines, microprocessors, templates, schedulability analysis, execution times, software prototyping, hard real time systems, processor utilization
23	P. Bosch, A. Carloganu, Daniel Etiemble	Complete x86 instruction trace generation from hardware bus collect.	EUROMICRO	1997	DBLP DOI BibTeX RDF	complete x86 instruction trace generation, hardware bus collect, architectural improvements, benchmark traces, hardware/software approach, x86 execution traces, commercial analyzer, computer architecture, microprocessors, memory hierarchies, trace driven simulation, performance data
23	Wolfgang K. Giloi, Ulrich Brüning 0001, Wolfgang Schröder-Preikschat	MANNA: Prototype of a Distributed Memory Architecture with Maximized Sustained Performance.	PDP	1996	DBLP DOI BibTeX RDF	maximized sustained performance, compiler problem, innovative architectural solutions, overlapping communication, MANNA computer, benchmark performance, performance evaluation, parallel computers, operating system, parallel machines, distributed memory systems, parallelizing compilers, operating systems (computers), programmability, virtual storage, parallelising compilers, latency hiding, distributed memory parallel computer, distributed memory architecture, virtual shared memory, global address space, superscalar microprocessors