Search results for "min-area"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
87	Hannah Honghua Yang, Martin D. F. Wong	Optimal min-area min-cut replication in partitioned circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
60	Hannah Honghua Yang, D. F. Wong 0001	New algorithms for min-cut replication in partitioned circuits.	ICCAD	1995	DBLP DOI BibTeX RDF	Hyper-MAMC, VLSI circuit partitioning, k-way partition, k-way partitioned digraph, min-cut replication, partitioned circuits, VLSI, optimal algorithm, circuit layout CAD, hypergraphs, VLSI layout, digraphs, circuit layout
59	Jia Wang 0003, Hai Zhou 0001	An efficient incremental algorithm for min-area retiming.	DAC	2008	DBLP DOI BibTeX RDF	retiming
47	Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi	A new approach for integration of min-area retiming and min-delay padding for simultaneously addressing short-path and long-path constraints.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	Minimum area retiming, application of mincost network flow, longpath circuit constraints, minimum delay padding, shortpath circuit constraints
33	James D. Z. Ma, Lei He 0001	Simultaneous signal and power routing under K model.	SLIP	2001	DBLP DOI BibTeX RDF	net ordering, on-chip inductance, shield insertion, interconnect estimation, interconnect design
31	Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi	Marsh: min-area retiming with setup and hold constraints.	ICCAD	1999	DBLP DOI BibTeX RDF
26	Fei Li 0003, Yizhou Lin, Lei He 0001, Deming Chen, Jason Cong	Power modeling and characteristics of field programmable gate arrays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
22	Aaron P. Hurst, Alan Mishchenko, Robert K. Brayton	Scalable min-register retiming under timing and initializability constraints.	DAC	2008	DBLP DOI BibTeX RDF	min-area, retiming, initial state, sequential optimization
17	Ana Mafalda Martins, António Leslie Bajuelos	Characterizing and Covering Some Subclasses of Orthogonal Polygons.	International Conference on Computational Science (2)	2006	DBLP DOI BibTeX RDF
16	Elias Dahlhaus, Sariel Har-Peled, Alan L. Hu	Covering Polygons by Min-Area Convex Polygons.	CoRR	2019	DBLP BibTeX RDF
16	Inhak Han, Youngsoo Shin	Folded Circuit Synthesis: Min-Area Logic Synthesis Using Dual-Edge-Triggered Flip-Flops.	ACM Trans. Design Autom. Electr. Syst.	2018	DBLP DOI BibTeX RDF
16	Weijie Chen, Hailong Yao, Yici Cai, Qiang Zhou 0001	Analog routing considering min-area constraint.	ASICON	2013	DBLP DOI BibTeX RDF
16	Tong Jing, Ling Zhang, Jinghong Liang, Jingyu Xu, Xianlong Hong, Jinjun Xiong, Lei He 0001	A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem.	ASP-DAC	2005	DBLP DOI BibTeX RDF
16	Jason Baumgartner, Andreas Kuehlmann	Min-Area Retiming on Dynamic Circuit Structures.	ICCAD	2001	DBLP DOI BibTeX RDF
15	Wai-Kei Mak, Evangeline F. Y. Young	Temporal logic replication for dynamically reconfigurable FPGA partitioning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
15	Wai-Kei Mak, Evangeline F. Y. Young	Temporal logic replication for dynamically reconfigurable FPGA partitioning.	ISPD	2002	DBLP DOI BibTeX RDF
13	Narendra V. Shenoy, Richard L. Rudell	Efficient implementation of retiming.	ICCAD	1994	DBLP DOI BibTeX RDF
13	Changbo Long, Jinjun Xiong, Lei He 0001	On optimal physical synthesis of sleep transistors.	ISPD	2004	DBLP DOI BibTeX RDF	physical design, power-gating, sleep transistors
9	Muhammet Mustafa Ozdal, Martin D. F. Wong	A provably good algorithm for high performance bus routing.	ICCAD	2004	DBLP DOI BibTeX RDF
9	Chao-Yang Yeh, Malgorzata Marek-Sadowska	Minimum-Area Sequential Budgeting for FPGA.	ICCAD	2003	DBLP DOI BibTeX RDF
9	Xiaoping Tang, D. F. Wong 0001	Floorplanning with alignment and performance constraints.	DAC	2002	DBLP DOI BibTeX RDF	floorplanning, longest common subsequence, sequence pair
7	Mohamed A. Elgamel, Ashok Kumar 0001, Magdy A. Bayoumi	Efficient shield insertion for inductive noise reduction in nanometer technologies.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
7	Xiaoping Tang, Martin D. F. Wong	On handling arbitrary rectilinear shape constraint.	ASP-DAC	2004	DBLP DOI BibTeX RDF
7	Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Xu Xu 0001, Alexander Zelikovsky	Multi-project reticle floorplanning and wafer dicing.	ISPD	2004	DBLP DOI BibTeX RDF	multi-project wafers, reticle design, wafer dicing
7	Mohamed A. Elgamel, Magdy A. Bayoumi	Minimum-Area Shield Insertion for Explicit Inductive Noise Reduction.	SBCCI	2003	DBLP DOI BibTeX RDF	Shield insertion, Algorithms, Noise, Inductance, DSM