Search results for "mixed-level"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
38	Chung Len Lee 0001, Ching Ping Wu, Wen-Zen Shen, Tyh-Song Hwang, Shueng Dar Hwang	MT-SIM a mixed-level transition fault simulator based on parallel patterns.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	mixed-level, parallel pattern, Fault simulation, transition fault
37	Alexander Maili, Damian Dalton, Christian Steger	A Generic Timing Mechanism for Using the APPLES Gate-Level Simulator in a Mixed-Level Simulation Environment.	PATMOS	2004	DBLP DOI BibTeX RDF
33	Uwe Gläser, Heinrich Theodor Vierhaus	Mixed level test generation for synchronous sequential circuits using the FOGBUSTER algorithm.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
25	Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi	The VPI-Based Combinational IP Core Module-Based Mixed Level Serial Fault Simulation and Test Generation Methodology.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
25	Kartikeya Mayaram, Jue-Hsien Chern, Ping Yang 0001	Algorithms for transient three-dimensional mixed-level circuit and device simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
23	Mark Thompson 0001, Andy D. Pimentel, Simon Polstra, Cagkan Erbas	A Mixed-level Co-simulation Method for System-level Design Space Exploration.	ESTIMedia	2006	DBLP DOI BibTeX RDF
20	Tyh-Song Hwang, Chung Len Lee 0001, Wen-Zen Shen, Ching Ping Wu	A Parallel Pattern Mixed-Level Fault Simulator.	DAC	1990	DBLP DOI BibTeX RDF
17	Wolfgang Borutzky	Combining Behavioral Block Diagram Modelling with Circuit Simulation.	EUROCAST	1989	DBLP DOI BibTeX RDF	mixed behavioral, circuit-level modelling, electrical macromodels, continuous system simulation, electronic control systems, circuit simulation, functional simulation, block diagrams, signal processing systems
16	Moshe Meyassed, Robert H. Klenke, James H. Aylor	Resolving unknown inputs in mixed-level simulation with sequential elements.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
16	Kartikeya Mayaram, Donald O. Pederson	Coupling algorithms for mixed-level circuit and device simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
16	Shigeru Takasaki, Tohru Sasaki, Nobuyoshi Nomizu, Hiroshi Ishikura, Nobuhiko Koike	HAL II: a mixed level hardware logic simulation system.	DAC	1986	DBLP DOI BibTeX RDF
15	Philip J. Guo, Jeff H. Perkins, Stephen McCamant, Michael D. Ernst	Dynamic inference of abstract types.	ISSTA	2006	DBLP DOI BibTeX RDF	mixed-level analysis, values and variables, Java, interaction, C++, C, dynamic analysis, type inference, abstract types, units
15	Renée C. Bryce, Charles J. Colbourn	Test prioritization for pairwise interaction coverage.	ACM SIGSOFT Softw. Eng. Notes	2005	DBLP DOI BibTeX RDF	biased covering arrays, pairwise interaction coverage, greedy algorithm, covering arrays, software interaction testing, mixed-level covering arrays
15	Renée C. Bryce, Charles J. Colbourn	Test prioritization for pairwise interaction coverage.	A-MOST	2005	DBLP DOI BibTeX RDF	biased covering arrays, pairwise interaction coverage, greedy algorithm, covering arrays, software interaction testing, mixed-level covering arrays
15	Renée C. Bryce	Automatic generation of high coverage usability tests.	CHI Extended Abstracts	2005	DBLP DOI BibTeX RDF	usability testing, design of experiments, covering arrays, mixed-level covering arrays, interaction testing
15	Renée C. Bryce, Charles J. Colbourn	Constructing interaction test suites with greedy algorithms.	ASE	2005	DBLP DOI BibTeX RDF	biased covering arrays, t-way interaction coverage, greedy algorithm, covering arrays, software interaction testing, mixed-level covering arrays
15	Renée C. Bryce, Charles J. Colbourn, Myra B. Cohen	A framework of greedy methods for constructing interaction test suites.	ICSE	2005	DBLP DOI BibTeX RDF	pair-wise interaction coverage, greedy algorithm, covering arrays, software interaction testing, mixed-level covering arrays
15	Wiebke S. Diestelkamp	Parameter Inequalities for Orthogonal Arrays with Mixed Levels.	Des. Codes Cryptogr.	2004	DBLP DOI BibTeX RDF	mixed-level orthogonal array, group character, adjacency operator
15	Zainalabedin Navabi, Shahrzad Mirkhani, Meisam Lavasani, Fabrizio Lombardi	Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	hierarchical fault simulation, mixed level, delta times, VHDL, register transfer level
15	Nobuyuki Ohba, Kohji Takano	An SoC design methodology using FPGAs and embedded microprocessors.	DAC	2004	DBLP DOI BibTeX RDF	mixed-level verification, SoC, ASIC, FPGA prototyping
15	Stephen J. Hegner	Transaction Isolation in Mixed-Level and Mixed-Scope Settings.	ADBIS	2019	DBLP DOI BibTeX RDF
15	Erwin de Kock, Jos Verhaegh, Serge Amougou	A configurable test infrastructure using a mixed-language and mixed-level IP integration IP-XACT flow.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
15	Hans Fleurkens, Pim H. W. Buurman	Flexible Mixed-mode and Mixed-level Simulation.	ISCAS	1993	DBLP BibTeX RDF
15	Marcelino B. Santos, João Paulo Teixeira 0001	Defect-Oriented Mixed-Level Fault Simulation of Digital Systems-on-a-Chip Using HDL.	DATE	1999	DBLP DOI BibTeX RDF
15	Hi-Keung Tony Ma, Alberto L. Sangiovanni-Vincentelli	Mixed-level fault coverage estimation.	DAC	1986	DBLP DOI BibTeX RDF
14	L. Peter Deutsch	Engineering broad-spectrum document software: lessons from ghostscript.	ACM Symposium on Document Engineering	2002	DBLP DOI BibTeX RDF
14	Chang-Xing Ma, Ming-Yao Ai, L. Y. Chan, T. N. Goh	Three-level and mixed-level orthogonal arrays for lean designs.	Qual. Reliab. Eng. Int.	2010	DBLP DOI BibTeX RDF
12	Fei Li 0003, Yizhou Lin, Lei He 0001, Deming Chen, Jason Cong	Power modeling and characteristics of field programmable gate arrays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
12	Venkatram Krishnaswamy, Jeremy Casas, Thomas Tetzlaff	A switch level fault simulation environment.	DAC	2000	DBLP DOI BibTeX RDF
11	Régis Leveugle, D. Cimonnet, Abdelaziz Ammari	System-Level Dependability Analysis with RT-Level Fault Injection Accuracy.	DFT	2004	DBLP DOI BibTeX RDF
10	Sungjoo Yoo, Gabriela Nicolescu, Damien Lyonnard, Amer Baghdadi, Ahmed Amine Jerraya	A generic wrapper architecture for multi-processor SoC cosimulation and design.	CODES	2001	DBLP DOI BibTeX RDF
10	J. Will Specks, Walter L. Engl	Computer-aided design and scaling of deep submicron CMOS.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
10	Jaan Raik, Tanel Nõmmeots, Raimund Ubar	A New Testability Calculation Method to Guide RTL Test Generation.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	test pattern generation, register-transfer level, decision diagrams, testability measures
10	Kent L. Einspahr, Sharad C. Seth	A switch-level test generation system for synchronous and asynchronous circuits.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	reverse time processing, stuck-open and stuck-at faults, time-frame expansion, sequential circuits, Automatic test generation
10	Rakhi Singh	Pareto-efficient designs for multi- and mixed-level supersaturated designs.	Stat. Comput.	2024	DBLP DOI BibTeX RDF
10	Ahmed M. Elsawah	A novel low complexity fast algorithm for effectively designing optimal mixed-level experiments.	Commun. Stat. Simul. Comput.	2024	DBLP DOI BibTeX RDF
10	Kashinath Chatterjee, Min-Qian Liu, Hong Qin 0008, Liuqing Yang	Construction of Optimal Mixed-Level Uniform Designs.	J. Syst. Sci. Complex.	2024	DBLP DOI BibTeX RDF
10	Ankita Verma, Seema Jaggi, Eldho Varghese, Cini Varghese, Arpan Bhowmik, Anindita Datta, Hemavathi M	On the construction of mixed-level rotatable response surface designs when experimental unit experiences overlap effects.	Commun. Stat. Simul. Comput.	2023	DBLP DOI BibTeX RDF
10	Shiqi Wei, Ziyu Wang, Weiguo Gao, Gus Xia	Controllable Music Inpainting with Mixed-Level and Disentangled Representation.	ICASSP	2023	DBLP DOI BibTeX RDF
10	Shuwei Qian, Ming Guo, Zhicheng Fan, Mingcai Chen, Chongjun Wang	LAMB: Label-Induced Mixed-Level Blending for Multimodal Multi-label Emotion Detection.	CollaborateCom (2)	2023	DBLP DOI BibTeX RDF
10	Wei-Ting Yeh, Chung-Lun Chang, Shang-Chih Yin, Chien-Hung Tsai	Mixed-Level Design Methodology With SystemVerilog Behavior Models for Digitally Controlled Power Converter ICs.	GCCE	2023	DBLP DOI BibTeX RDF
10	Alla M. Manakhova, Nadezhda S. Lagutina	Analysis of the Influence of Mixed-Level Stylometric Characteristics on the Verification of Authors of Literary Works.	Autom. Control. Comput. Sci.	2022	DBLP DOI BibTeX RDF
10	Shuo Yang, Yang Jiao, Shaoyu Dou, Mana Zheng, Chen Zhu	CPMLHO: Hyperparameter Tuning via Cutting Plane and Mixed-Level Optimization.	CoRR	2022	DBLP DOI BibTeX RDF
10	Li-Chun Chen, Hsin-I Wu, Ren-Song Tsay	Automatic Timing-Coherent Transactor Generation for Mixed-level Simulations.	CoRR	2021	DBLP BibTeX RDF
10	Nam-Ky Nguyen, Tung-Dinh Pham, Mai Phuong Vuong	Constructing D-Efficient Mixed-Level Foldover Designs Using Hadamard Matrices.	Technometrics	2020	DBLP DOI BibTeX RDF
10	Chaoyang He 0001, Haishan Ye, Li Shen 0005, Tong Zhang 0001	MiLeNAS: Efficient Neural Architecture Search via Mixed-Level Reformulation.	CoRR	2020	DBLP BibTeX RDF
10	Thien Nguyen, Huu Nguyen, Phuoc Tran	Mixed-Level Neural Machine Translation.	Comput. Intell. Neurosci.	2020	DBLP DOI BibTeX RDF
10	Chaoyang He 0001, Haishan Ye, Li Shen 0005, Tong Zhang 0001	MiLeNAS: Efficient Neural Architecture Search via Mixed-Level Reformulation.	CVPR	2020	DBLP BibTeX RDF
10	Ulrike Grömping, Roberto Fontana	An algorithm for generating good mixed level factorial designs.	Comput. Stat. Data Anal.	2019	DBLP DOI BibTeX RDF
10	Yaquelin V. Pantoja, Armando J. Ríos, Moisés Tapia Esquivias	A method for construction of mixed-level fractional designs.	Qual. Reliab. Eng. Int.	2019	DBLP DOI BibTeX RDF
10	Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik	Mixed-level identification of fault redundancy in microprocessors.	CoRR	2019	DBLP BibTeX RDF
10	Feng Yang, Yong-Dao Zhou, Aijun Zhang	Mixed-level column augmented uniform designs.	J. Complex.	2019	DBLP DOI BibTeX RDF
10	Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik	Mixed-level identification of fault redundancy in microprocessors.	LATS	2019	DBLP DOI BibTeX RDF
10	Linda Lee Ho, Carla A. Vivacqua, André Luís Santos de Pinho	Extensions and variants of mixed-level split-plot designs for manufacturing planning and optimization.	Qual. Reliab. Eng. Int.	2018	DBLP DOI BibTeX RDF
10	Yi-Hua Chang, Kai-Yu Hu, Guan-Shen Yao, Chun-Yu Chen, Chien-Hung Tsai	Mixed-Level Design Methodology for Digitally Controlled Power Converter IC.	GCCE	2018	DBLP DOI BibTeX RDF
10	Qiang Gao, Wenping Ma, Xiaoping Li	A Key Predistribution Scheme Based on Mixed-level Orthogonal Arrays.	Ad Hoc Sens. Wirel. Networks	2017	DBLP BibTeX RDF
10	Ahmed M. Elsawah, Hong Qin 0008	Optimum mechanism for breaking the confounding effects of mixed-level designs.	Comput. Stat.	2017	DBLP DOI BibTeX RDF
10	Sander Bogers, Carl Megens, Steven Vos	Design for Balanced Engagement in Mixed Level Sports Teams.	CHI Extended Abstracts	2017	DBLP DOI BibTeX RDF
10	Li-Chun Chen, Hsin-I Wu, Ren-Song Tsay	Automatic timing-coherent transactor generation for mixed-level simulations.	ASP-DAC	2015	DBLP DOI BibTeX RDF
10	Juliana Marino Balera, Valdivino Alexandre de Santiago Júnior	T-Tuple Reallocation: An Algorithm to Create Mixed-Level Covering Arrays to Support Software Test Case Generation.	ICCSA (4)	2015	DBLP DOI BibTeX RDF
10	Kelson Gent, Michael S. Hsiao	Dual-Purpose Mixed-Level Test Generation Using Swarm Intelligence.	ATS	2014	DBLP DOI BibTeX RDF
10	Leibo Liu, Wen Jia, Shouyi Yin, Dong Wang 0040, Guanyi Sun, Eugene Tang, Shaojun Wei	ReSSIM: a mixed-level simulator for dynamic coarse-grained reconfigurable processor.	Sci. China Inf. Sci.	2013	DBLP DOI BibTeX RDF
10	Armando J. Ríos, James R. Simpson, Yong Guo	Semifold plans for mixed-level designs.	Qual. Reliab. Eng. Int.	2011	DBLP DOI BibTeX RDF
10	George Giorgidze, Henrik Nilsson	Mixed-Level Embedding and JIT Compilation for an Iteratively Staged DSL.	WFLP	2010	DBLP DOI BibTeX RDF
10	Jan Haase 0001, Mario Lang, Christoph Grimm 0001	Mixed-Level Simulation of Wireless Sensor Networks.	FDL	2010	DBLP BibTeX RDF
10	Markus Becker 0001, Henning Zabel, Wolfgang Müller 0003	A Mixed Level Simulation Environment for Stepwise RTOS Software Refinement.	DIPES/BICC	2010	DBLP DOI BibTeX RDF
10	Yang Hu 0001, Shouyi Yin, Leibo Liu, Shaojun Wei	Mixed-level modeling for network on chip infrastructure in SoC design.	APCCAS	2010	DBLP DOI BibTeX RDF
10	Min-Qian Liu, Li Zhang	An algorithm for constructing mixed-level k-circulant supersaturated designs.	Comput. Stat. Data Anal.	2009	DBLP DOI BibTeX RDF
10	Yong Guo, James R. Simpson, Joseph J. Pignatiello Jr.	The general balance metric for mixed-level fractional factorial designs.	Qual. Reliab. Eng. Int.	2009	DBLP DOI BibTeX RDF
10	Yong Guo, James R. Simpson, Joseph J. Pignatiello Jr.	Optimal foldover plans for mixed-level fractional factorial designs.	Qual. Reliab. Eng. Int.	2009	DBLP DOI BibTeX RDF
10	Sanggyu Park, Sang-yong Yoon, Soo-Ik Chae	A mixed-level virtual prototyping environment for SystemC-based design methodology.	Microelectron. J.	2009	DBLP DOI BibTeX RDF
10	Nam-Ky Nguyen, Min-Qian Liu	An algorithmic approach to constructing mixed-level orthogonal and near-orthogonal arrays.	Comput. Stat. Data Anal.	2008	DBLP DOI BibTeX RDF
10	Hung-Yuan Chu, Chun-Hung Yang, Chi-Wai Leng, Chien-Hung Tsai	A top-down, mixed-level design methodology for CT BP ΔΣ modulator using verilog-A.	APCCAS	2008	DBLP DOI BibTeX RDF
10	Juergen Weber, Andreas C. Lemke, Andreas Lehmler, Mario Anton, Sorin A. Huss	Mixed-Level Modeling Using Configurable MOS Transistor Models.	FDL	2007	DBLP BibTeX RDF
10	Shu Yamada, Michiyo Matsui, Tomomi Matsui, Dennis K. J. Lin, Takenori Takahashi	A general construction method for mixed-level supersaturated design.	Comput. Stat. Data Anal.	2006	DBLP DOI BibTeX RDF
10	Sanggyu Park, Sang-yong Yoon, Soo-Ik Chae	A Mixed-Level Virtual Prototyping Environment for Refinement-Based Design Environment.	IEEE International Workshop on Rapid System Prototyping	2006	DBLP DOI BibTeX RDF
10	M. Enamul Amyeen, Debashis Nayak, Srikanth Venkataraman	Improving Precision Using Mixed-level Fault Diagnosis.	ITC	2006	DBLP DOI BibTeX RDF
10	Jeff Z. Ma, Li Deng 0001	A mixed-level switching dynamic system for continuous speech recognition.	Comput. Speech Lang.	2004	DBLP DOI BibTeX RDF
10	Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi	Using Verilog VPI for Mixed Level Serial Fault Simulation in a Test Generation Environment.	Embedded Systems and Applications	2003	DBLP BibTeX RDF
10	Robert H. Klenke, James H. Aylor, Moshe Meyassed, William W. Dungan	Interfaces for mixed-level simulation with sequential elements.	J. Syst. Archit.	2001	DBLP DOI BibTeX RDF
10	Gabriela Nicolescu, Sungjoo Yoo, Ahmed Amine Jerraya	Mixed-level cosimulation for fine gradual refinement of communication in SoC design.	DATE	2001	DBLP DOI BibTeX RDF
10	Leo C. N. de Vreede, Henk C. de Graaff, Joost A. Willemen, Wibo D. van Noort, Rik Jos, Lawrence E. Larson, Jan W. Slotboom, Joseph L. Tauritz	Bipolar transistor epilayer design using the MAIDS mixed-level simulator.	IEEE J. Solid State Circuits	1999	DBLP DOI BibTeX RDF
10	Hitoshi Hemmi, Tomofumi Hikage, Katsunori Shimohara	On mixed-level real-time hardware evolutionary systems.	Artif. Life Robotics	1999	DBLP DOI BibTeX RDF
10	Michael Hess 0001	Mixed-Level Knowledge Representation and Variable-Depth Inference in Natural Language Processing	CoRR	1999	DBLP BibTeX RDF
10	Michael Hess 0001	Deduction over Mixed-Level Logic Representations for Text Passage Retrieval	CoRR	1999	DBLP BibTeX RDF
10	Mauro Chinosi, Roberto Zafalon, Carlo Guardiani	Fast and accurate power verification of a Viterbi decoder IP based on mixed-level power simulation technique with automatic spatio-temporal circuit partitioning.	CICC	1999	DBLP DOI BibTeX RDF
10	Mauro Chinosi, Roberto Zafalon, Carlo Guardiani	Parallel Mixed-Level Power Simulation Based on Spatio-Temporal Circuit Partitioning.	DAC	1999	DBLP DOI BibTeX RDF
10	Mihai A. T. Sanduleanu, A. J. M. van Tuijl, R. F. Wassenaar, M. C. Lammers, H. Wallinga	A low noise, low residual offset, chopped amplifier for mixed level applications.	ICECS	1998	DBLP DOI BibTeX RDF
10	F. Keith Hanna	Automatic Verification of Mixed-Level Logic Circuits.	FMCAD	1998	DBLP DOI BibTeX RDF
10	Michael Hess 0001	Mixed-Level Knowledge Representations and Variable-Depth Inference in Natural Language Processing.	Int. J. Artif. Intell. Tools	1997	DBLP DOI BibTeX RDF
10	Michael Hess 0001	Deduction over Mixed-Level Logic Representations.	ICTAI	1996	DBLP DOI BibTeX RDF
10	Sankaran Karthik, Mark Aitken, Glidden Martin, Srinivasu Pappula, Bob Stettler, Praveen Vishakantaiah, Manuel A. d'Abreu, Jacob A. Abraham	Distributed Mixed Level Logic and Fault Simulation on the Pentium® Pro Microprocessor.	ITC	1996	DBLP DOI BibTeX RDF
10	Uwe Hübner	Partitionierung und Analyse statischer, digitaler CMOS-Schaltungen auf der Schalterebene einer Mixed-Level Testgenerierung.		1994	RDF
10	Carolina L. C. Cooper, Michael L. Bushnell	Neural models for transistor and mixed-level test generation.	VTS	1994	DBLP DOI BibTeX RDF
10	Dah-Cherng Yuan, Lawrence T. Pillage, Joseph T. Rahmeh	Evaluation of Parts by Mixed-Level DC-Connected Components in Logic Simulation.	DAC	1993	DBLP DOI BibTeX RDF
10	David I. Long, Saad Sabih Ahmed Medhat	Simulating Mixed-level Systems with VHDL.	EUROSIM	1992	DBLP BibTeX RDF
10	Uwe Gläser, Heinrich Theodor Vierhaus	MILEF: an efficient approach to mixed level automatic test pattern generation.	EURO-DAC	1992	DBLP DOI BibTeX RDF
10	Uwe Gläser, Uwe Hübner, Heinrich Theodor Vierhaus	Mixed Level Hierarchical Test Generation for Transition Faults and Overcurrent Related Defects.	ITC	1992	DBLP DOI BibTeX RDF
10	Uwe Hübner, H. Hinsen, M. Hofebauer, Heinrich Theodor Vierhaus	Mixed level test generation for high fault coverage.	Microprocessing and Microprogramming	1991	DBLP DOI BibTeX RDF
10	Kartikeya Mayaram, Ping Yang 0001, Jue-Hsien Chern	Transient Three-Dimensional Mixed-Level Circuit and Device Simulation: Algorithms and Applications.	ICCAD	1991	DBLP DOI BibTeX RDF