Search results for "multi-processor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
41	Shigeaki Iwasa, Shung Ho Shing, Hisashi Mogi, Hiroshi Nozuwe, Hiroo Hayashi, Osamu Wakamori, Takashi Ohmizo, Kuninori Tanaka, Hiroshi Sakai, Mitsuo Saito	SSM-MP: more scalability in shared-memory multi-processor.	ICCD	1995	DBLP DOI BibTeX RDF	SSM-MP, shared-memory multi-processor, cache refill latency, bus bottle neck problem, MTag, scalability, shared memory systems, cache coherency, memory architecture, multi-processor system
39	Minsu Choi, Nohpill Park, Fabrizio Lombardi	Hardware-Software Co-Reliability in Field Reconfigurable Multi-Processor-Memory Systems.	IPDPS	2002	DBLP DOI BibTeX RDF	Multi-Processor-Memory System, Field Reconfiguration, HW/SW Co-reliability, Modular Redundancy
38	Dongyoon Lee, Mahmoud Said, Satish Narayanasamy, Zijiang Yang 0006, Cristiano Pereira	Offline symbolic analysis for multi-processor execution replay.	MICRO	2009	DBLP DOI BibTeX RDF	multi-processor replay, shared-memory dependencies, SMT solver
38	Wolfgang Puffitsch	Decoupled root scanning in multi-processor systems.	CASES	2008	DBLP DOI BibTeX RDF	real-time, garbage collection, multi-processor
34	Hossein Pourreza, Peter Graham	On the Programming Impact ofMulti-Core, Multi-Processor Nodes inMPI Clusters.	HPCS	2007	DBLP DOI BibTeX RDF
32	Giovanni Mariani, Aleksandar Brankovic, Gianluca Palermo, Jovana Jovic, Vittorio Zaccaria, Cristina Silvano	A correlation-based design space exploration methodology for multi-processor systems-on-chip.	DAC	2010	DBLP DOI BibTeX RDF	design space exploration, kriging, response surface, multi-processor systems-on-chip
32	Zhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson, Omar Sattari, Michael A. Lai, Jeremy W. Webb, Eric W. Work, Tinoosh Mohsenin, Bevan M. Baas	Architecture and Evaluation of an Asynchronous Array of Simple Processors.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	programmable DSP, digital signal processing, DSP, multi-core, array processor, GALS, many-core, chip multi-processor, globally asynchronous locally synchronous
32	Tsutomu Nishimura, Takuji Miki, Hiroaki Sugiura 0003, Yuki Matsumoto, Masatsugu Kobayashi, Toshiyuki Kato, Tsutomu Eda, Hironori Yamauchi	Configurable multi-processor architecture and its processor element design.	ASP-DAC	2006	DBLP DOI BibTeX RDF
31	Pierre G. Paulin, Chuck Pilkington, Michel Langevin, Essaid Bensoudane, Gabriela Nicolescu	Parallel programming models for a multi-processor SoC platform applied to high-speed traffic management.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	system-on-chip, embedded software, multi-processor systems
29	Pavel Krcál, Martin Stigge, Wang Yi 0001	Multi-processor Schedulability Analysis of Preemptive Real-Time Tasks with Variable Execution Times.	FORMATS	2007	DBLP DOI BibTeX RDF
28	Guilin Chen, Guangyu Chen, Ozcan Ozturk 0001, Mahmut T. Kandemir	Exploiting Inter-Processor Data Sharing for Improving Behavior of Multi-Processor SoCs.	ISVLSI	2005	DBLP DOI BibTeX RDF
28	Tai-Yi Huang, Yu-Che Tsai, Edward T.-H. Chu	A Near-optimal Solution for the Heterogeneous Multi-processor Single-level Voltage Setup Problem.	IPDPS	2007	DBLP DOI BibTeX RDF
26	Dragomir Milojevic, Luc J. M. Montperrus, Diederik Verkest	Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Multi-processor systems-on-chip (MPSoC), Real-time video encoding, AVC/H.264, Low-power VLSI implementation, decoding, Networks-on-chip (NoC)
26	Yadan Deng, Ning Jing, Wei Xiong 0010, Chen Luo, Hongsheng Chen	Hash Join Optimization Based on Shared Cache Chip Multi-processor.	DASFAA	2009	DBLP DOI BibTeX RDF	Radix-Join, Shared L2-Cache, Chip Multi-Processor, Cache Conflict
26	Jingui Huang, Jianer Chen, Songqiao Chen, Jianxin Wang 0001	A simple linear time approximation algorithm for multi-processor job scheduling on four processors.	J. Comb. Optim.	2007	DBLP DOI BibTeX RDF	Multi-processor job scheduling, Approximation algorithm, NP-hard problem
26	Kevin T. Pedretti, Ron Brightwell, Joshua Williams	Cplant? Runtime System Support for Multi-Processor and Heterogeneous Compute Nodes.	CLUSTER	2002	DBLP DOI BibTeX RDF	heterogeneous computing, runtime system, multi-processor, commodity cluster
26	Michiko Inoue, Sen Moriya, Toshimitsu Masuzawa, Hideo Fujiwara	Optimal Wait-Free Clock Synchronisation Protocol on a Shared-Memory Multi-processor System.	WDAG	1997	DBLP DOI BibTeX RDF	shared-memory multi-processor system, napping fault, fault-tolerance, clock-synchronization, wait-freedom
25	Rodrigo P. Mendonça, Mario A. R. Dantas	A Study of Adaptive Co-scheduling Approach for an Opportunistic Software Environment to Execute in Multi-core and Multi-Processor Configurations.	CSE	2008	DBLP DOI BibTeX RDF	multi-core, metacomputing, co-scheduling
24	Cheng Chang, Chien-Chung Chen, Yao-Liang Chen, Fu-Shin Huang	Real-time scheduling in a programmable radar signal processor.	RTCSA	1997	DBLP DOI BibTeX RDF	programmable radar signal processor, parallel multi-processor architecture, real-time scheduling algorithm, digital signal processing, real-time scheduling, processing speed, radar signal processing
24	Thomas Rauber, Gudula Rünger	Library support for hierarchical multi-processor tasks.	SC	2002	DBLP DOI BibTeX RDF	hierarchical decomposition of processor sets, library support, mixed task and data parallelism, multilevel group SPMD, distributed memory, multiprocessor tasks
22	G. D. Nagendra, V. G. Prem Kumar, B. S. Sheshadri Chakravarthy	Simulation bridge: a framework for multi-processor simulation.	CODES	2002	DBLP DOI BibTeX RDF	simulation framework, instruction set simulator, multiprocessor simulation
22	Gyu Sang Choi, Jin-Ha Kim, Deniz Ersoz, Chita R. Das	A multi-threaded PIPELINED Web server architecture for SMP/SoC machines.	WWW	2005	DBLP DOI BibTeX RDF	asynchronous multi-process event-driven, single event-driven process, symmetric multi-processor, system-on-chip, multi-thread, multi-process
22	Myunggwon Hwang, Dongjin Choi, Pankoo Kim	Least Slack Time Rate First: New Scheduling Algorithm for Multi-Processor Environment.	CISIS	2010	DBLP DOI BibTeX RDF	multi-processor scheduling, least slack time rate, LSTR, scheduling algorithm, optimal scheduling
22	Chandra Chekuri, Ashish Goel, Sanjeev Khanna, Amit Kumar 0001	Multi-processor scheduling to minimize flow time with epsilon resource augmentation.	STOC	2004	DBLP DOI BibTeX RDF	multi-processor scheduling, load balancing, online algorithms, stretch, resource augmentation, flow time
21	Emiliano Dolif, Michele Lombardi 0001, Martino Ruggiero, Michela Milano, Luca Benini	Communication-aware stochastic allocation and scheduling framework for conditional task graphs in multi-processor systems-on-chip.	EMSOFT	2007	DBLP DOI BibTeX RDF	multimedia dataflow streaming, scheduling, allocation
21	Dakai Zhu 0001, Rami G. Melhem, Bruce R. Childers	Scheduling with Dynamic Voltage/Speed Adjustment Using Slack Reclamation in Multi-Processor Real-Time Systems.	RTSS	2001	DBLP DOI BibTeX RDF
21	Hiroshi Yasui, Toshikazu Sakaguchi, Kohichi Kudo, Nobuyuki Hironishi	Design of the Shared Memory System for Multi-Processor Lisp Machines and Its Implementation on the EVLIS Machine.	Workshop on Parallel Lisp	1989	DBLP DOI BibTeX RDF
21	Hans G. Kerkhoff, Jarkko J. M. Huijts	Testing of a Highly Reconfigurable Processor Core for Dependable Data Streaming Applications.	DELTA	2008	DBLP DOI BibTeX RDF	reconfigurable multi-processor-cores SoC, embedded system test, dependable SoCs, ATPG, Design-for-Test, self-repair
20	Bart D. Theelen, A. C. Verschueren	Architecture Design of a Scalable Single-Chip Multi-Processor.	DSD	2002	DBLP DOI BibTeX RDF
20	Yijun Liu, Banghai Wang, Guobo Xie, Pinghua Chen, Zhenkun Li	Designing a Multi-Processor Education Board for High-Performance Embedded Processing.	ICYCS	2008	DBLP DOI BibTeX RDF
20	Guan Yu, Gauthier Lafruit, Peter Schelkens	Platform-scalable Task Partition and Multilevel Buffering in Multi-processor Plessey Corner Detector.	ACSD	2007	DBLP DOI BibTeX RDF
20	Satoshi Imai, Atsuki Inoue, Motoaki Matsumura, Kenichi Kawasaki, Atsuhiro Suga	Single-chip multi-processor integrating quadruple 8-way VLIW processors with interface timing analysis considering power supply noise.	ASP-DAC	2006	DBLP DOI BibTeX RDF
20	Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, Ingrid Verbauwhede	Energy and Performance Analysis of Mapping Parallel Multithreaded Tasks for An On-Chip Multi-Processor System.	ICCD	2005	DBLP DOI BibTeX RDF
20	Sourav Ghosh, Ragunathan Rajkumar, Jeffery P. Hansen, John P. Lehoczky	Scalable Resource Allocation for Multi-Processor QoS Optimization.	ICDCS	2003	DBLP DOI BibTeX RDF
20	Eryk Laskowski	Fast Scheduling and Partitioning Algorithm in the Multi-processor System with Redundant Communication Resources.	PPAM	2001	DBLP DOI BibTeX RDF
20	Seung-Min Lee, Jin-Hong Chung, Mike Myung-Ok Lee	High-Speed and Low-Power Real-Time Programmable Video Multi-Processor for MPEG-2 Multimedia Chip on 0.6µm TLM CMOS Technology.	ASP-DAC	1999	DBLP DOI BibTeX RDF
19	Nader Bagherzadeh, Pai H. Chou, Jinfeng Liu 0006	Combined Functional Partitioning and Communication Speed Selection for Networked Voltage-Scalable Processors.	ISSS	2002	DBLP DOI BibTeX RDF	communication speed selection, communication/computation trade-offs, embedded multi-processor, low-power design, functional partitioning
19	Bilge Saglam Akgul, Jaehwan Lee 0002, Vincent John Mooney III	A system-on-a-chip lock cache with task preemption support.	CASES	2001	DBLP DOI BibTeX RDF	lock synchronization, multi-processor synchronization, SoC, shared memory, RTOS, preemption
19	Jair Jehuda, Gilad Koren, Daniel M. Berry	A time-sharing architecture for complex real-time systems.	ICECCS	1995	DBLP DOI BibTeX RDF	time-sharing systems, time-sharing architecture, dynamic multiple job systems, shared-memory multi-processor platforms, multiple states, near-optimal mode selection, reliable real-time time-sharing, job-oriented strategy, best-effort system values, dynamic critical task sets, complex task characteristics, real-time systems, resource allocation, shared memory systems, processor scheduling, portability, dynamic load-balancing, complex real-time systems, divide-and-conquer approach
19	Marko Bertogna, Michele Cirinei	Response-Time Analysis for Globally Scheduled Symmetric Multiprocessor Platforms.	RTSS	2007	DBLP DOI BibTeX RDF
18	Jie Yu 0016, Satish Narayanasamy	A case for an interleaving constrained shared-memory multi-processor.	ISCA	2009	DBLP DOI BibTeX RDF	parallel programming, multiprocessors, software reliability, concurrency bugs
18	Torsten Kempf, Malte Doerper, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tim Kogel, Bart Vanthournout	A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms.	DATE	2005	DBLP DOI BibTeX RDF
18	Duoduo Liao, Simon Y. Berkovich	A conceptual system for parallel solid voxelization using multi-processor pipelining.	VRCAI	2008	DBLP DOI BibTeX RDF
18	Xu Cheng	Heterogeneous Multi-processor SoC: An Emerging Paradigm of Embedded System Design and Its Challenges.	ICESS	2005	DBLP DOI BibTeX RDF
18	Pierre G. Paulin, Chuck Pilkington, Essaid Bensoudane, Michel Langevin, Damien Lyonnard	Application of a Multi-Processor SoC Platform to High-Speed Packet Forwarding.	DATE	2004	DBLP DOI BibTeX RDF
18	Prasad Krishna Saravu	Multi-processor Memory Scoreboard: A Multi-processor Memory Ordering and Data Consistency Checker.	MTV	2016	DBLP DOI BibTeX RDF
17	Kimish Patel, Enrico Macii, Massimo Poncino	Synthesis of Partitioned Shared Memory Architectures for Energy-Efficient Multi-Processor SoC.	DATE	2004	DBLP DOI BibTeX RDF
17	Valentina Salapura	Scaling up next generation supercomputers.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	scalability of systems, chip multiprocessors (cmp), multicore, coherence protocols, blue gene
17	Claudia Kretzschmar, Christian Galke, Heinrich Theodor Vierhaus	A Hierarchical Self Test Scheme for SoCs.	IOLTS	2004	DBLP DOI BibTeX RDF
17	Jean-Pierre Dérutin, Lionel Damez, Alexis Landrault	Embedding of a Real Time Image Stabilization Algorithm on SoPC Platform, a Chip Multi-processor Approach.	ACIVS	2008	DBLP DOI BibTeX RDF
17	Andriy Naborskyy, Richard M. Fujimoto	Using Reversible Computation Techniques in a Parallel Optimistic Simulation of a Multi-Processor Computing System.	PADS	2007	DBLP DOI BibTeX RDF
17	Thomas Schlichter, Christian Haubelt, Frank Hannig, Jürgen Teich	Using Symbolic Feasibility Tests during Design Space Exploration of Heterogeneous Multi-Processor Systems.	ASAP	2005	DBLP DOI BibTeX RDF
17	Matteo Dall'Osso, Gianluca Biccari, Luca Giovannini, Davide Bertozzi, Luca Benini	xpipes: a Latency Insensitive Parameterized Network-on-chip Architecture For Multi-Processor SoCs.	ICCD	2003	DBLP DOI BibTeX RDF
17	Sidney Cadot, Frits Kuijlman, Koen Langendoen, Kees van Reeuwijk, Henk J. Sips	ENSEMBLE: A Communication Layer for Embedded Multi-Processor Systems.	LCTES/OM	2001	DBLP DOI BibTeX RDF
17	Jian-Jia Chen, Chia-Mei Hung, Tei-Wei Kuo	On the Minimization fo the Instantaneous Temperature for Periodic Real-Time Tasks.	IEEE Real-Time and Embedded Technology and Applications Symposium	2007	DBLP DOI BibTeX RDF	Temperature-aware scheduling, Real-time systems, Dynamic voltage scaling
17	Thin-Fong Tsuei, Wayne Yamamoto	Queuing Simulation Model for Multiprocessor Systems.	Computer	2003	DBLP DOI BibTeX RDF
17	Marek Tudruj, Lukasz Masko	Task Scheduling for Dynamically Configurable Multiple SMP Clusters Based on Extended DSC Approach.	PPAM	2001	DBLP DOI BibTeX RDF
17	Brian M. Rogers, Anil Krishna, Gordon B. Bell, Ken V. Vu, Xiaowei Jiang, Yan Solihin	Scaling the bandwidth wall: challenges in and avenues for CMP scaling.	ISCA	2009	DBLP DOI BibTeX RDF	analytical model, memory bandwidth, chip multi-processor
17	Mohammad Abdullah Al Faruque, Jörg Henkel	QoS-supported On-chip Communication for Multi-processors.	Int. J. Parallel Program.	2008	DBLP DOI BibTeX RDF	quality of services, Networks on chips, arbitration, multi-processor, service class
17	Marc Geilen, Twan Basten	Requirements on the Execution of Kahn Process Networks.	ESOP	2003	DBLP DOI BibTeX RDF	Kahn Principle, multi-processor architectures, streaming, signal processing, dynamic scheduling, media processing, Kahn process networks, deadlock resolution
17	Kam Hong Shum	Fault tolerant cluster computing through replication.	ICPADS	1997	DBLP DOI BibTeX RDF	fault tolerant cluster computing, runtime overhead, fault tolerance schemes, checkpoint states, fault tolerant model, Fujitsu AP3000 multi-processor machine, performance evaluation, replication, workstation clusters, workstation cluster, fault recovery, resource consumption, program termination
16	Xuli Liu	Exploiting Object-Based Parallelism on Multi-core Multi-processor Clusters.	PDCAT	2007	DBLP DOI BibTeX RDF
16	Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, Ingrid Verbauwhede	Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip.	ASAP	2006	DBLP DOI BibTeX RDF
16	Natalino G. Busá, Ghiath Alkadi, Michael J. Verberne, Rafael Peset Llopis, Sethuraman Ramanatha	RAPIDO: A Modular, Multi-Board, Heterogeneous Multi-Processor, PCI Bus Based Prototyping Framework for the Validation of SoC VLSI Designs.	IEEE International Workshop on Rapid System Prototyping	2002	DBLP DOI BibTeX RDF
16	Murali Annavaram, Ed Grochowski, John Paul Shen	Mitigating Amdahl's Law through EPI Throttling.	ISCA	2005	DBLP DOI BibTeX RDF
16	Yahya Jan, Lech Józwiak	Processor architecture exploration and synthesis of massively parallel multi-processor accelerators in application to LDPC decoding.	Microprocess. Microsystems	2014	DBLP DOI BibTeX RDF
16	Bill Penner	Multi-processor debug in SoC and processor designs.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
16	Mohammad Mahdi Jaghoori	From nonpreemptive to preemptive scheduling: from single-processor to multi-processor?	SAC	2011	DBLP DOI BibTeX RDF
16	Andreas Wieferink	Retargetable processor system integration into multi-processor system on chip platforms.		2008	RDF
16	Koichi Kashiwagi, Yoshinobu Higami, Shin-ya Kobayashi	A Consideration of Processor Utilization on Multi-Processor System.	Advances in Information Processing and Protection	2007	DBLP DOI BibTeX RDF
16	Arun Vijayaraghavan, M. Kannan, R. Seshasayanan	Simulation Analysis of Low Power Synchronous Token Ring Based VLIW processor under GALS Multi-processor technology with improved efficiency.	CDES	2005	DBLP BibTeX RDF
16	Andreas Wieferink, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Achim Nohl	A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform.	DATE	2004	DBLP DOI BibTeX RDF
16	Shunichiro Nakamura, Toshimune Kawanishi, Sunao Tanimoto, Yohtaro Miyanishi, Seiichi Saito	Improved Processor Synchronization for Multi-processor Traffic Simulator.	AsiaSim	2004	DBLP DOI BibTeX RDF
16	Guichang Zhong, Fan Xu, Alan N. Willson Jr.	An energy-efficient reconfigurable FFT/IFFT processor based on a multi-processor ring.	EUSIPCO	2004	DBLP BibTeX RDF
16	Ken-ichiro Murakami	A Pseudo Network Approach to Inter-processor Communication on a Shared-memory Multi-processor MacELIS.	Workshop on Parallel Lisp	1989	DBLP DOI BibTeX RDF
16	Giovanni Beltrame, Luca Fossati, Donatella Sciuto	Concurrency emulation and analysis of parallel applications for multi-processor system-on-chip co-design.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	ReSP, Operating System, Emulation, OpenMP, MPSoC, codesign
16	Pierre G. Paulin	Automatic Mapping of Parallel Applications onto Multi-Processor Platforms: A Multimedia Application.	DSD	2004	DBLP DOI BibTeX RDF
16	Roberto Airoldi, Fabio Garzia, Tapani Ahonen, Dragomir Milojevic, Jari Nurmi	Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management.	SAMOS	2009	DBLP DOI BibTeX RDF
16	Bassam Jamil Mohd, Earl E. Swartzlander Jr.	A Power-Scalable Switch-Based Multi-processor FFT.	ASAP	2009	DBLP DOI BibTeX RDF
16	Jun Wang, Hongbo Zeng, Kun Huang, Ge Zhang 0007, Yan Tang	Zero-Efficient Buffer Design for Reliable Network-on-Chip in Tiled Chip-Multi-Processor.	DATE	2008	DBLP DOI BibTeX RDF
16	Jiulong Shan, Yurong Chen 0001, Qian Diao, Yimin Zhang 0002	Parallel Information Extraction on Shared Memory Multi-processor System.	ICPP	2006	DBLP DOI BibTeX RDF
16	Chitra Natarajan, Bruce Christenson, Faye A. Briggs	A study of performance impact of memory controller features in multi-processor server environment.	WMPI	2004	DBLP DOI BibTeX RDF	memory transaction scheduling, server systems, multi-processors, memory controller, memory subsystem, performance impact
15	Noel Eisley, Vassos Soteriou, Li-Shiuan Peh	High-level power analysis for multi-core chips.	CASES	2006	DBLP DOI BibTeX RDF	simulation, chip multiprocessor (CMP), multi-core, power analysis, system-on-a-chip (SoC)
15	Hakduran Koc, Mahmut T. Kandemir, Ehat Ercanli, Ozcan Ozturk 0001	Reducing Off-Chip Memory Access Costs Using Data Recomputation in Embedded Chip Multi-processors.	DAC	2007	DBLP DOI BibTeX RDF
15	Peter J. Vidler, Michael J. Pont	Computer Assisted Source-Code Parallelisation.	ICCSA (5)	2006	DBLP DOI BibTeX RDF
14	Zhiyi Yu, Bevan M. Baas	Performance and Power Analysis of Globally Asynchronous Locally Synchronous Multi-Processor Systems.	ISVLSI	2006	DBLP DOI BibTeX RDF
14	Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi, Nikil D. Dutt	Methodology for multi-granularity embedded processor power model generation for an ESL design flow.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	system-on-chip, embedded processor, power modeling, esl
14	Masaitsu Nakajima, Takao Yamamoto, Masayuki Yamasaki, Tetsu Hosoki, Masaya Sumita	Low Power Techniques for Mobile Application SoCs Based on Integrated Platform "UniPhier".	ASP-DAC	2007	DBLP DOI BibTeX RDF
14	M. Chastain, G. Gostin, James E. Mankovich, Steven J. Wallach	The convex C240 architecture.	SC	1988	DBLP DOI BibTeX RDF
13	Ilya Wagner, Valeria Bertacco	MCjammer: Adaptive Verification for Multi-core Designs.	DATE	2008	DBLP DOI BibTeX RDF
13	Caixia Liu, Jiaxin Li, Hongli Zhang, Qi Zuo	HHMA: A Hierarchical Hybrid Memory Architecture Sharing Multi-Port Memory.	ICYCS	2008	DBLP DOI BibTeX RDF
13	Vijaykumar Ramamurthi, Jason McCollum, Christopher Ostler, Karam S. Chatha	System Level Methodology for Programming CMP Based Multi-Threaded Network Processor Architectures.	ISVLSI	2005	DBLP DOI BibTeX RDF
13	Kevin O'Brien, Kathryn M. O'Brien, Zehra Sura, Tong Chen 0001, Tao Zhang	Supporting OpenMP on Cell.	IWOMP	2007	DBLP DOI BibTeX RDF
13	Seng Lin Shee, Sri Parameswaran	Design Methodology for Pipelined Heterogeneous Multiprocessor System.	DAC	2007	DBLP DOI BibTeX RDF
13	Joël Rossier, Yann Thoma, Pierre-André Mudry, Gianluca Tempesti	MOVE Processors That Self-replicate and Differentiate.	BioADIT	2006	DBLP DOI BibTeX RDF
13	Andreas Hansson 0001, Kees Goossens, Marco Bekooij, Jos Huisken	CoMPSoC: A template for composable and predictable multi-processor system on chips.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	predictable, system on chip, network on chip, model of computation, Composable
13	Miroslav Manik, Elena Gramatová	Boolean Formalisation of the PMC Model for Faulty Units Diagnosis in Regular Multi-Processor Systems.	DDECS	2008	DBLP DOI BibTeX RDF
13	Sudeep Pasricha, Nikil D. Dutt	ORB: An on-chip optical ring bus communication architecture for multi-processor systems-on-chip.	ASP-DAC	2008	DBLP DOI BibTeX RDF
13	Sushu Zhang, Karam S. Chatha	Automated techniques for energy efficient scheduling on homogeneous and heterogeneous chip multi-processor architectures.	ASP-DAC	2008	DBLP DOI BibTeX RDF
13	Jung-Ho Lee, Sung-Rok Yoon, Kwang-Eui Pyun, Sin-Chong Park	A Multi-Processor NoC platform applied on the 802.11i TKIP cryptosystem.	ASP-DAC	2008	DBLP DOI BibTeX RDF