Search results for "multi-processors"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
31	Pierre-François Dutot	Hierarchical Scheduling for Moldable Tasks.	Euro-Par	2005	DBLP DOI BibTeX RDF
25	Paul Bogdan, Miray Kas, Radu Marculescu, Onur Mutlu	QuaLe: A Quantum-Leap Inspired Model for Non-stationary Analysis of NoC Traffic in Chip Multi-processors.	NOCS	2010	DBLP DOI BibTeX RDF	Self-Similar Stochastic Processes, Multi-fractal Analysis, Networks-on-Chip, Chip Multi-Processors
25	Anca Mariana Molnos, Sorin Dan Cotofana, Marc J. M. Heijligers, Jos T. J. van Eijndhoven	Static cache partitioning robustness analysis for embedded on-chip multi-processors.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	robustness, cache partitioning, multi-processors
21	Michael Yang, Ahmed N. Tantawy	A design methodology for protocol processors.	FTDCS	1995	DBLP DOI BibTeX RDF	protocol processors, FCS, Fibre Channel Standard, homogeneous multi-processors, single VLSI chip, VHDL macro libraries, VLSI protocol processors, CVDS, Communication VLSI Design System, protocols, asynchronous transfer mode, ATM, multiprocessing systems, communication protocols
21	Rajdeep Bhowmik, Chaitali Gupta, Madhusudhan Govindaraju, Aneesh Aggarwal	Optimizing XML processing for grid applications using an emulation framework.	IPDPS	2008	DBLP DOI BibTeX RDF
21	Rajdeep Bhowmik, Chaitali Gupta, Madhusudhan Govindaraju, Aneesh Aggarwal	Efficient XML-Based Grid Middleware Design for Multi-Core Processors.	ICWS	2007	DBLP DOI BibTeX RDF
17	Adrián Cristal, Oliverio J. Santana, Mateo Valero	Maintaining Thousands of In-flight Instructions.	Euro-Par	2004	DBLP DOI BibTeX RDF
17	Bart D. Theelen, A. C. Verschueren	Architecture Design of a Scalable Single-Chip Multi-Processor.	DSD	2002	DBLP DOI BibTeX RDF
16	Antony L. Hosking	Portable, mostly-concurrent, mostly-copying garbage collection for multi-processors.	ISMM	2006	DBLP DOI BibTeX RDF	ambiguous-roots, mostly-concurrent, mostly-copying, concurrent, garbage collection, memory management, portability, incremental, conservative
16	Shigeaki Iwasa, Shung Ho Shing, Hisashi Mogi, Hiroshi Nozuwe, Hiroo Hayashi, Osamu Wakamori, Takashi Ohmizo, Kuninori Tanaka, Hiroshi Sakai, Mitsuo Saito	SSM-MP: more scalability in shared-memory multi-processor.	ICCD	1995	DBLP DOI BibTeX RDF	SSM-MP, shared-memory multi-processor, cache refill latency, bus bottle neck problem, MTag, scalability, shared memory systems, cache coherency, memory architecture, multi-processor system
15	Ryo Watanabe, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya	Power reduction of chip multi-processors using shared resource control cooperating with DVFS.	ICCD	2007	DBLP DOI BibTeX RDF
15	Fengguang Song, Shirley Moore, Jack J. Dongarra	L2 Cache Modeling for Scientific Applications on Chip Multi-Processors.	ICPP	2007	DBLP DOI BibTeX RDF	cache performance modeling, architecture, chip multi-processor, multi-threaded programming
15	Ishwar Parulkar, Thomas A. Ziaja, Rajesh Pendurkar, Anand D'Souza, Amitava Majumdar 0002	A Scalable, Low Cost Design-for-Test Architecture for UltraSPARCTM Chip Multi-Processors.	ITC	2002	DBLP DOI BibTeX RDF
14	Hongbin Yang, Chen Li, Yue Wu	Research in Re-execution of the Thread Granule.	ISPA	2010	DBLP DOI BibTeX RDF	re-execution optimization, thread granule re-execution, Chip Multi-Processors
14	Pablo Abad Fidalgo, Valentin Puente, José-Ángel Gregorio, Pablo Prieto	Rotary router: an efficient architecture for CMP interconnection networks.	ISCA	2007	DBLP DOI BibTeX RDF	interconnection networks, router architecture, chip multi-processors
14	Chitra Natarajan, Bruce Christenson, Faye A. Briggs	A study of performance impact of memory controller features in multi-processor server environment.	WMPI	2004	DBLP DOI BibTeX RDF	memory transaction scheduling, server systems, multi-processors, memory controller, memory subsystem, performance impact
14	Takenori Koushiro, Toshinori Sato, Itsujiro Arita	A trace-level value predictor for Contrail processors.	SIGARCH Comput. Archit. News	2003	DBLP DOI BibTeX RDF	traceconstruction, energy efficiency, simultaneous multithreading, value prediction, chip multi processors
14	Tarek S. Abdelrahman, Thomas N. Wong	Compiler Support for Array Distribution on NUMA Shared Memory Multiprocessors.	J. Supercomput.	1998	DBLP DOI BibTeX RDF	locality management, NUMA multi-processors, parallelizing compilers, data distribution, cache management
14	Ireneusz Karkowski, Henk Corporaal	Exploiting Fine- and Coarse-Grain Parallelism in Embedded Programs.	IEEE PACT	1998	DBLP DOI BibTeX RDF	heterogeneous multi-processors, compilers for parallel systems, high performance embedded system design, application-specific architectures
14	Pengyong Ma, Shuming Chen	MID: a Novel Coherency Protocol in Chip Multiprocessor.	CIT	2006	DBLP DOI BibTeX RDF
14	Murali Annavaram, Ed Grochowski, John Paul Shen	Mitigating Amdahl's Law through EPI Throttling.	ISCA	2005	DBLP DOI BibTeX RDF
13	Stephen D. Craven, Cameron D. Patterson, Peter M. Athanas	A Methodology for Generating Application-Specific Heterogeneous Processor Arrays.	HICSS	2006	DBLP DOI BibTeX RDF
13	Soyeon Park, Yuanyuan Zhou 0001, Weiwei Xiong, Zuoning Yin, Rini Kaushik, Kyu H. Lee, Shan Lu 0001	PRES: probabilistic replay with execution sketching on multiprocessors.	SOSP	2009	DBLP DOI BibTeX RDF	replay, concurrency bug
13	Filip Blagojevic, Matthew Curtis-Maury, Jae-Seung Yeom, Scott Schneider 0001, Dimitrios S. Nikolopoulos	Scheduling Asymmetric Parallelism on a PlayStation3 Cluster.	CCGRID	2008	DBLP DOI BibTeX RDF	Performance Modeling, Process Scheduling, Cell BE
13	Carlos Pérez-Miguel, José Miguel-Alonso, Alexander Mendiburu	Evaluating the cell broadband engine as a platform to run estimation of distribution algorithms.	GECCO (Companion)	2009	DBLP DOI BibTeX RDF	parallel programming, estimation of distribution algorithms, cell broadband engine
12	Shashank Jaiswal, Jingwei Hu, Julien K. Brillon, Alina A. Alexeenko	A Discontinuous Galerkin Fast Spectral Method for Multi-Species Full Boltzmann on Streaming Multi-Processors.	PASC	2019	DBLP DOI BibTeX RDF
12	Wei Ding	The makespan problem of scheduling multi groups of jobs on multi processors at different speeds.	Algorithmic Oper. Res.	2012	DBLP BibTeX RDF
12	Scott Cotton, Oded Maler, Julien Legriel, Selma Saidi	Multi-criteria optimization for mapping programs to multi-processors.	SIES	2011	DBLP DOI BibTeX RDF
12	Wei Ding, Yi Zhao	An improved LS algorithm for the problem of scheduling multi groups of jobs on multi processors at the same speed.	Algorithmic Oper. Res.	2010	DBLP BibTeX RDF
12	J. Dobbie, D. Zatyko	System optimization: A mass memory system designed for the multi-program/multi-processors users.	ACM National Conference	1965	DBLP DOI BibTeX RDF
11	Richard T. Saunders, Clinton L. Jeffery, Derek T. Jones	A Portable Framework for High-Speed Parallel Producer/Consumers on Real CMP, SMT and SMP Architectures.	IPDPS	2007	DBLP DOI BibTeX RDF
11	Ali El-Moursy, Rajeev Garg, David H. Albonesi, Sandhya Dwarkadas	Compatible phase co-scheduling on a CMP of multi-threaded processors.	IPDPS	2006	DBLP DOI BibTeX RDF
11	Inki Hong, Miodrag Potkonjak, Ramesh Karri	A heterogeneous built-in self-repair approach using system-level synthesis flexibility.	IEEE Trans. Reliab.	2004	DBLP DOI BibTeX RDF
11	Wolfgang Puffitsch	Decoupled root scanning in multi-processor systems.	CASES	2008	DBLP DOI BibTeX RDF	real-time, garbage collection, multi-processor
11	Luke K. McDowell, Susan J. Eggers, Steven D. Gribble	Improving server software support for simultaneous multithreaded processors.	PPoPP	2003	DBLP DOI BibTeX RDF	servers, simultaneous multithreading, runtime support
11	Rodrigo P. Mendonça, Mario A. R. Dantas	A Study of Adaptive Co-scheduling Approach for an Opportunistic Software Environment to Execute in Multi-core and Multi-Processor Configurations.	CSE	2008	DBLP DOI BibTeX RDF	multi-core, metacomputing, co-scheduling
10	Jianyu Wei, Ting Cao, Shijie Cao, Shiqi Jiang, Shaowei Fu, Mao Yang, Yanyong Zhang, Yunxin Liu	NN-Stretch: Automatic Neural Network Branching for Parallel Inference on Heterogeneous Multi-Processors.	MobiSys	2023	DBLP DOI BibTeX RDF
10	Furat Al-Obaidy, Arghavan Asad, Farah A. Mohammadi	A Power-Aware Hybrid Cache for Chip-Multi Processors Based on Neural Network Prediction Technique.	Int. J. Parallel Program.	2021	DBLP DOI BibTeX RDF
10	Wanjuan Wang	Government ecological governance management based on heterogeneous multi-processors and dynamic image sampling.	Microprocess. Microsystems	2021	DBLP DOI BibTeX RDF
10	Jie Zhang 0048, Myoungsoo Jung	Ohm-GPU: Integrating New Optical Network and Heterogeneous Memory into GPU Multi-Processors.	CoRR	2021	DBLP BibTeX RDF
10	Jie Zhang 0048, Myoungsoo Jung	Ohm-GPU: Integrating New Optical Network and Heterogeneous Memory into GPU Multi-Processors.	MICRO	2021	DBLP DOI BibTeX RDF
10	Zhe Lin 0007, Sharad Sinha, Hao Liang 0003, Liang Feng 0001, Wei Zhang 0012	Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-Processors.	CoRR	2020	DBLP BibTeX RDF
10	Jie Zhang 0048, Myoungsoo Jung	ZnG: Architecting GPU Multi-Processors with New Flash for Scalable Data Analysis.	CoRR	2020	DBLP BibTeX RDF
10	Augusto Vega, Aporva Amarnath, John-David Wellman, Hiwot Kassa, Subhankar Pal, Hubertus Franke, Alper Buyuktosunoglu, Ronald G. Dreslinski, Pradip Bose	STOMP: A Tool for Evaluation of Scheduling Policies in Heterogeneous Multi-Processors.	CoRR	2020	DBLP BibTeX RDF
10	Agostino Mascitti, Tommaso Cucinotta, Luca Abeni	Heuristic partitioning of real-time tasks on multi-processors.	ISORC	2020	DBLP DOI BibTeX RDF
10	Abhijit Das 0002, Abhishek Kumar, John Jose, Maurizio Palesi	Exploiting On-Chip Routers to Store Dirty Cache Blocks in Tiled Chip Multi-processors.	ISVLSI	2020	DBLP DOI BibTeX RDF
10	Jie Zhang 0048, Myoungsoo Jung	ZnG: Architecting GPU Multi-Processors with New Flash for Scalable Data Analysis.	ISCA	2020	DBLP DOI BibTeX RDF
10	Johanna Sepúlveda, Felix Wilgerodt, Michael Pehl	Towards memory integrity and authenticity of multi-processors system-on-chip using physical unclonable functions.	it Inf. Technol.	2019	DBLP DOI BibTeX RDF
10	Furat Al-Obaidy, Arghavan Asad, Farah Mohammadi 0001	Reconfigurable Hybrid Cache Hierarchy in 3D Chip-Multi Processors Based on a Convex optimization Method.	CCECE	2019	DBLP DOI BibTeX RDF
10	Furat Al-Obaidy, Arghavan Asad, Farah Mohammadi 0001	Power-Management based on Reconfigurable Last-Cache level on Non-volatile Memories in Chip-Multi processors.	CCECE	2019	DBLP DOI BibTeX RDF
10	Zhe Lin 0007, Sharad Sinha, Hao Liang 0003, Liang Feng 0001, Wei Zhang 0012	Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-Processors.	IEEE Trans. Multi Scale Comput. Syst.	2018	DBLP DOI BibTeX RDF
10	Ashwini A. Kulkarni, Chirag Joshi, Khushboo Rani, Sukarn Agarwal, Shrinivas P. Mahajan, Hemangee K. Kapoor	Towards Analysing the Effect of Snoozy Caches on the Temperature of Tiled Chip Multi-Processors.	ISED	2018	DBLP DOI BibTeX RDF
10	Ying Wang 0001, Wen Li, Huawei Li 0001, Xiaowei Li 0001	Leveraging DRAM Refresh to Protect the Memory Timing Channel of Cloud Chip Multi-processors.	ITC-Asia	2018	DBLP DOI BibTeX RDF
10	Ashwini A. Kulkarni, Shounak Chakraborty 0001, Shrinivas P. Mahajan, Hemangee K. Kapoor	Utility Aware Snoozy Caches for Energy Efficient Chip Multi-Processors.	ACM Great Lakes Symposium on VLSI	2018	DBLP DOI BibTeX RDF
10	Johanna Sepúlveda, Felix Wilgerodt, Michael Pehl	SEPUFSoC: Using PUFs for Memory Integrity and Authentication in Multi-Processors System-on-Chip.	ACM Great Lakes Symposium on VLSI	2018	DBLP DOI BibTeX RDF
10	Ashwini A. Kulkarni, Khushboo Rani, Sukarn Agarwal, Shrinivas P. Mahajan, Hemangee K. Kapoor	Towards Analysing the Effect of Hybrid Caches on the Temperature of Tiled Chip Multi-Processors.	iSES	2018	DBLP DOI BibTeX RDF
10	Milad Ghorbani Moghaddam, Cristinel Ababei	Dynamic energy management for chip multi-processors under performance constraints.	Microprocess. Microsystems	2017	DBLP DOI BibTeX RDF
10	Yanhua Li, Youhui Zhang, Cihang Jiang, Weiming Zheng	Hardware support for message-passing in chip multi-processors.	Int. J. High Perform. Comput. Netw.	2017	DBLP DOI BibTeX RDF
10	Jalal Khamse-Ashari, George Kesidis, Ioannis Lambadaris, Bhuvan Urgaonkar, Yiqiang Q. Zhao	Efficient and fair scheduling of placement constrained threads on heterogeneous multi-processors.	INFOCOM Workshops	2017	DBLP DOI BibTeX RDF
10	Bing Li 0005	W3B: Special session: Secure multi-processors systems-on-chip for critical applications.	SoCC	2017	DBLP DOI BibTeX RDF
10	Naga Durga Prasad Avirneni, Prem Kumar Ramesh, Arun K. Somani	Utilization Aware Power Management in Reliable and Aggressive Chip Multi Processors.	IEEE Trans. Computers	2016	DBLP DOI BibTeX RDF
10	Hrishikesh Salunkhe, Alok Lele, Orlando Moreira, Kees van Berkel 0001	Buffer allocation for real-time streaming applications running on heterogeneous multi-processors without back-pressure.	J. Syst. Archit.	2016	DBLP DOI BibTeX RDF
10	Ying Wang 0001, Huawei Li 0001, Xiaowei Li 0001	Frequency scheduling for resilient chip multi-processors operating at Near Threshold Voltage.	DATE	2016	DBLP BibTeX RDF
10	Anastasios Psarras, Junghee Lee, Pavlos M. Mattheakis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos	A Low-Power Network-on-Chip Architecture for Tile-based Chip Multi-Processors.	ACM Great Lakes Symposium on VLSI	2016	DBLP DOI BibTeX RDF
10	Ying Wang 0001, Yinhe Han 0001, Jun Zhou 0022, Huawei Li 0001, Xiaowei Li 0001	DISCO: a low overhead in-network data compressor for energy-efficient chip multi-processors.	DAC	2016	DBLP DOI BibTeX RDF
10	Minhui Lv, Wei Xiong	Cache-Aware Spatial Indices on Chip Multi-Processors: Limitations and Opportunities.	CyberC	2016	DBLP DOI BibTeX RDF
10	Tripti S. Warrier, Kanakagiri Raghavendra, Madhu Mutyam	SkipCache: application aware cache management for chip multi-processors.	IET Comput. Digit. Tech.	2015	DBLP DOI BibTeX RDF
10	Vijayalakshmi Saravanan, Alagan Anpalagan, Isaac Woungang	An energy-delay product study on chip multi-processors for variable stage pipelining.	Hum. centric Comput. Inf. Sci.	2015	DBLP DOI BibTeX RDF
10	Milan Patnaik, Chidhambaranathan Rajamanikkam, Chirag Garg, Arnab Roy 0003, V. R. Devanathan, Shankar Balachandran, V. Kamakoti 0001	ProWATCh: A Proactive Cross-Layer Workload-Aware Temperature Management Framework for Low-Power Chip Multi-Processors.	ACM J. Emerg. Technol. Comput. Syst.	2015	DBLP DOI BibTeX RDF
10	Arghavan Asad, Ozcan Ozturk 0001, Mahmood Fathy, Mohammad Reza Jahed-Motlagh	Exploiting Heterogeneity in Cache Hierarchy in Dark-Silicon 3D Chip Multi-processors.	DSD	2015	DBLP DOI BibTeX RDF
10	Ashkan Sadeghi, Kaamran Raahemifar, Mahmood Fathy, Arghavan Asad	Lighting the Dark-Silicon 3D Chip Multi-processors by Exploiting Heterogeneity in Cache Hierarchy.	MCSoC	2015	DBLP DOI BibTeX RDF
10	Michael A. Skitsas, Chrysostomos Nicopoulos, Maria K. Michael	Toward efficient check-pointing and rollback under on-demand SBST in chip multi-processors.	IOLTS	2015	DBLP DOI BibTeX RDF
10	Yuang Zhang, Li Li 0003, Zhonghai Lu, Axel Jantsch, Minglun Gao, Hongbing Pan, Feng Han 0008	A survey of memory architecture for 3D chip multi-processors.	Microprocess. Microsystems	2014	DBLP DOI BibTeX RDF
10	Mohamed Issa, Ahmed Mansour Alzohairy	Tracing Origins Of Unknown DNA/Protein Offspring Sequences On Multi-Processors.	ICCTA	2014	DBLP DOI BibTeX RDF
10	Gang Wang, Xu Wang, Xinke Chen, Shuangbai Xue	Test and Repair Flow for Shared BISR in Asynchronous Multi-processors.	ASYNC	2014	DBLP DOI BibTeX RDF
10	Malik Al-Manasia, Zenon Chaczko	An Overview of Chip Multi-Processors Simulators Technology.	ICSEng	2014	DBLP DOI BibTeX RDF
10	Lech Józwiak, Yahya Jan	Design of massively parallel hardware multi-processors for highly-demanding embedded applications.	Microprocess. Microsystems	2013	DBLP DOI BibTeX RDF
10	Filippo Sironi, Martina Maggio, Riccardo Cattaneo, Giovanni F. Del Nero, Donatella Sciuto, Marco D. Santambrogio	ThermOS: System support for dynamic thermal management of chip multi-processors.	PACT	2013	DBLP DOI BibTeX RDF
10	Bharathwaj Raghunathan, Yatish Turakhia, Siddharth Garg, Diana Marculescu	Cherry-picking: exploiting process variations in dark-silicon homogeneous chip multi-processors.	DATE	2013	DBLP DOI BibTeX RDF
10	Yatish Turakhia, Bharathwaj Raghunathan, Siddharth Garg, Diana Marculescu	HaDeS: architectural synthesis for heterogeneous dark silicon chip multi-processors.	DAC	2013	DBLP DOI BibTeX RDF
10	Chiahsun Ho	Reducing scheduling overheads in multi-processors real-time systems.		2013	RDF
10	Hong-Yun Kim, Young-Jun Kim 0001, Lee-Sup Kim	MRTP: Mobile Ray Tracing Processor With Reconfigurable Stream Multi-Processors for High Datapath Utilization.	IEEE J. Solid State Circuits	2012	DBLP DOI BibTeX RDF
10	Wael Kdouh, Hesham El-Rewini	Reliability-aware platform optimization for 3D chip multi-processors.	J. Supercomput.	2012	DBLP DOI BibTeX RDF
10	Yahya Jan, Lech Józwiak	Scalable communication architectures for massively parallel hardware multi-processors.	J. Parallel Distributed Comput.	2012	DBLP DOI BibTeX RDF
10	Bruno Girodias, Luiza Gheorghe Iugan, Youcef Bouchebaba, Gabriela Nicolescu, El Mostapha Aboulhamid, Michel Langevin, Pierre G. Paulin	Integrating Memory Optimization with Mapping Algorithms for Multi-Processors System-on-Chip.	ACM Trans. Embed. Comput. Syst.	2012	DBLP DOI BibTeX RDF
10	Moo-Ryong Ra, Bodhi Priyantha, Aman Kansal, Jie Liu 0001	Improving energy efficiency of personal sensing applications with heterogeneous multi-processors.	UbiComp	2012	DBLP DOI BibTeX RDF
10	Mengjie Mao, Hong An, Tao Sun, Qi Li 0034, Bobin Deng, Xuechao Wei, Junrui Zhou	Distributed Control Independence for Composable Multi-processors.	ACIS-ICIS	2012	DBLP DOI BibTeX RDF
10	Hossein Khezripour, Saadat Pourmozaffari	Fault Tolerance and Power Consumption Analysis on Chip-Multi Processors Architectures.	ARES	2012	DBLP DOI BibTeX RDF
10	Weixing Ji, Yizhuo Wang, Zhi Huang, Junqing Zhao, Xi Li	Exploring Object-Level Parallelism on Chip Multi-processors.	ICA3PP (2)	2012	DBLP DOI BibTeX RDF
10	Rahim Soleymanpour, Siamak Mohammadi, Hamed Rajabi	A synthesis algorithm for customized heterogeneous multi-processors.	ISOCC	2012	DBLP DOI BibTeX RDF
10	Moslem Didehban, Ario Sadafi, Sajjad Salehi, Mohammad Bagher Chami	A Gate Level Analysis of Transient Faults Effects on Dual-Core Chip-Multi Processors.	ARES	2011	DBLP DOI BibTeX RDF
10	Marek Tudruj, Lukasz Masko	Communication on the Fly for Hierarchical Systems of Chip Multi-processors.	PARELEC	2011	DBLP DOI BibTeX RDF
10	Arvind Kandhalu, Junsung Kim, Karthik Lakshmanan, Ragunathan Rajkumar	Energy-Aware Partitioned Fixed-Priority Scheduling for Chip Multi-processors.	RTCSA (1)	2011	DBLP DOI BibTeX RDF
10	Marek Tudruj, Lukasz Masko	Data Transfers on the Fly for Hierarchical Systems of Chip Multi-Processors.	PPAM (1)	2011	DBLP DOI BibTeX RDF
10	Lothar Thiele, Lars Schor, Hoeseok Yang, Iuliana Bacivarov	Thermal-aware system analysis and software synthesis for embedded multi-processors.	DAC	2011	DBLP DOI BibTeX RDF
10	Chao Wang 0003, Junneng Zhang, Xuehai Zhou, Xiaojing Feng, Xiaoning Nie	SOMP: Service-Oriented Multi Processors.	IEEE SCC	2011	DBLP DOI BibTeX RDF	Service-oriented, Run-time reconfiguration, Run-time scheduling, Multi processor system on chip
10	Junli Gu, Rakesh Kumar 0002, Steven S. Lumetta, Yihe Sun	Accelerating data movement on future chip multi-processors.	IFMT	2010	DBLP DOI BibTeX RDF
10	Vittorio Zaccaria, Gianluca Palermo, Fabrizio Castro, Cristina Silvano, Giovanni Mariani	Multicube Explorer: An Open Source Framework for Design Space Exploration of Chip Multi-Processors.	ARCS Workshops	2010	DBLP BibTeX RDF
10	Bruno Girodias, Luiza Gheorghe, Youcef Bouchebaba, Gabriela Nicolescu, El Mostapha Aboulhamid, Michel Langevin, Pierre G. Paulin	Combining memory optimization with mapping of multimedia applications for multi-processors system-on-chip.	International Symposium on Rapid System Prototyping	2010	DBLP DOI BibTeX RDF
10	Claudio Favi, René Beuchat, Xavier Jimenez, Paolo Ienne	From gates to multi-processors learning systems hands-on with FPGA4U in a computer science programme.	WESE@ESWEEK	2009	DBLP DOI BibTeX RDF