Search results for "nbti"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
144	Andrea Calimera, Enrico Macii, Massimo Poncino	NBTI-aware sleep transistor design for reliable power-gating.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	reliability, sizing, sleep-transistor, nbti
138	Wenping Wang, Shengqi Yang, Yu Cao 0001	Node Criticality Computation for Circuit Timing Analysis and Optimization under NBTI Effect.	ISQED	2008	DBLP DOI BibTeX RDF
129	Basab Datta, Wayne P. Burleson	Analysis and mitigation of NBTI-impact on PVT variability in repeated global interconnect performance.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	tunable buffer, variability, NBTI, global-interconnect
129	Hamed Abrishami, Safar Hatami, Behnam Amelifard, Massoud Pedram	NBTI-aware flip-flop characterization and design.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	device aging, setup and hold times, static timing analysis, NBTI, circuit reliability
114	Taniya Siddiqua, Sudhanva Gurumurthi	A multi-level approach to reduce the impact of NBTI on processor functional units.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	reliability, NBTI
114	Rakesh Vattikonda, Wenping Wang, Yu Cao 0001	Modeling and minimization of PMOS NBTI effect for robust nanometer design.	DAC	2006	DBLP DOI BibTeX RDF	reliability, variability, temperature, performance degradation, NBTI, threshold voltage
108	Yu Wang 0002, Xiaoming Chen 0003, Wenping Wang, Varsha Balakrishnan, Yu Cao 0001, Yuan Xie 0001, Huazhong Yang	On the efficacy of input Vector Control to mitigate NBTI effects and leakage power.	ISQED	2009	DBLP DOI BibTeX RDF
108	Kunhyuk Kang, Saakshi Gangwal, Sang Phill Park, Kaushik Roy 0001	NBTI induced performance degradation in logic and memory circuits: how effectively can we approach a reliability solution?	ASP-DAC	2008	DBLP DOI BibTeX RDF
106	Kunhyuk Kang, Haldun Kufluoglu, Kaushik Roy 0001, Muhammad Ashraful Alam	Impact of Negative-Bias Temperature Instability in Nanoscale SRAM Array: Modeling and Analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
99	Ashutosh Chakraborty, David Z. Pan	Skew management of NBTI impacted gated clock trees.	ISPD	2010	DBLP DOI BibTeX RDF	clock skew, clock gating, NBTI
99	Andrea Calimera, Enrico Macii, Massimo Poncino	NBTI-aware power gating for concurrent leakage and aging optimization.	ISLPED	2009	DBLP DOI BibTeX RDF	aging, leakage, power-gating, nbti
99	Zhenyu Qi, Mircea R. Stan	NBTI resilient circuits using adaptive body biasing.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	reliability, body bias, nbti
99	John Keane 0001, Tony Tae-Hyoung Kim, Chris H. Kim	An on-chip NBTI sensor for measuring PMOS threshold voltage degradation.	ISLPED	2007	DBLP DOI BibTeX RDF	locked loop, delay, aging, NBTI
99	Yiran Chen 0001, Hai Li 0001, Jing Li 0073, Cheng-Kok Koh	Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI.	ISLPED	2007	DBLP DOI BibTeX RDF	variable-latency adder (VL-adder), negative bias temperature instability (NBTI)
96	Xiaoming Chen 0003, Yu Wang 0002, Yu Cao 0001, Yuchun Ma, Huazhong Yang	Variation-aware supply voltage assignment for minimizing circuit degradation and leakage.	ISLPED	2009	DBLP DOI BibTeX RDF	dynamic vdd scaling, leakage power, negative bias temperature instability (NBTI), dual vdd
93	Shubhankar Basu, Ranga Vemuri	Process Variation and NBTI Tolerant Standard Cells to Improve Parametric Yield and Lifetime of ICs.	ISVLSI	2007	DBLP DOI BibTeX RDF
93	Xiangning Yang, Kewal K. Saluja	Combating NBTI Degradation via Gate Sizing.	ISQED	2007	DBLP DOI BibTeX RDF
93	Wenping Wang, Shengqi Yang, Sarvesh Bhardwaj, Rakesh Vattikonda, Sarma B. K. Vrudhula, Frank Liu 0001, Yu Cao 0001	The Impact of NBTI on the Performance of Combinational and Sequential Circuits.	DAC	2007	DBLP DOI BibTeX RDF
91	Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar	An analytical model for negative bias temperature instability.	ICCAD	2006	DBLP DOI BibTeX RDF
84	Bin Zhang 0011, Michael Orshansky	Modeling of NBTI-Induced PMOS Degradation under Arbitrary Dynamic Temperature Variation.	ISQED	2008	DBLP DOI BibTeX RDF	temperature variation, NBTI
84	Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar	Impact of NBTI on SRAM Read Stability and Design for Reliability.	ISQED	2006	DBLP DOI BibTeX RDF	Static Noise Margin (SNM), Reaction-Diffusion (R-D) Model, Cache, SRAM, Negative Bias Temperature Instability (NBTI)
78	Yu Wang 0002, Hong Luo, Ku He, Rong Luo, Huazhong Yang, Yuan Xie 0001	Temperature-aware NBTI modeling and the impact of input vector control on performance degradation.	DATE	2007	DBLP DOI BibTeX RDF
78	Jaume Abella 0001, Xavier Vera, Antonio González 0001	Penelope: The NBTI-Aware Processor.	MICRO	2007	DBLP DOI BibTeX RDF
78	Kunhyuk Kang, Sang Phill Park, Kaushik Roy 0001, Muhammad Ashraful Alam	Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance.	ICCAD	2007	DBLP DOI BibTeX RDF
78	Rakesh Vattikonda, Yansheng Luo, Alex Gyure, Xiaoning Qi, Sam C. Lo, Mahmoud Shahram, Yu Cao 0001, Kishore Singhal, Dino Toffolon	A New Simulation Method for NBTI Analysis in SPICE Environment.	ISQED	2007	DBLP DOI BibTeX RDF
78	Hong Luo, Yu Wang 0002, Ku He, Rong Luo, Huazhong Yang, Yuan Xie 0001	Modeling of PMOS NBTI Effect Considering Temperature Variation.	ISQED	2007	DBLP DOI BibTeX RDF
78	Xiangning Yang, Eric F. Weglarz, Kewal K. Saluja	On NBTI Degradation Process in Digital Logic Circuits.	VLSI Design	2007	DBLP DOI BibTeX RDF
78	Kunhyuk Kang, Keejong Kim, Ahmad E. Islam, Muhammad Ashraful Alam, Kaushik Roy 0001	Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement.	DAC	2007	DBLP DOI BibTeX RDF
78	Bipul Chandra Paul, Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy 0001	Temporal performance degradation under NBTI: estimation and design for improved reliability of nanoscale circuits.	DATE	2006	DBLP DOI BibTeX RDF
69	Mehmet Basoglu, Michael Orshansky, Mattan Erez	NBTI-aware DVFS: a new approach to saving energy and increasing processor lifetime.	ISLPED	2010	DBLP DOI BibTeX RDF	wearout, energy efficiency, process variation, DVFS, NBTI
69	Basab Datta, Wayne P. Burleson	Circuit-level NBTI macro-models for collaborative reliability monitoring.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	macro-models, on-chip sensors, calibration, NBTI
69	Zhenyu Qi, Jiajing Wang, Adam C. Cabe, Stuart N. Wooters, Travis N. Blalock, Benton H. Calhoun, Mircea R. Stan	SRAM-based NBTI/PBTI sensor system design.	DAC	2010	DBLP DOI BibTeX RDF	PBTI, sensor system design, sensor, redundancy, process variation, aging, yield, SRAM, NBTI
63	Michael DeBole, Krishnan Ramakrishnan, Varsha Balakrishnan, Wenping Wang, Hong Luo, Yu Wang 0002, Yuan Xie 0001, Yu Cao 0001, Narayanan Vijaykrishnan	A framework for estimating NBTI degradation of microarchitectural components.	ASP-DAC	2009	DBLP DOI BibTeX RDF
63	Balaji Vaidyanathan, Anthony S. Oates, Yuan Xie 0001, Yu Wang 0002	NBTI-aware statistical circuit delay assessment.	ISQED	2009	DBLP DOI BibTeX RDF
63	Jin Sun 0006, Avinash Karanth Kodi, Ahmed Louri, Janet Meiling Wang	NBTI aware workload balancing in multi-core systems.	ISQED	2009	DBLP DOI BibTeX RDF
63	Alexander L. Stempkovsky, Alexey Glebov, Sergey Gavrilov	Calculation of stress probability for NBTI-aware timing analysis.	ISQED	2009	DBLP DOI BibTeX RDF
63	Xin Fu, Tao Li 0006, José A. B. Fortes	NBTI tolerant microarchitecture design in the presence of process variation.	MICRO	2008	DBLP DOI BibTeX RDF
63	Krishnan Ramakrishnan, Xiaoxia Wu, Narayanan Vijaykrishnan, Yuan Xie 0001	Comparative analysis of NBTI effects on low power and high performance flip-flops.	ICCD	2008	DBLP DOI BibTeX RDF
63	Kewal K. Saluja, Shriram Vijayakumar, Warin Sootkaneung, Xaingning Yang	NBTI Degradation: A Problem or a Scare?	VLSI Design	2008	DBLP DOI BibTeX RDF
63	Krishnan Ramakrishnan, Sivaprakasam Suresh, Narayanan Vijaykrishnan, Mary Jane Irwin	Impact of NBTI on FPGAs.	VLSI Design	2007	DBLP DOI BibTeX RDF
60	Bipul Chandra Paul, Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy 0001	Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
60	Wenping Wang, Zile Wei, Shengqi Yang, Yu Cao 0001	An efficient method to identify critical gates under circuit aging.	ICCAD	2007	DBLP DOI BibTeX RDF
59	Yu Wang 0002, Hong Luo, Ku He, Rong Luo, Huazhong Yang, Yuan Xie 0001	Temperature-Aware NBTI Modeling and the Impact of Standby Leakage Reduction Techniques on Circuit Performance Degradation.	IEEE Trans. Dependable Secur. Comput.	2011	DBLP DOI BibTeX RDF	temperature-aware NBTI modeling, circuit performance degradation, Negative bias temperature instability (NBTI), leakage reduction
53	Karthik Duraisami, Enrico Macii, Massimo Poncino	Using soft-edge flip-flops to compensate NBTI-induced delay degradation.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	device aging, seff, setup and hold time, flip-flop, circuit reliability, nbti
48	Anuj Pushkarna, Hamid Mahmoodi	Reliability analysis of power gated SRAM under combined effects of NBTI and PBTI in nano-scale CMOS.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	reliability, aging, SRAM, power gating
48	Andrea Marongiu, Andrea Acquaviva, Luca Benini	OpenMP Support for NBTI-Induced Aging Tolerance in MPSoCs.	SSS	2009	DBLP DOI BibTeX RDF
48	Lide Zhang, Robert P. Dick	Scheduled voltage scaling for increasing lifetime in the presence of NBTI.	ASP-DAC	2009	DBLP DOI BibTeX RDF
48	Adam C. Cabe, Zhenyu Qi, Stuart N. Wooters, Travis N. Blalock, Mircea R. Stan	Small embeddable NBTI sensors (SENS) for tracking on-chip performance decay.	ISQED	2009	DBLP DOI BibTeX RDF
48	Hong Luo, Yu Wang 0002, Ku He, Rong Luo, Huazhong Yang, Yuan Xie 0001	A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect.	PATMOS	2007	DBLP DOI BibTeX RDF
48	Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar	NBTI-Aware Synthesis of Digital Circuits.	DAC	2007	DBLP DOI BibTeX RDF
45	Andrea Calimera, Mirko Loghi, Enrico Macii, Massimo Poncino	Aging effects of leakage optimizations for caches.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	memory hierarchy, aging, leakage reduction
45	Subhasish Mitra	Circuit Failure Prediction Enables Robust System Design Resilient to Aging and Wearout.	IOLTS	2007	DBLP DOI BibTeX RDF
45	Mridul Agarwal, Bipul C. Paul, Ming Zhang, Subhasish Mitra	Circuit Failure Prediction and Its Application to Transistor Aging.	VTS	2007	DBLP DOI BibTeX RDF
36	Andrea Calimera, Mirko Loghi, Enrico Macii, Massimo Poncino	Dynamic indexing: concurrent leakage and aging optimization for caches.	ISLPED	2010	DBLP DOI BibTeX RDF	leakage optimization, memory hierarchy, aging, NBTI
36	Martin Omaña 0001, Daniele Rossi 0001, Nicolò Bosio, Cecilia Metra	Novel low-cost aging sensor.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	aging sensor, performance degradation, nbti
36	Arjun Rajagopal	Clock tree design challenges for robust and low power design.	ISPD	2006	DBLP DOI BibTeX RDF	NBTI, IR drop
36	Zhihong Liu, Bruce McGaughy, James Z. Ma	Design tools for reliability analysis.	DAC	2006	DBLP DOI BibTeX RDF	design-in reliability, reliability simulation, HCI, EM, NBTI
36	Toshinari Takayanagi, Jinuk Luke Shin, Bruce Petrick, Jeffrey Y. Su, Ana Sonia Leon	A dual-core 64b ultraSPARC microprocessor for dense server applications.	DAC	2004	DBLP DOI BibTeX RDF	L2, UltraSPARC, coupling noise, deep submicron technology, dense server, dual-core, throughput computing, cache, multiprocessor, leakage, NBTI, negative bias temperature instability
35	Gyusung Park, Hanzhao Yu, Minsu Kim, Chris H. Kim	An All BTI (N-PBTI, N-NBTI, P-PBTI, P-NBTI) Odometer based on a Dual Power Rail Ring Oscillator Array.	IRPS	2021	DBLP DOI BibTeX RDF
35	Katerina Katsarou, Yiorgos Tsiatouhas, Angela Arapoyanni	NBTI aging tolerance in pipeline based designs NBTI.	IOLTS	2013	DBLP DOI BibTeX RDF
35	Eisuke Saneyoshi, Koichi Nose, Masayuki Mizuno	A precise-tracking NBTI-degradation monitor independent of NBTI recovery effect.	ISSCC	2010	DBLP DOI BibTeX RDF
33	Ronald Carlsten, Jeremy Ralston-Good, Douglas Goodman	An Approach to Detect Negative Bias Temperature Instability (NBTI) in Ultra-Deep Submicron Technologies.	ISCAS	2007	DBLP DOI BibTeX RDF
30	Krishnan Ramakrishnan, R. Rajaraman, Sivaprakasam Suresh, Narayanan Vijaykrishnan, Yuan Xie 0001, Mary Jane Irwin	Variation Impact on SER of Combinational Circuits.	ISQED	2007	DBLP DOI BibTeX RDF
21	Guihai Yan, Yinhe Han 0001, Xiaowei Li 0001	ReviveNet: A Self-Adaptive Architecture for Improving Lifetime Reliability via Localized Timing Adaptation.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF	Lifetime reliability, aging sensor, self-adaptive, NBTI, timing adaptation
21	Edward A. Stott, Peter Y. K. Cheung	Improving FPGA Reliability with Wear-Levelling.	FPL	2011	DBLP DOI BibTeX RDF	FPGA, Reliability, NBTI, Degradation, Wear Levelling
21	Amlan Ghosh, Rob Franklin, Richard B. Brown	Analog Circuit Design Methodologies to Improve Negative-Bias Temperature Instability Degradation.	VLSI Design	2010	DBLP DOI BibTeX RDF	analog circuit design methodologies, input switching, NBTI, body biasing
21	Yinghai Lu, Li Shang, Hai Zhou 0001, Hengliang Zhu, Fan Yang 0001, Xuan Zeng 0001	Statistical reliability analysis under process variation and aging effects.	DAC	2009	DBLP DOI BibTeX RDF	process variations, yield, NBTI
21	Thomas Pompl, Christian Schlünder, Martina Hommel, Heiko Nielen, Jens Schneider	Practical aspects of reliability analysis for IC designs.	DAC	2006	DBLP DOI BibTeX RDF	ESD, TDDB of intermetal dielectric, design-in reliability, gate oxide integrity, hot carrier stress, stress-induced voiding, NBTI, electromigration
18	Daniele Placido, Gianluca De Marzi, Luigi Muzzi, Laura Savoldi	Techno-Economic Optimization of the NbTi DTT Feeders.	IEEE Access	2023	DBLP DOI BibTeX RDF
18	Daniele Placido, Gianluca De Marzi, Luigi Muzzi, Laura Savoldi	Corrections to "Techno-Economic Optimization of the NbTi DTT Feeders".	IEEE Access	2023	DBLP DOI BibTeX RDF
18	Hui Xu, Rui Zhu, Xia Sun, Xianjin Fang, Pan Qi, Huaguo Liang, Zhengfeng Huang	Novel Critical Gate-Based Circuit Path-Level NBTI-Aware Aging Circuit Degradation Prediction.	J. Circuits Syst. Comput.	2023	DBLP DOI BibTeX RDF
18	Huimei Zhou, Miaomiao Wang 0006, Nicolas Loubet, Andrew Gaul, Yasir Sulehria	Impact of Gate Stack Thermal Budget on NBTI Reliability in Gate-All-Around Nanosheet P-type Devices.	IRPS	2023	DBLP DOI BibTeX RDF
18	Christian Bogner, Christian Schlünder, Michael Waltl, Hans Reisinger, Tibor Grasser	Modeling of NBTI Induced Threshold Voltage Shift Based on Activation Energy Maps Under Consideration of Variability.	IRPS	2023	DBLP DOI BibTeX RDF
18	Wonju Sung, Hyun Seung Kim, Jung Hoon Han, Seguen Park, Jeonghoon Oh, Hyodong Ban, Jooyoung Lee	Investigation on NBTI Control Techniques of HKMG Transistors for Low-power DRAM applications.	IRPS	2023	DBLP DOI BibTeX RDF
18	Daehyun Kwon, Heon Su Jeong, Jaemin Choi, Wijong Kim, Jae Woong Kim, Junsub Yoon, Jungmin Choi, Sanguk Lee, Hyunsub Norbert Rie, Jin-Il Lee, Jongbum Lee, Taeseong Jang, JunHyung Kim, Sanghee Kang, Jung-Bum Shin, Yanggyoon Loh, Chang-Yong Lee, Junmyung Woo, Hye-Seung Yu, Changhyun Bae, Reum Oh, Young-Soo Sohn, Changsik Yoo, Jooyoung Lee	A 1.1V 6.4Gb/s/pin 24-Gb DDR5 SDRAM with a Highly-Accurate Duty Corrector and NBTI-Tolerant DLL.	ISSCC	2023	DBLP DOI BibTeX RDF
18	Yi Jiang, Yanning Chen, Fang Liu, Bo Wu, Yongfeng Deng, Junkang Li, Dawei Gao, Rui Zhang	Systematic Study on Predicting the Lifetime of Si pMOSFETs During NBTI Stress Based on Low-Frequency Noise.	ICICDT	2023	DBLP DOI BibTeX RDF
18	Jani Babu Shaik, Sonal Singhal, Siona Menezes Picardo, Nilesh Goel	Impact of various NBTI distributions on SRAM performance for FinFET technology.	Integr.	2022	DBLP DOI BibTeX RDF
18	Yarong Fu, Wang Wang, Xin Zhong, Manni Li, Zixu Li, Qing Dong, Yu Jiang, Yinyin Lin	Statistical Observations of Three Co-Existing NBTI Behaviors in 28 nm HKMG by On-Chip Monitor With Less Recovery Impact.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
18	Ashish Sharma 0005, Manoj Singh Gaur, Lava Bhargava, Vijay Laxmi, Manoj Gupta	Pre-Silicon NBTI Delay-Aware Modeling of Network-on-Chip Router Microarchitecture.	Microprocess. Microsystems	2022	DBLP DOI BibTeX RDF
18	Abhishek Bhattacharjee, Abhishek Nag, Kaushik Das, Sambhu Nath Pradhan	Design of Power Gated SRAM Cell for Reducing the NBTI Effect and Leakage Power Dissipation During the Hold Operation.	J. Electron. Test.	2022	DBLP DOI BibTeX RDF
18	Nicolás Landeros Muñoz, Alejandro Valero, Ruben Gran Tejero, Davide Zoni	Gated-CNN: Combating NBTI and HCI aging effects in on-chip activation memories of Convolutional Neural Network accelerators.	J. Syst. Archit.	2022	DBLP DOI BibTeX RDF
18	Christian Bogner, Tibor Grasser, Michael Waltl, Hans Reisinger, Christian Schlünder	Efficient Evaluation of the Time-Dependent Threshold Voltage Distribution Due to NBTI Stress Using Transistor Arrays.	IRPS	2022	DBLP DOI BibTeX RDF
18	Yu-Hsing Cheng, Michael Cook 0004, Derryl D. J. Allman	NBTI Characterization with in Situ Poly Heater.	IRPS	2022	DBLP DOI BibTeX RDF
18	Nilotpal Choudhury, Ayush Ranjan, Souvik Mahapatra	Decoupling of NBTI and Pure HCD Contributions in p-GAA SNS FETs Under Mixed VG/VD Stress.	IRPS	2022	DBLP DOI BibTeX RDF
18	S. M. Shakil, Muhammad Sana Ullah	Effects of NBTI On PMOS Device With Technology Scaling.	UEMCON	2022	DBLP DOI BibTeX RDF
18	Yu-Guang Chen, Ing-Chao Lin, Kun-Wei Chiu, Cheng-Hsuan Liu	An efficient NBTI-aware wake-up strategy: Concept, design, and manipulation.	Integr.	2021	DBLP DOI BibTeX RDF
18	Abhishek Bhattacharjee, Sambhu Nath Pradhan	NBTI-Aware Power Gating Design with Dynamically Varying Stress Probability Control on Sleep Transistor.	J. Circuits Syst. Comput.	2021	DBLP DOI BibTeX RDF
18	Kajal, Vijay Kumar Sharma	Design and Simulation for NBTI Aware Logic Gates.	Wirel. Pers. Commun.	2021	DBLP DOI BibTeX RDF
18	Stephan Adolf, Wolfgang Nebel	Abstraction NBTI model.	it Inf. Technol.	2021	DBLP DOI BibTeX RDF
18	Matthew R. Strong, Kushagra Bhatheja, Ruohan Yang, Degang Chen 0001	A Simple Monitor for Tracking NBTI in Integrated Systems.	MWSCAS	2021	DBLP DOI BibTeX RDF
18	Longda Zhou, Zhaohao Zhang, Hong Yang, Zhigang Ji, Qianqian Liu, Qingzhu Zhang, Eddy Simoen, Huaxiang Yin, Jun Luo, Anyan Du, Chao Zhao, Wenwu Wang 0006	A Fast DCIV Technique for Characterizing the Generation and Repassivation of Interface Traps Under DC/ AC NBTI Stress/Recovery Condition in Si p-FinFETs.	IRPS	2021	DBLP DOI BibTeX RDF
18	Gang-Jun Kim, Moonjee Yoon, SungHwan Kim, Myeongkyu Eo, Shinhyung Kim, Taehun You, Namhyun Lee, Kijin Kim, Sangwoo Pae	The Characterization of Degradation on various SiON pMOSFET transistors under AC/DC NBTI stress.	IRPS	2021	DBLP DOI BibTeX RDF
18	Nilotpal Choudhury, Tarun Samadder, Ravi Tiwari, Huimei Zhou, Richard G. Southwick, Miaomiao Wang 0006, Souvik Mahapatra	Analysis of Sheet Dimension (W, L) Dependence of NBTI in GAA-SNS FETs.	IRPS	2021	DBLP DOI BibTeX RDF
18	Hao Chang, Longda Zhou, Hong Yang, Zhigang Ji, Qianqian Liu, Eddy Simoen, Huaxiang Yin, Wenwu Wang 0006	Comparative Study on the Energy Distribution of Defects under HCD and NBTI in Short Channel p-FinFETs.	IRPS	2021	DBLP DOI BibTeX RDF
18	Xiong Li, Huangxia Zhu, Xiaolin Guo, Kejun Mu, Peng Feng, Qi-An Xu, Blacksmith Wu, Kanyu Cao	Impact of Hydrogen Anneal on Peripheral PMOS NBTI and Array Transistor GIDL in DRAM.	ASICON	2021	DBLP DOI BibTeX RDF
18	Yu-Guang Chen, Ing-Chao Lin, Yong-Che Wei	A Novel NBTI-Aware Chip Remaining Lifetime Prediction Framework Using Machine Learning.	ISQED	2021	DBLP DOI BibTeX RDF
18	Takumi Hosaka, Shinichi Nishizawa, Ryo Kishida, Takashi Matsumoto, Kazutoshi Kobayashi	Universal NBTI Compact Model Replicating AC Stress/Recovery from a Single-shot Long-term DC Measurement.	IPSJ Trans. Syst. LSI Des. Methodol.	2020	DBLP DOI BibTeX RDF
18	Shilpa Pendyala, Sheikh Ariful Islam, Srinivas Katkoori	Gate Level NBTI and Leakage Co-Optimization in Combinational Circuits with Input Vector Cycling.	IEEE Trans. Emerg. Top. Comput.	2020	DBLP DOI BibTeX RDF
18	Amel Chenouf, Boualem Djezzar, Hamid Bentarzi, Abdelmadjid Benabdelmoumene	Sizing of the CMOS 6T-SRAM cell for NBTI ageing mitigation.	IET Circuits Devices Syst.	2020	DBLP DOI BibTeX RDF
18	Liting Yu, Jianguo Ren, Xian Lu, Xiaoxiao Wang 0001	NBTI and HCI Aging Prediction and Reliability Screening During Production Test.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2020	DBLP DOI BibTeX RDF