Search results for "networks-on-chips"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
44	Srinivasan Murali, Martijn Coenen, Andrei Radulescu, Kees Goossens, Giovanni De Micheli	A methodology for mapping multiple use-cases onto networks on chips.	DATE	2006	DBLP DOI BibTeX RDF	dynamic re-configuration, systems on chips, networks on chips, use-cases, modes
44	Srinivasan Murali, Martijn Coenen, Andrei Radulescu, Kees Goossens, Giovanni De Micheli	Mapping and configuration methods for multi-use-case networks on chips.	ASP-DAC	2006	DBLP DOI BibTeX RDF	guaranteed throughput, multiple application platforms, systems on chips, networks on chips, reconfiguration, dynamic, use-cases, voltage scaling, frequency scaling, best effort
44	Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo	Designing application-specific networks on chips with floorplan information.	ICCAD	2006	DBLP DOI BibTeX RDF	networks on chips, topology, floorplan, deadlock-free routing
40	Srinivasan Murali, Ciprian Seiculescu, Luca Benini, Giovanni De Micheli	Synthesis of networks on chips for 3D systems on chips.	ASP-DAC	2009	DBLP DOI BibTeX RDF	topology synthesis, networks on chip, 3D, application-specific
38	Michihiro Koibuchi, Kenichiro Anjo, Yutaka Yamada, Akiya Jouraku, Hideharu Amano	A Simple Data Transfer Technique Using Local Address for Networks-on-Chips.	IEEE Trans. Parallel Distributed Syst.	2006	DBLP DOI BibTeX RDF	table-lookup routing, interconnection networks, Networks-on-chips, streaming processing, reconfigurable systems, on-chip interconnects
36	Giovanni De Micheli	Design Technologies for Networks on Chips.	NOCS	2007	DBLP DOI BibTeX RDF
34	Frits Steenhof, Harry Duque, Björn Nilsson, Kees Goossens, Rafael Peset Llopis	Networks on chips for high-end consumer-electronics TV system architectures.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
31	Rutuparna Tamhankar, Srinivasan Murali, Giovanni De Micheli	Performance driven reliable link design for networks on chips.	ASP-DAC	2005	DBLP DOI BibTeX RDF	aggressive design, performance, reliability, networks on chips, link
30	Resve A. Saleh	An approach that will NoC your SoCs off!	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	networks on chips, SoC design, Moore's law, interconnect delay, IP blocks
30	Srinivasan Murali, Luca Benini, Giovanni De Micheli	Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees.	ASP-DAC	2005	DBLP DOI BibTeX RDF	physical planning, QoS, optimization, systems on chips, mapping, networks on chips
28	Jiang Xu 0001, Wayne H. Wolf	Wave pipelining for application-specific networks-on-chips.	CASES	2002	DBLP DOI BibTeX RDF	system-on-chip (SoC), interconnection, networks-on-chip (NoC), wave pipelining, coupling capacitance
27	Giovanni De Micheli, Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Federico Angiolini, Antonio Pullini	Networks on Chips: from research to products.	DAC	2010	DBLP DOI BibTeX RDF	SoC, system on chip, network on chip, NoC
27	Stergios Stergiou, Federico Angiolini, Salvatore Carta, Luigi Raffo, Davide Bertozzi, Giovanni De Micheli	xpipes Lite: A Synthesis Oriented Design Library For Networks on Chips.	DATE	2005	DBLP DOI BibTeX RDF
27	Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo	Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
24	Rajesh K. Gupta 0001	On-chip networks.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	integration, SoCs, networks on chips, on-chip interconnects
22	Arnab Banerjee, Robert D. Mullins, Simon W. Moore	A Power and Energy Exploration of Network-on-Chip Architectures.	NOCS	2007	DBLP DOI BibTeX RDF
21	Mingsong Lv, Ying Guo, Nan Guan, Qingxu Deng	RTNoC: A Simulation Tool for Real-Time Communication Scheduling on Networks-on-Chips.	CSSE (4)	2008	DBLP DOI BibTeX RDF
21	Leandro Fiorin, Cristina Silvano, Mariagiovanna Sami	Security Aspects in Networks-on-Chips: Overview and Proposals for Secure Implementations.	DSD	2007	DBLP DOI BibTeX RDF
21	Avinoam Kolodny	Networks on chips: keeping up with Rent's rule and Moore's law.	SLIP	2007	DBLP DOI BibTeX RDF	routing, timing, interconnect, power, on-chip network, wires
21	Partha Pratim Pande, Cristian Grecu, André Ivanov, Resve A. Saleh, Giovanni De Micheli	Design, Synthesis, and Test of Networks on Chips.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	Reliability, VLSI, Automatic synthesis, VLSI Systems, Testing and Fault-Tolerance
21	Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, Akiya Jouraku, Hideharu Amano	Non-Minimal Routing Strategy for Application-Specific Networks-on-Chips.	ICPP Workshops	2005	DBLP DOI BibTeX RDF
19	Tomas Henriksson, Pieter van der Wolf	TTL Hardware Interface: A High-Level Interface for Streaming Multiprocessor Architectures.	ESTIMedia	2006	DBLP DOI BibTeX RDF
17	Mohammad Abdullah Al Faruque, Jörg Henkel	QoS-supported On-chip Communication for Multi-processors.	Int. J. Parallel Program.	2008	DBLP DOI BibTeX RDF	quality of services, Networks on chips, arbitration, multi-processor, service class
17	Mohammad Abdullah Al Faruque, Gereon Weiss, Jörg Henkel	Bounded arbitration algorithm for QoS-supported on-chip communication.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	bounded arbitration algorithm, quality of services, networks-on-chips
17	André Ivanov, Giovanni De Micheli	Guest Editors' Introduction: The Network-on-Chip Paradigm in Practice and Research.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	micronetworks, networks on chips, multiprocessor SoCs, on-chip interconnection network, on-chip communication, infrastructure IP
17	Srinivasan Murali, Giovanni De Micheli	Bandwidth-Constrained Mapping of Cores onto NoC Architectures.	DATE	2004	DBLP DOI BibTeX RDF	routing, Systems on Chips, mapping, Networks on Chips, bandwidth, cores
17	Antoine Jalabert, Srinivasan Murali, Luca Benini, Giovanni De Micheli	×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip.	DATE	2004	DBLP DOI BibTeX RDF	Systems on Chips, Networks on Chips, SystemC, application-specific, latency-insensitive design
16	Onur Derin, Erkan Diken, Leandro Fiorin	A Middleware Approach to Achieving Fault Tolerance of Kahn Process Networks on Networks on Chips.	Int. J. Reconfigurable Comput.	2011	DBLP DOI BibTeX RDF
15	Elisabeth Pelz, Dietmar Tutsch	Formal Models for Multicast Traffic in Network on Chip Architectures with Compositional High-Level Petri Nets.	ICATPN	2007	DBLP DOI BibTeX RDF
15	Grant Martin	Book Reviews: NoC, NoC ... Who's there?	IEEE Des. Test Comput.	2006	DBLP DOI BibTeX RDF	technology and tools, networks, NoC
14	Nassima Kadri, Azzeddine Chenine, Zakaria Laib, Mouloud Koudil	Reliability-aware intelligent mapping based on reinforcement learning for networks-on-chips.	J. Supercomput.	2022	DBLP DOI BibTeX RDF
14	Junwei Zhang, Thomas G. Robertazzi	Analyzing Data Intensive Networks on Chips.	UCC	2022	DBLP DOI BibTeX RDF
14	Junwei Zhang, Li Shi, Yang Liu 0177, Thomas G. Robertazzi	Optimizing Data Intensive Flows for Networks on Chips.	Parallel Process. Lett.	2021	DBLP DOI BibTeX RDF
14	Pablo A. Ferreyra, Rubén Danilo Capkob, Alberto Fabián Gómez, Juan Andres Fraire, Carlos José Barrientos	Embedded wireless delay tolerant networks on chips for segmented architectures.	Int. J. Embed. Syst.	2021	DBLP DOI BibTeX RDF
14	Jie Hou	Performability analysis of Networks-on-Chips		2021	DOI RDF
14	Amir Charif, Alexandre Coelho, Nacer-Eddine Zergainoh, Michael Nicolaidis	A Dynamic Sufficient Condition of Deadlock-Freedom for High-Performance Fault-Tolerant Routing in Networks-on-Chips.	IEEE Trans. Emerg. Top. Comput.	2020	DBLP DOI BibTeX RDF
14	Mengchu Li, Tsun-Ming Tseng, Mahdi Tala, Ulf Schlichtmann	Maximizing the Communication Parallelism for Wavelength-Routed Optical Networks-On-Chips.	ASP-DAC	2020	DBLP DOI BibTeX RDF
14	Nidhi Anantharajaiah, Fabian Kempf, Leonard Masing, Fabian Marc Lesniak, Jürgen Becker 0001	Dynamic and scalable runtime block-based multicast routing for networks on chips.	NoCArc@MICRO	2019	DBLP DOI BibTeX RDF
14	Junwei Zhang, Yang Liu 0177, Shi Li, Thomas G. Robertazzi	Optimizing Data Intensive Flows for Networks on Chips.	CoRR	2018	DBLP BibTeX RDF
14	Alexandre Coelho, Amir Charif, Nacer-Eddine Zergainoh, Juan A. Fraire, Raoul Velazco	A soft-error resilient route computation unit for 3D Networks-on-Chips.	DATE	2018	DBLP DOI BibTeX RDF
14	Adele Maleki, Hamidreza Ahmadian, Roman Obermaisser	Fault-Tolerant and Energy-Efficient Communication in Mixed-Criticality Networks-on-Chips.	NORCAS	2018	DBLP DOI BibTeX RDF
14	Fengxian Jiao, Sheqin Dong, Bei Yu 0001, Bing Li 0005, Ulf Schlichtmann	Thermal-Aware Placement and Routing for 3D Optical Networks-on-Chips.	ISCAS	2018	DBLP DOI BibTeX RDF
14	Amir Charif, Alexandre Coelho, Nacer-Eddine Zergainoh, Michael Nicolaidis	A Framework for Scalable TSV Assignment and Selection in Three-Dimensional Networks-on-Chips.	VLSI Design	2017	DBLP DOI BibTeX RDF
14	Giovanni De Micheli, Luca Benini	Networks on Chips: 15 Years Later.	Computer	2017	DBLP DOI BibTeX RDF
14	William Rayess, David W. Matolak, Savas Kaya, Avinash Karanth Kodi	Antennas and Channel Characteristics for Wireless Networks on Chips.	Wirel. Pers. Commun.	2017	DBLP DOI BibTeX RDF
14	Hamidreza Ahmadian, Farzad Nekouei, Roman Obermaisser	Fault recovery and adaptation in time-triggered Networks-on-Chips for mixed-criticality systems.	ReCoSoC	2017	DBLP DOI BibTeX RDF
14	Ashur Rafiev, Fei Xia, Alexei Iliasov, Alexander B. Romanovsky, Alexandre Yakovlev	Selective Abstraction for Estimating Extra-Functional Properties in Networks-on-Chips Using ArchOn Framework.	ACSD	2017	DBLP DOI BibTeX RDF
14	Amir Charif, Alexandre Coelho, Nacer-Eddine Zergainoh, Michael Nicolaidis	MINI-ESPADA: A low-cost fully adaptive routing mechanism for Networks-on-Chips.	LATS	2017	DBLP DOI BibTeX RDF
14	Wei Tan, Huaxi Gu, Yintang Yang, Meaad Fadhel, Bowen Zhang 0004	Network Condition-Aware Communication Mechanism for Circuit-Switched Optical Networks-on-Chips.	JOCN	2016	DBLP DOI BibTeX RDF
14	Adam Kostrzewa, Sebastian Tobuschat, Rolf Ernst, Selma Saidi	Safe and dynamic traffic rate control for networks-on-chips.	NOCS	2016	DBLP DOI BibTeX RDF
14	Amir Charif, Nacer-Eddine Zergainoh, Michael Nicolaidis	Addressing transient routing errors in fault-tolerant Networks-on-Chips.	ETS	2016	DBLP DOI BibTeX RDF
14	Adam Kostrzewa, Selma Saidi, Leonardo Ecco, Rolf Ernst	Dynamic admission control for real-time networks-on-chips.	ASP-DAC	2016	DBLP DOI BibTeX RDF
14	Kai Lampka, Adam Lackorzynski	Resolving Contention for Networks-on-Chips: Combining Time-Triggered Application Scheduling with Dynamic Budgeting of Memory Bus Use.	MMB/DFT	2016	DBLP DOI BibTeX RDF
14	Arseni Vitkovski, Vassos Soteriou, Paul V. Gratz	Wear-Aware Adaptive Routing for Networks-on-Chips.	NOCS	2015	DBLP DOI BibTeX RDF
14	Hela Ben Salah, Adel Benzina, Mohamed Khalgui	Petri Nets-based design of real-time reconfigurable networks on chips.	ICIS	2015	DBLP DOI BibTeX RDF
14	Qianqi Le, Guowu Yang, William N. N. Hung, Xiaoyu Song, Fuyou Fan	Performance-driven assignment and mapping for reliable networks-on-chips.	J. Zhejiang Univ. Sci. C	2014	DBLP DOI BibTeX RDF
14	Costas Iordanou, Vassos Soteriou, Konstantinos Aisopos, Elena Kakoulli	Hermes: Architecting a top-performing fault-tolerant routing algorithm for Networks-on-Chips.	NOCS	2014	DBLP DOI BibTeX RDF
14	Mohamed Sallam, M. Watheq El-Kharashi, Mohamed Dessouky	The Connection-Then-Credit Flow Control Protocol for Networks-On-Chips: Implementation Trade-offs.	NoCArc@MICRO	2014	DBLP DOI BibTeX RDF
14	Costas Iordanou, Vassos Soteriou, Konstantinos Aisopos	Hermes: Architecting a top-performing fault-tolerant routing algorithm for Networks-on-Chips.	ICCD	2014	DBLP DOI BibTeX RDF
14	David W. Matolak, Savas Kaya, Avinash Karanth Kodi	Channel modeling for wireless networks-on-chips.	IEEE Commun. Mag.	2013	DBLP DOI BibTeX RDF
14	Haytham Elmiligi, M. Watheq El-Kharashi, Fayez Gebali	Power consumption of 3D networks-on-chips: Modeling and optimization.	Microprocess. Microsystems	2013	DBLP DOI BibTeX RDF
14	Xiaohang Wang 0001, Peng Liu 0016, Mei Yang, Yingtao Jiang	Avoiding request-request type message-dependent deadlocks in networks-on-chips.	Parallel Comput.	2013	DBLP DOI BibTeX RDF
14	Yancang Chen, Zhonghai Lu, Lunguo Xie, Jinwen Li, Minxuan Zhang	A single-cycle output buffered router with layered switching for Networks-on-Chips.	Comput. Electr. Eng.	2012	DBLP DOI BibTeX RDF
14	David W. Matolak, Avinash Karanth Kodi, Savas Kaya, Dominic DiTomaso, Soumyasanta Laha, William Rayess	Wireless networks-on-chips: architecture, wireless channel, and devices.	IEEE Wirel. Commun.	2012	DBLP DOI BibTeX RDF
14	Freek Verbeek, Julien Schmaltz	Easy Formal Specification and Validation of Unbounded Networks-on-Chips Architectures.	ACM Trans. Design Autom. Electr. Syst.	2012	DBLP DOI BibTeX RDF
14	Wen-Chung Tsai, Ying-Cherng Lan, Yu Hen Hu, Sao-Jie Chen	Networks on Chips: Structure and Design Methodologies.	J. Electr. Comput. Eng.	2012	DBLP DOI BibTeX RDF
14	Elena Kakoulli, Vassos Soteriou, Theocharis Theocharides	HPRA: A pro-active Hotspot-Preventive high-performance routing algorithm for Networks-on-Chips.	ICCD	2012	DBLP DOI BibTeX RDF
14	Kees Goossens, Radu Marculescu	Special Issue on Networks-on-Chips: Design Flows and Case Studies.	Des. Autom. Embed. Syst.	2011	DBLP DOI BibTeX RDF
14	Zhonghai Lu	Cross clock-domain TDM virtual circuits for networks on chips.	NOCS	2011	DBLP DOI BibTeX RDF
14	Freek Verbeek, Julien Schmaltz	Automatic verification for deadlock in networks-on-chips with adaptive routing and wormhole switching.	NOCS	2011	DBLP DOI BibTeX RDF
14	Daniel Vergeylen, Angelo Kuti Lusala, Jean-Didier Legat	A new mechanism to reduce congestion on TDM networks-on-chips.	ReCoSoC	2011	DBLP DOI BibTeX RDF
14	Konstantinos Aisopos, Chia-Hsin Owen Chen, Li-Shiuan Peh	Enabling system-level modeling of variation-induced faults in networks-on-chips.	DAC	2011	DBLP DOI BibTeX RDF
14	Freek Verbeek, Julien Schmaltz	Formal specification of networks-on-chips: deadlock and evacuation.	DATE	2010	DBLP DOI BibTeX RDF
14	Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli	A method to remove deadlocks in Networks-on-Chips with Wormhole flow control.	DATE	2010	DBLP DOI BibTeX RDF
14	Srinivasan Murali, Luca Benini, Giovanni De Micheli	Design of networks on chips for 3D ICs.	ASP-DAC	2010	DBLP DOI BibTeX RDF
14	Davide Bertozzi, Kees Goossens	Networks on chips [editorial].	IET Comput. Digit. Tech.	2009	DBLP DOI BibTeX RDF
14	Haytham Elmiligi, Ahmed A. Morgan, M. Watheq El-Kharashi, Fayez Gebali	Power optimization for application-specific networks-on-chips: A topology-based approach.	Microprocess. Microsystems	2009	DBLP DOI BibTeX RDF
14	Srinivasan Murali	Designing Reliable and Efficient Networks on Chips		2009	DBLP DOI BibTeX RDF
14		Third International Symposium on Networks-on-Chips, NOCS 2009, May 10-13 2009, La Jolla, CA, USA. Proceedings	NOCS	2009	DBLP BibTeX RDF
14	Robin Emery, Alexandre Yakovlev, E. Graeme Chester	Connection-centric network for spiking neural networks.	NOCS	2009	DBLP DOI BibTeX RDF
14	Bo Fu, David Wolpert 0001, Paul Ampadu	Lookahead-based adaptive voltage scheme for energy-efficient on-chip interconnect links.	NOCS	2009	DBLP DOI BibTeX RDF
14	Nicola Concer, Luciano Bononi, Michael Soulie, Riccardo Locatelli, Luca P. Carloni	CTC: An end-to-end flow control protocol for multi-core systems-on-chip.	NOCS	2009	DBLP DOI BibTeX RDF
14	Somayyeh Koohi, Shaahin Hessabi	Contention-free on-chip routing of optical packets.	NOCS	2009	DBLP DOI BibTeX RDF
14	Ajay Joshi, Christopher Batten, Yong-Jin Kwon, Scott Beamer, Imran Shamim, Krste Asanovic, Vladimir Stojanovic	Silicon-photonic clos networks for global on-chip communication.	NOCS	2009	DBLP DOI BibTeX RDF
14	Ivo Bolsens	NoCs: It is about the memory and the programming model.	NOCS	2009	DBLP DOI BibTeX RDF
14	Henrique C. Freitas, Marco A. Z. Alves, Lucas Mello Schnorr, Philippe Olivier Alexandre Navaux	Performance Evaluation of NoC Architectures for Parallel Workloads.	NOCS	2009	DBLP DOI BibTeX RDF
14	Andrew A. Chien	NoC's at the center of chip architecture: Urgent needs (today) and what they must become (future).	NOCS	2009	DBLP DOI BibTeX RDF
14	Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet	Estimating reliability and throughput of source-synchronous wave-pipelined interconnect.	NOCS	2009	DBLP DOI BibTeX RDF
14	Marcos Hervé, Érika F. Cota, Fernanda Lima Kastensmidt, Marcelo Lubaszewski	Diagnosis of interconnect shorts in mesh NoCs.	NOCS	2009	DBLP DOI BibTeX RDF
14	Lei Wang 0041, Yuho Jin, Hyungjun Kim, Eun Jung Kim 0001	Recursive partitioning multicast: A bandwidth-efficient routing for Networks-on-Chip.	NOCS	2009	DBLP DOI BibTeX RDF
14	Yue Qian, Zhonghai Lu, Wenhua Dou	Analysis of worst-case delay bounds for best-effort communication in wormhole networks on chip.	NOCS	2009	DBLP DOI BibTeX RDF
14	Anh Thien Tran, Dean Truong, Bevan M. Baas	A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network.	NOCS	2009	DBLP DOI BibTeX RDF
14	Ran Manevich, Isask'har Walter, Israel Cidon, Avinoam Kolodny	Best of both worlds: A bus enhanced NoC (BENoC).	NOCS	2009	DBLP DOI BibTeX RDF
14	Gilbert Hendry, Shoaib Kamil 0001, Aleksandr Biberman, Johnnie Chan, Benjamin G. Lee, Marghoob Mohiyuddin, Ankit Jain, Keren Bergman, Luca P. Carloni, John Kubiatowicz, Leonid Oliker, John Shalf	Analysis of photonic networks for a chip multiprocessor using scientific applications.	NOCS	2009	DBLP DOI BibTeX RDF
14	Rudy Beraha, Isask'har Walter, Israel Cidon, Avinoam Kolodny	The design of a latency constrained, power optimized NoC for a 4G SoC.	NOCS	2009	DBLP DOI BibTeX RDF
14	Ying-Cherng Lan, Shih-Hsin Lo, Yueh-Chi Lin, Yu Hen Hu, Sao-Jie Chen	BiNoC: A bidirectional NoC architecture with dynamic self-reconfigurable channel.	NOCS	2009	DBLP DOI BibTeX RDF
14	Prabhat Kumar 0002, Yan Pan, John Kim, Gokhan Memik, Alok N. Choudhary	Exploring concentration and channel slicing in on-chip network router.	NOCS	2009	DBLP DOI BibTeX RDF
14	Luca P. Carloni, Partha Pande 0001, Yuan Xie 0001	Networks-on-chip in emerging interconnect paradigms: Advantages and challenges.	NOCS	2009	DBLP DOI BibTeX RDF
14	Daniel Gebhardt, Kenneth S. Stevens	Power reduction through physical placement of asynchronous routers.	NOCS	2009	DBLP DOI BibTeX RDF
14	Evgeni Krimer, Mattan Erez, Isaac Keslassy, Avinoam Kolodny, Isask'har Walter	Packet-level static timing analysis for NoCs.	NOCS	2009	DBLP DOI BibTeX RDF