Search results for "numa"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
191	Babak Falsafi, David A. Wood 0001	Reactive NUMA: A Design for Unifying S-COMA and CC-NUMA.	ISCA	1997	DBLP DOI BibTeX RDF
145	Zheng Zhang 0001, Josep Torrellas	Reducing Remote Conflict Misses: NUMA with Remote Cache versus COMA.	HPCA	1997	DBLP DOI BibTeX RDF	remote conflict miss, NUMA with Remote Cache, shared-memory multiprocessor, cache coherent, COMA
132	Takeshi Ogasawara	NUMA-aware memory manager with dominant-thread-based copying GC.	OOPSLA	2009	DBLP DOI BibTeX RDF	java, cc-NUMA
128	Markus Nordén, Sverker Holmgren, Michael Thuné	OpenMP versus MPI for PDE Solvers Based on Regular Sparse Numerical Operators.	International Conference on Computational Science (3)	2002	DBLP DOI BibTeX RDF	UMA, Euler, Optimization, MPI, OpenMP, PDE, NUMA, Stencil
126	Soo-Cheol Oh, Sang-Hwa Chung, Hankook Jang	Design and Implementation of CC-NUMA Card II for SCI-Based PC Clustering.	CLUSTER	2002	DBLP DOI BibTeX RDF
108	Kai Lu, Ruibo Wang, Xicheng Lu	Brief announcement: NUMA-aware transactional memory.	PODC	2010	DBLP DOI BibTeX RDF	transactional memory, numa
108	Zheng Zhang 0001, Marcelo H. Cintra, Josep Torrellas	Excel-NUMA: Toward Programmability, Simplicity, and High Performance.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	NUMA organizations, performance evaluation, caches, Shared-memory multiprocessors, cache-coherence protocols
98	An-Chow Lai, Babak Falsafi	Optimizing Traffic in DSM Clusters: Fine-Grain Memory Caching versus Page Migration/Replication.	Theory Comput. Syst.	2002	DBLP DOI BibTeX RDF
98	An-Chow Lai, Babak Falsafi	Comparing the effectiveness of fine-grain memory caching against page migration/replication in reducing traffic in DSM clusters.	SPAA	2000	DBLP DOI BibTeX RDF
96	Xiaodong Zhang 0001, Xiaohan Qin	Performance Prediction and Evaluation of Parallel Processing on a NUMA Multiprocessor.	IEEE Trans. Software Eng.	1991	DBLP DOI BibTeX RDF	nonuniform memory access, parallel processing performance, BBN GP1000, NUMA shared-memory multiprocessor, scheduling, performance evaluation, parallel processing, programming environment, multiprocessing systems, analytical models, interprocessor communication, process scheduling, network contention, process synchronization, memory contention, optimal strategies, remote memory access
80	Sang-Hwa Chung, Soo-Cheol Oh	An SCI-Based PC Cluster Utilizing Coherent Network Cache.	Clust. Comput.	2003	DBLP DOI BibTeX RDF	network cache, cluster system, CC-NUMA, SCI
77	Jie Tao 0001, Martin Schulz 0001, Wolfgang Karl	SIMT/OMP: A Toolset to Study and Exploit Memory Locality of OpenMP Applications on NUMA Architectures.	WOMPAT	2004	DBLP DOI BibTeX RDF
71	Xiaodong Zhang 0001, Yong Yan 0003	Comparative Modeling and Evaluation of CC-NUMA and COMA on Hierarchical Ring Architectures.	IEEE Trans. Parallel Distributed Syst.	1995	DBLP DOI BibTeX RDF	performance modeling and measurements, the KSR1, shared-memory, Cache coherence, CC-NUMA, COMA, slotted rings
67	Henk L. Muller, Paul W. A. Stallard, David H. D. Warren	The Role of Associative Memory in Virtual Shared Memory Architectures: A Price-Performance Comparison.	PDP	1996	DBLP DOI BibTeX RDF	virtual shared memory architectures, price-performance, set associative memory, large coherent cache, performance evaluation, benchmarks, parallel machines, memory hierarchy, shared memory systems, costing, cost, associative memory, memory architecture, content-addressable storage, application specific, virtual storage, CC-NUMA, COMA, miss ratios
66	Hubert Garavel, César Viho, Massimo Zendri	System design of a CC-NUMA multiprocessor architecture using formal specification, model-checking, co-simulation, and test generation.	Int. J. Softw. Tools Technol. Transf.	2001	DBLP DOI BibTeX RDF	Verification, Formal specification, Testing, Formal methods, Validation, Code generation, Computer architecture, Test generation, Rapid prototyping, Process algebra, Conformance testing, Cache coherency, System level design, Co-design, lotos, Hardware design, Co-simulation, numa, cc-numa
66	Richard P. LaRowe Jr., Carla Schlatter Ellis, Mark A. Holliday	Evaluation of NUMA Memory Management Through Modeling and Measurements.	IEEE Trans. Parallel Distributed Syst.	1992	DBLP DOI BibTeX RDF	NUMA memory management, nonuniform memory access time, shared-memoryarchitectures, experimental DUnX operating system kernel, BBNGP1000, highly parameterized dynamic page placement policy, memorysystem performance, local/remote NUMA architecture, approximate mean-value analysistechniques, model predictions, dynamic multiple-copy pageplacement, replication/coherency fault errors, remotely referenced, parallel programs, parallel programming, analytic model, shared memory systems, storage management, storage allocation, experimental data
65	Nathan Robertson, Alistair P. Rendell	OpenMP and NUMA Architectures I: Investigating Memory Placement on the SCI Origin 3000.	International Conference on Computational Science	2003	DBLP DOI BibTeX RDF
65	Joo Beom Yun, Seong Tae Jhang, Chu Shik Jhon, Cheol Won Lee	Analysis of System Performance by Changing the Ring Architecture on the Dual Ring CC-NUMA System.	ICPADS	2002	DBLP DOI BibTeX RDF
65	Ravi R. Iyer 0001, Laxmi N. Bhuyan	Design and Evaluation of a Switch Cache Architecture for CC-NUMA Multiprocessors.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	scalable interconnects, shared memory multiprocessors, wormhole routing, execution-driven simulation, Crossbar switches, cache architectures
65	Richard P. LaRowe Jr., Carla Schlatter Ellis, Laurence S. Kaplan	The Robustness of NUMA Memory Management.	SOSP	1991	DBLP DOI BibTeX RDF
59	Kenneth M. Wilson, Bob B. Aglietti	Dynamic page placement to improve locality in CC-NUMA multiprocessors for TPC-C.	SC	2001	DBLP DOI BibTeX RDF	TPC-C, dynamic page placement, multiprocessor, replication, migration, CC-NUMA
59	Takahiro Koita, Tetsuro Katayama, Keizo Saisho, Akira Fukuda	Memory Conscious Scheduling for Cluster-based NUMA Multiprocessors.	J. Supercomput.	2000	DBLP DOI BibTeX RDF	dynamic space-sharing, page placement, cluster-based NUMA multiprocessors, multiprogrammed environments, processor scheduling
59	Tarek S. Abdelrahman, Thomas N. Wong	Compiler Support for Array Distribution on NUMA Shared Memory Multiprocessors.	J. Supercomput.	1998	DBLP DOI BibTeX RDF	locality management, NUMA multi-processors, parallelizing compilers, data distribution, cache management
59	Edward D. Moreno, Sergio Takeo Kofuji	Efficiency of remote access caches in future SMP-based CC-NUMA multiprocessors: initial results.	ISPAN	1997	DBLP DOI BibTeX RDF	shared remote access cache, future SMP based CC-NUMA multiprocessors, symmetric multiprocessor nodes, future architectures, realistic hardware parameters, state of the art systems components, SPLASH-2 benchmark suite, performance application, baseline architecture, approach-1, slow network, approach-2, fast network, 32-processor system, four-processor SMP nodes, two-processor SMP nodes, multiprocessing systems, execution time, cost effectiveness
55	François Broquedis, François Diakhaté, Samuel Thibault, Olivier Aumage, Raymond Namyst, Pierre-André Wacrenier	Scheduling Dynamic OpenMP Applications over Multicore Architectures.	IWOMP	2008	DBLP DOI BibTeX RDF	Hierarchical Thread Scheduling, Multi-Core, OpenMP, SMP, NUMA, Bubbles, Nested Parallelism
55	Mônica Corrêa, Avelino Francisco Zorzo, Roque Scheer	Operating system multilevel load balancing.	SAC	2006	DBLP DOI BibTeX RDF	NUMA computers, performance, scalability, load balancing, linux, Linux
53	Hung-Chang Hsiao, Chung-Ta King	The Thread-Based Protocol Engines for CC-NUMA Multiprocessors.	ICPP	2000	DBLP DOI BibTeX RDF
53	Ravi R. Iyer 0001, Laxmi N. Bhuyan	Switch Cache: A Framework for Improving the Remote Memory Access Latency of CC-NUMA Multiprocessors.	HPCA	1999	DBLP DOI BibTeX RDF
53	John Chapin, Stephen Alan Herrod, Mendel Rosenblum, Anoop Gupta	Memory System Performance of UNIX on CC-NUMA Multiprocessors.	SIGMETRICS	1995	DBLP DOI BibTeX RDF
53	Roger L. Adema, Carla Schlatter Ellis	Memory allocation constructs to complement NUMA memory management.	SPDP	1991	DBLP DOI BibTeX RDF
53	Xiaodong Zhang 0001, P. Srinivasan	Distributed task processing performance on a NUMA shared memory multiprocessor.	SPDP	1990	DBLP DOI BibTeX RDF
49	Abdul Haseeb Malik, Andy J. Wellings, Yang Chang	A locality model for the real-time specification for Java.	JTRES	2010	DBLP DOI BibTeX RDF
49	Tong Li 0003, Dan P. Baumberger, David A. Koufaty, Scott Hahn	Efficient operating system scheduling for performance-asymmetric multi-core architectures.	SC	2007	DBLP DOI BibTeX RDF
49	Lei Chai, Albert Hartono, Dhabaleswar K. Panda 0001	Designing High Performance and Scalable MPI Intra-node Communication Support for Clusters.	CLUSTER	2006	DBLP DOI BibTeX RDF
49	Erik Hagersten, Michael Koster	WildFire: A Scalable Path for SMPs.	HPCA	1999	DBLP DOI BibTeX RDF
47	François Broquedis, Nathalie Furmento, Brice Goglin, Raymond Namyst, Pierre-André Wacrenier	Dynamic Task and Data Placement over NUMA Architectures: An OpenMP Runtime Perspective.	IWOMP	2009	DBLP DOI BibTeX RDF	Hierarchical Thread Scheduling, Memory, Multi-Core, OpenMP, NUMA
47	Roberto Gomperts, Michael J. Frisch, Jean-Pierre Panziera	Scalability of Gaussian 03 on SGI Altix: The Importance of Data Locality on CC-NUMA Architecture.	IWOMP	2009	DBLP DOI BibTeX RDF	Gaussian 03, SGI Altix, OpenMP, memory latency, CC-NUMA
47	Manuel E. Acacio, José González 0002, José M. García 0001, José Duato	A Two-Level Directory Architecture for Highly Scalable cc-NUMA Multiprocessors.	IEEE Trans. Parallel Distributed Syst.	2005	DBLP DOI BibTeX RDF	directory memory overhead, two-level directory architecture, compressed sharing codes, unnecessary coherence messages, cc-NUMA multiprocessor, Scalability
47	Henrik Löf, Sverker Holmgren	affinity-on-next-touch: increasing the performance of an industrial PDE solver on a cc-NUMA system.	ICS	2005	DBLP DOI BibTeX RDF	TLB shoot-down, computational electro-magnetics, large pages, OpenMP, sparse matrices, conjugate gradients, cc-NUMA, page migration
47	Laxmi N. Bhuyan, Hu-Jun Wang	Switch MSHR: A Technique to Reduce Remote Read Memory Access Time in CC-NUMA Multiprocessors.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	CC-NUMA multiprocessor, memory latency problem, miss status holding register, interconnection network, execution-driven simulation
47	Dannie Durand, Thierry Montaut, Lionel Kervella, William Jalby	Impact of Memory Contention on Dynamic Scheduling on NUMA Multiprocessors.	IEEE Trans. Parallel Distributed Syst.	1996	DBLP DOI BibTeX RDF	NUMA multiprocessors, load balancing, Dynamic scheduling, memory performance, self-scheduling
47	Guan-Joe Lai, Cheng Chen	A new scheduling strategy for NUMA multiprocessor systems.	ICPADS	1996	DBLP DOI BibTeX RDF	non-uniform memory access, Longest Extended Critical Path First, multiprocessor systems, shared-memory multiprocessor, shared memory systems, processor scheduling, NUMA, scheduling strategies
41	Qiong Li, Zhengbin Pang, Yufeng Guo, Enqiang Zhou, Xuejun Yang	A GPDMA-based Distributed Shared I/O Solution for CC-NUMA System.	ICYCS	2008	DBLP DOI BibTeX RDF
41	Zhou Yingchao, Meng Dan, Ma Jie	Dual-layered file cache on cc-NUMA system.	IPDPS	2006	DBLP DOI BibTeX RDF
41	Mustafa M. Tikir, Jeffrey K. Hollingsworth	NUMA-Aware Java Heaps for Server Applications.	IPDPS	2005	DBLP DOI BibTeX RDF
41	Valentin Puente, José A. Gregorio, Ramón Beivide, Cruz Izu	On the Design of a High-Performance Adaptive Router for CC-NUMA Multiprocessors.	IEEE Trans. Parallel Distributed Syst.	2003	DBLP DOI BibTeX RDF	hardware router design, Interconnection networks, shared memory multiprocessors, adaptive routing
41	Manuel E. Acacio, José González 0002, José M. García 0001, José Duato	The Use of Prediction for Accelerating Upgrade Misses in cc-NUMA Multiprocessors.	IEEE PACT	2002	DBLP DOI BibTeX RDF
41	Manuel E. Acacio, José González 0002, José M. García 0001, José Duato	Owner prediction for accelerating cache-to-cache transfer misses in a cc-NUMA architecture.	SC	2002	DBLP DOI BibTeX RDF
41	Martin Schmollinger, Michael Kaufmann 0001	kappa NUMA: A Model for Clusters of SMP-Machines.	PPAM	2001	DBLP DOI BibTeX RDF
41	Barbara M. Chapman, Amit Patil, Achal Prabhakar	Performance Oriented Programming for NUMA Architectures.	WOMPAT	2001	DBLP DOI BibTeX RDF	ccNUMA Architectures, OpenMP, data distribution, data locality, restructuring, parallel programming models, Software Distributed Shared Memory, shared memory parallelism
41	Laxmi N. Bhuyan, Ravi R. Iyer 0001, Hu-Jun Wang, Akhilesh Kumar	Impact of CC-NUMA Memory Management Policies on the Application Performance of Multistage Switching Networks.	IEEE Trans. Parallel Distributed Syst.	2000	DBLP DOI BibTeX RDF	Memory management, shared-memory multiprocessor, wormhole routing, scientific applications, execution-driven simulation, switch design
41	Wijnand Derks, Sietse Dijkstra, H. D. Enting, Willem Jonker, Jeroen Wijnands	Experimenting NUMA for Scalable CDR Processing.	DEXA	2000	DBLP DOI BibTeX RDF
41	Tom Lovett, Russell M. Clapp	STiNG: A CC-NUMA Computer System for the Commercial Marketplace.	ISCA	1996	DBLP DOI BibTeX RDF
41	Ben Verghese, Scott Devine, Anoop Gupta, Mendel Rosenblum	Operating System Support for Improving Data Locality on CC-NUMA Compute Servers.	ASPLOS	1996	DBLP DOI BibTeX RDF
41	Richard P. LaRowe Jr., Mark A. Holliday, Carla Schlatter Ellis	An Analysis of Dynamic Page Replacement on a NUMA Multiprocessor.	SIGMETRICS	1992	DBLP DOI BibTeX RDF
41	Songnian Zhou, Tim Brecht	Processor-Pool-Based Scheduling for Large-Scale NUMA Multiprocessors.	SIGMETRICS	1991	DBLP DOI BibTeX RDF
41	Alan L. Cox, Robert J. Fowler	The Implementation of a Coherent Memory Abstraction on a NUMA Multiprocessor: Experiences with PLATINUM.	SOSP	1989	DBLP DOI BibTeX RDF
37	Martin Schmollinger, Michael Kaufmann 0001	Algorithms for SMP-Clusters Dense Matrix-Vector Multiplication.	IPDPS	2002	DBLP DOI BibTeX RDF
37	Shigeki Shibayama, Kazumasa Hamaguchi, Toshiyuki Fukui, Yoshiaki Sudo, Tomohiko Shimoyama, Shuichi Nakamura	An Optical Bus Computer Cluster with a deferred cache coherence protocol.	ICPADS	1996	DBLP DOI BibTeX RDF	Optical Bus Computer Cluster, deferred cache coherence protocol, optical star-coupler, one-hop simultaneous broadcasting, wavelength multiplexing, deferred cache coherence, coherence maintenance, protocols, wavelength-division multiplexing, optical interconnections, cache storage
37	Harjinder S. Sandhu	Integrating applications with cache and memory management on a shared-memory multiprocessor.	CASCON	1992	DBLP BibTeX RDF
35	Rui Yang 0005, Joseph Antony, Alistair P. Rendell	Effective Use of Dynamic Page Migration on NUMA Platforms: The Gaussian Chemistry Code on the SunFire X4600M2 System.	ISPAN	2009	DBLP DOI BibTeX RDF	dynamic page migration, data locality, NUMA
35	Marius Pirvu, Nan Ni, Laxmi N. Bhuyan	Exploring the Switch Design Space in a CC-NUMA Multiprocessor Environment.	IPDPS	2000	DBLP DOI BibTeX RDF	input buffer management, CC-NUMA multiprocessors, performance evaluation, arbitration, execution driven simulation, switch design
35	Michael F. P. O'Boyle	A hierarchical locality algorithm for NUMA compilation.	PDP	1995	DBLP DOI BibTeX RDF	hierarchical locality algorithm, NUMA compilation, latency overhead, parallel hierarchical memory machines, nonlocal accesses, compound sequenc, complex array accesses, general iteration spaces, strip mining, parallel machines, program compilers, storage management, distributed memory systems, memory structure, program locality, unimodular transformations, data alignment, compiler algorithm
33	Iulia Stirb	Improving runtime performance and energy consumption through balanced data locality with NUMA-BTLP and NUMA-BTDM static algorithms for thread classification and thread type-aware mapping.	Int. J. Comput. Sci. Eng.	2020	DBLP DOI BibTeX RDF
33	Chenhao Xie 0001, Xin Fu, Mingsong Chen, Shuaiwen Leon Song	OO-VR: NUMA Friendly Object-Oriented VR Rendering Framework For Future NUMA-Based Multi-GPU Systems.	CoRR	2020	DBLP BibTeX RDF
33	Chenhao Xie 0001, Xin Fu, Mingsong Chen, Shuaiwen Leon Song	OO-VR: NUMA friendly object-oriented VR rendering framework for future NUMA-based multi-GPU systems.	ISCA	2019	DBLP DOI BibTeX RDF
33	Probir Roy, Shuaiwen Leon Song, Sriram Krishnamoorthy, Abhinav Vishnu, Dipanjan Sengupta, Xu Liu 0001	NUMA-Caffe: NUMA-Aware Deep Learning Neural Networks.	ACM Trans. Archit. Code Optim.	2018	DBLP DOI BibTeX RDF
33	Philippe Virouleau	Etude et amélioration de l'exploitation des architectures NUMA à travers des supports exécutifs. (Studying and improving the use of NUMA architectures through runtime systems).		2018	RDF
33	Gauthier Voron	Efficient Virtualization of NUMA Architectures. (Virtualisation Efficace d'Architectures NUMA).		2018	RDF
33	Iulia Stirb	NUMA-BTDM: A Thread Mapping Algorithm for Balanced Data Locality on NUMA Systems.	PDCAT	2016	DBLP DOI BibTeX RDF
33	Lokesh Gidra	Garbage Collector for memory intensive applications on NUMA architectures. (ramasse-miette pour les applications avec forte utilisation de la mémoire sur architectures numa).		2015	RDF
33	Andi Drebes	Dynamic optimization of data-flow task-parallel applications for large-scale NUMA systems. (Optimisation dynamique des applications à base de tâches data-flow pour des machines NUMA).		2015	RDF
33	Baptiste Lepers	Improving performance on NUMA systems. (Amélioration de performance sur les architectures NUMA).		2014	RDF
33	Qiuming Luo, Chengjian Liu, Chang Kong, Ye Cai	MAP-numa: Access Patterns Used to Characterize the NUMA Memory Access Optimization Techniques and Algorithms.	NPC	2012	DBLP DOI BibTeX RDF
33	Márcio Castro 0001, Luiz Gustavo Fernandes, Christiane Pousa Ribeiro, Jean-François Méhaut, Marilton Sanchotene de Aguiar	NUMA-ICTM: A parallel version of ICTM exploiting memory placement strategies for NUMA machines.	IPDPS	2009	DBLP DOI BibTeX RDF
33	Mathieu Faverge	Ordonnancement hybride statique-dynamique en algèbre linéaire creuse pour de grands clusters de machines NUMA et multi-cœurs. (Static-Dynamic Hybrid Scheduling in sparse linear algebra for large clusters of NUMA and multi-cores architectures).		2009	RDF
31	Markus Nordén, Henrik Löf, Jarmo Rantakokko, Sverker Holmgren	Dynamic Data Migration for Structured AMR Solvers.	Int. J. Parallel Program.	2007	DBLP DOI BibTeX RDF	SAMR, Geographical locality, Shared memory, OpenMP, Graph partitioning, Adaptive mesh refinement, cc-NUMA, Page migration
31	Samuel Thibault, François Broquedis, Brice Goglin, Raymond Namyst, Pierre-André Wacrenier	An Efficient OpenMP Runtime System for Hierarchical Architectures.	IWOMP	2007	DBLP DOI BibTeX RDF	Hierarchical Thread Scheduling, Multi-Core, OpenMP, SMP, NUMA, Bubbles, Nested Parallelism
31	Marco Galluzzi, Valentin Puente, Adrián Cristal, Ramón Beivide, José-Ángel Gregorio, Mateo Valero	A first glance at Kilo-instruction based multiprocessors.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	ROB, in-flight instructions, shared-memory multiprocessors, CC-NUMA, memory wall, instruction window, Kilo-instruction processors
31	Manuel E. Acacio, José González 0002, José M. García 0001, José Duato	Reducing the Latency of L2 Misses in Shared-Memory Multiprocessors through On-Chip Directory Integration.	PDP	2002	DBLP DOI BibTeX RDF	L2 misses, on-chip directory integration, multilevel directory, cc-NUMA
31	Manuel E. Acacio, José González 0002, José M. García 0001, José Duato	A Novel Approach to Reduce L2 Miss Latency in Shared-Memory Multiprocessors.	IPDPS	2002	DBLP DOI BibTeX RDF	L2 misses, On-chip Integration, Three-Level Directory, Shared Data Cache, Scalability, cc-NUMA
31	Leonid Oliker, Rupak Biswas	Parallelization of a Dynamic Unstructured Algorithm Using Three Leading Programming Paradigms.	IEEE Trans. Parallel Distributed Syst.	2000	DBLP DOI BibTeX RDF	CC-NUMA machines, parallel implementation techniques, application performance studies, unstructured mesh adaptation, Distributed memory systems, multithreaded architectures
31	Josep Torrellas, Liuxi Yang, Anthony-Trung Nguyen	Toward a Cost-Effective DSM Organization That Exploits Processor-Memory Integration.	HPCA	2000	DBLP DOI BibTeX RDF	directory controller, multiprocessor, reconfigurable, PIM, DSM, coherence protocol, NUMA, processor-in-memory, COMA
31	Jonas Skeppstedt	Overcoming Limitations of Prefetching in Multiprocessors by Compiler-Initiated Coherence Actions.	IEEE PACT	1997	DBLP DOI BibTeX RDF	compiler-initiated coherence, CC-NUMA multiprocessor, compiler-controlled prefetching, read-stall time, write-latency, read-latency, memory access latency reduction, migratory sharing, parallel architectures, multiprocessors, prefetching, prefetch, compiler-analysis
31	Injong Rhee	Optimizing a FIFO, scalable spin lock using consistent memory.	RTSS	1996	DBLP DOI BibTeX RDF	FIFO optimization, scalable spin lock, consistent memory, FIFO queue based scalable spin lock, non atomic read, atomic swap operation, timing guarantee, scalable mutual exclusion problem, NUMA architectures, FSSL algorithm, write operations, non atomic memory operations, weakly consistent memories, multiprocessors, shared memory systems, real time applications, atomic operations
31	Walid R. Tout, Sakti Pramanik	Distributed Load Balancing for Parallel Main Memory Hash Join.	IEEE Trans. Parallel Distributed Syst.	1995	DBLP DOI BibTeX RDF	NUMA architecture, load balancing, parallel processing, database systems, Relational join
29	Tomohiro Nishiguchi, Nobutaka Kuroki, Masahiro Numa	Technology Remapping Approach Using Multi-Gate Reconfigurable Cells for Post-Mask Functional ECO.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2024	DBLP DOI BibTeX RDF
29	Yusuke Numa, Atsushi Ohnishi	Supporting change management of UML class diagrams.	KES	2023	DBLP DOI BibTeX RDF
29	Ze Zhou Wang, Numa Joy Bertola, Siang Huat Goh, Ian F. C. Smith	Systematic selection of field response measurements for excavation back analysis.	Adv. Eng. Informatics	2021	DBLP DOI BibTeX RDF
29	Kazuya Urazoe, Nobutaka Kuroki, Yu Kato, Shinya Ohtani, Tetsuya Hirose, Masahiro Numa	Multi-Category Image Super-Resolution with Convolutional Neural Network and Multi-Task Learning.	IEICE Trans. Inf. Syst.	2021	DBLP DOI BibTeX RDF
29	Masaya Nishi, Kaori Matsumoto, Nobutaka Kuroki, Masahiro Numa, Hikaru Sebe, Ryo Matsuzuka, Osamu Maida, Daisuke Kanemoto, Tetsuya Hirose	A 35-mV supply ring oscillator consisting of stacked body bias inverters for extremely low-voltage LSIs.	IEICE Electron. Express	2021	DBLP DOI BibTeX RDF
29	Kazuya Urazoe, Nobutaka Kuroki, Yu Kato, Shinya Ohtani, Tetsuya Hirose, Masahiro Numa	Improvement of Luminance Isotropy for Convolutional Neural Networks-Based Image Super-Resolution.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2020	DBLP DOI BibTeX RDF
29	Kaori Matsumoto, Hiroki Asano, Yuichiro Nakazawa, Nobutaka Kuroki, Masahiro Numa, Osamu Maida, Daisuke Kanemoto, Tetsuya Hirose	An 11.8 nA ultra-low power active diode using a hysteresis common gate comparator for low-power energy harvesting systems.	IEICE Electron. Express	2020	DBLP DOI BibTeX RDF
29	Kunihiko Taya, Nobutaka Kuroki, Naoto Takeda, Tetsuya Hirose, Masahiro Numa	Detecting tampered regions in JPEG images via CNN.	NEWCAS	2020	DBLP DOI BibTeX RDF
29	Masaya Nishi, Kaori Matsumoto, Nobutaka Kuroki, Masahiro Numa, Hikaru Sebe, Ryo Matsuzuka, Osamu Maida, Daisuke Kanemoto, Tetsuya Hirose	A 34-mV Startup Ring Oscillator Using Stacked Body Bias Inverters for Extremely Low-Voltage Thermoelectric Energy Harvesting.	NEWCAS	2020	DBLP DOI BibTeX RDF
29	Paul Azunre, Craig Corcoran, Numa Dhamani, Jeffrey L. Gleason, Garrett Honke, David Sullivan, Rebecca Ruppel, Sandeep Verma, Jonathon Morgan	Semantic Classification of Tabular Datasets via Character-Level Convolutional Neural Networks.	CoRR	2019	DBLP BibTeX RDF
29	Numa Dhamani, Paul Azunre, Jeffrey L. Gleason, Craig Corcoran, Garrett Honke, Steve Kramer, Jonathon Morgan	Using Deep Networks and Transfer Learning to Address Disinformation.	CoRR	2019	DBLP BibTeX RDF
29	Numa Joy Bertola, Marco Cinelli, Simon Casset, Salvatore Corrente, Ian F. C. Smith	A multi-criteria decision framework to support measurement-system design for bridge load testing.	Adv. Eng. Informatics	2019	DBLP DOI BibTeX RDF
29	Craig Corcoran, Renee DiResta, David Morar, Numa Dhamani, David Sullivan, Jeffrey L. Gleason, Paul Azunre, Steve Kramer, Becky Ruppel	Disinformation: Detect to Disrupt.	TTO	2019	DBLP BibTeX RDF
29	Masaya Nishi, Yuichiro Nakazawa, Kaori Matsumoto, Nobutaka Kuroki, Masahiro Numa, Ryo Matsuzuka, Osamu Maida, Daisuke Kanemoto, Tetsuya Hirose	Sub-0.1V Input, Low-Voltage CMOS Driver Circuit for Multi-Stage Switched Capacitor Voltage Boost Converter.	ICECS	2019	DBLP DOI BibTeX RDF