Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
51 | Dmitry V. Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose |
Isolating Short-Lived Operands for Energy Reduction. |
IEEE Trans. Computers |
2004 |
DBLP DOI BibTeX RDF |
|
49 | Sivaram Gopalakrishnan, Priyank Kalla, Florian Enescu |
Optimization of Arithmetic Datapaths with Finite Word-Length Operands. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
arithmetic datapaths, finite word length, operands, polynomial computations, finite integer rings, CAD, area optimization, bit vectors |
47 | Ilhyun Kim, Mikko H. Lipasti |
Half-Price Architecture. |
ISCA |
2003 |
DBLP DOI BibTeX RDF |
|
47 | Gyula Magó |
Copying operands versus copying results: A solution to the problem of large operands in FFP'S. |
FPCA |
1981 |
DBLP DOI BibTeX RDF |
|
44 | Belle W. Y. Wei, He Du, Honglu Chen |
A complex-number multiplier using radix-4 digits. |
IEEE Symposium on Computer Arithmetic |
1995 |
DBLP DOI BibTeX RDF |
complex-number multiplier, radix-4 digits, arithmetic datapath, complex-number digital signal processor, binary signed digits, fast multiplication, compact layout, three-multiplication scheme, radix-4 operands, delays, delay, encoding, digital arithmetic, multiplying circuits, binary additions, coding scheme |
42 | Kaijie Wu 0001, Ramesh Karri |
Algorithm-level recomputing with shifted operands-a register transfer level concurrent error detection technique. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
42 | Anthony S. Fong |
A computer architecture with access control and cache option tags on individual instruction operands. |
SIGARCH Comput. Archit. News |
2003 |
DBLP DOI BibTeX RDF |
operand descriptor, optional encaching, system attributes, access control, data coherency |
42 | Dmitry Ponomarev 0001, Gurhan Kucuk, Oguz Ergin, Kanad Ghose |
Reducing Datapath Energy through the Isolation of Short-Lived Operands. |
IEEE PACT |
2003 |
DBLP DOI BibTeX RDF |
|
38 | Masaaki Kondo, Hiroshi Nakamura |
A Small, Fast and Low-Power Register File by Bit-Partitioning. |
HPCA |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Brian R. Mestan, Mikko H. Lipasti |
Exploiting Partial Operand Knowledge. |
ICPP |
2003 |
DBLP DOI BibTeX RDF |
|
38 | Norman Ramsey |
Relocating Machine Instructions by Currying. |
PLDI |
1996 |
DBLP DOI BibTeX RDF |
|
35 | Jean-Claude Bajard, Laurent-Stéphane Didier, Peter Kornerup |
An IWS Montgomery Modular Multiplication Algorithm. |
IEEE Symposium on Computer Arithmetic |
1997 |
DBLP DOI BibTeX RDF |
RNS Montgomery modular multiplication algorithm, very large operands, mixed radix, processor ring, redundant high-radix implementation, residue number systems, residue number system, computation time, table look-up |
35 | Geoff Barrett |
Formal Methods Applied to a Floating-Point Number System. |
IEEE Trans. Software Eng. |
1989 |
DBLP DOI BibTeX RDF |
floating-point number system, binary floating-point arithmetic, ANSI/IEEE Std. 754-1985, set-theoretic specification language, sequential components, unpack, operands, proven rules, mathematically rigorous method, Inmos IMS T800 transputer, formal specification, formal methods, specification languages, digital arithmetic, Z, formalization, round, pack, program development, IEEE standard, floating-point unit, internal representations |
33 | Maziar Goudarzi, Tohru Ishihara |
Instruction cache leakage reduction by changing register operands and using asymmetric sram cells. |
ACM Great Lakes Symposium on VLSI |
2008 |
DBLP DOI BibTeX RDF |
asymmetric sram, leakage, instruction cache, register renaming |
33 | Namrata Shekhar, Priyank Kalla, Florian Enescu |
Equivalence verification of arithmetic datapaths with multiple word-length operands. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Daehong Kim, Dongwan Shin, Kiyoung Choi |
Pipelining with common operands for power-efficient linear systems. |
IEEE Trans. Very Large Scale Integr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
33 | Tongquan Wei, Kaijie Wu 0001, Ramesh Karri, Alex Orailoglu |
Fault tolerant quantum cellular array (QCA) design using Triple Modular Redundancy with shifted operands. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
33 | Kaushal R. Gandhi, Nihar R. Mahapatra |
A Study of Hardware Techniques That Dynamically Exploit Frequent Operands to Reduce Power Consumption in Integer Function Units. |
ICCD |
2003 |
DBLP DOI BibTeX RDF |
|
33 | Jean-Michel Muller |
Complex Division with Prescaling of Operands. |
ASAP |
2003 |
DBLP DOI BibTeX RDF |
|
33 | Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou |
High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands. |
IEEE Symposium on Computer Arithmetic |
2001 |
DBLP DOI BibTeX RDF |
|
33 | Monica Alderighi, Sergio D'Angelo, Giacomo R. Sechi, Cecilia Metra |
Achieving Fault-Tolerance by Shifted and Rotated Operands in TMR Non-Diverse ALUs. |
DFT |
2000 |
DBLP DOI BibTeX RDF |
|
33 | Brian R. Nickerson |
Graph Coloring Register Allocation for Processors with Multi-Register Operands. |
PLDI |
1990 |
DBLP DOI BibTeX RDF |
Intel 80960 |
28 | Jatan P. Shah, Rama Sangireddy |
Higher Clock Rate at Comparable IPC Through Reduced Circuit Complexity in Instruction Format Based Pipeline Clustering. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
28 | Mallik Kandala, Wei Zhang 0002, Laurence Tianruo Yang |
An Area-Efficient Approach to Improving Register File Reliability against Transient Errors. |
AINA Workshops (1) |
2007 |
DBLP DOI BibTeX RDF |
|
28 | Kaushal R. Gandhi, Nihar R. Mahapatra |
Exploiting data-dependent slack using dynamic multi-VDD to minimize energy consumption in datapath circuits. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Sanjay Misra |
Modified Cognitive Complexity Measure. |
ISCIS |
2006 |
DBLP DOI BibTeX RDF |
cognitive weights, basic control structures, cognitive complexity measure, Software metrics |
28 | Ramkumar Jayaseelan, Haibin Liu, Tulika Mitra |
Exploiting forwarding to improve data bandwidth of instruction-set extensions. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
instruction-set extensions, data forwarding |
28 | Sorin Dan Cotofana, Casper Lageweg, Stamatis Vassiliadis |
Addition Related Arithmetic Operations via Controlled Transport of Charge. |
IEEE Trans. Computers |
2005 |
DBLP DOI BibTeX RDF |
single electron technology, electron counting, multiplication, SET, addition |
28 | Robert D. Kenney, Michael J. Schulte |
High-Speed Multioperand Decimal Adders. |
IEEE Trans. Computers |
2005 |
DBLP DOI BibTeX RDF |
multioperand adders, Computer arithmetic, hardware designs, decimal arithmetic |
28 | Hongkyu Kim, D. Scott Wills, Linda M. Wills |
Empirical Analysis of Operand Usage and Transport in Multimedia Applications. |
IWSOC |
2004 |
DBLP DOI BibTeX RDF |
|
28 | Madhubanti Mukherjee, Ranga Vemuri |
A Novel Synthesis Strategy Driven by Partial Evaluation Based Circuit Reduction for Application Specific DSP Circuits. |
ICCD |
2003 |
DBLP DOI BibTeX RDF |
|
28 | Michael J. Schulte, Louis Marquette, Shankar Krithivasan, E. George Walters III, John Glossner |
Combined Multiplication and Sum-of-Squares Units. |
ASAP |
2003 |
DBLP DOI BibTeX RDF |
|
28 | Milan Ojstersek, Viljem Zumer, Ljubo Pipan |
Efficient execution of parallel programs using partial strict triggering of program graph nodes. |
ICPADS |
1997 |
DBLP DOI BibTeX RDF |
partial strict triggering, program graph nodes, coarse grained program graph nodes, VL, DSH scheduling algorithms, parallel programming, parallel programs, CPM |
28 | Sorin Cotofana, Stamatis Vassiliadis |
delta-Bit serial binary addition with linear threshold networks. |
J. VLSI Signal Process. |
1996 |
DBLP DOI BibTeX RDF |
|
28 | Tudor Jebelean |
Design of a systolic coprocessor for rational addition. |
ASAP |
1995 |
DBLP DOI BibTeX RDF |
systolic coprocessor, rational addition, exact division, field programmable gate arrays, parallel architectures, systolic arrays, digital arithmetic, multiplication, addition, subtraction, rational numbers, GCD |
28 | S. E. Richardson |
Exploiting trivial and redundant computation. |
IEEE Symposium on Computer Arithmetic |
1993 |
DBLP DOI BibTeX RDF |
|
28 | Ben Heggy, Mary Lou Soffa |
Architectural support for register allocation in the presence of aliasing. |
SC |
1990 |
DBLP DOI BibTeX RDF |
|
28 | J. Philip Benkard |
Replicate each, anyone? |
APL |
1987 |
DBLP DOI BibTeX RDF |
APL |
28 | Edward L. Robertson |
Code Generation and Storage Allocation for Machines with Span-Dependent Instructions. |
ACM Trans. Program. Lang. Syst. |
1979 |
DBLP DOI BibTeX RDF |
|
28 | Brian Randell, L. J. Russell |
Single-Scan Techniques for the Translation of Arithmetic Expressions into ALGOL 60. |
J. ACM |
1964 |
DBLP DOI BibTeX RDF |
ALGOL |
26 | Toshinori Sato, Itsujiro Arita |
Table size reduction for data value predictors by exploiting narrow width values. |
ICS |
2000 |
DBLP DOI BibTeX RDF |
narrow width operands, instruction level parallelism, hardware implementation, value prediction, data speculation |
26 | Jean-Michel Muller |
Some Characterizations of Functions Computable in On-Line Arithmetic. |
IEEE Trans. Computers |
1994 |
DBLP DOI BibTeX RDF |
piecewise affine functions, operands, arbitrarily long length, computability, digital arithmetic, finite automata, multiplication, division, elementary functions, finite automaton, online computing, rational numbers |
26 | Peter Kornerup, David W. Matula |
An Algorithm for Redundant Binary Bit-Pipelined Rational Arithmetic. |
IEEE Trans. Computers |
1990 |
DBLP DOI BibTeX RDF |
tree pipeline, Gosper, redundant binary bit-pipelined rational arithmetic, redundant binary representation, rational operands, partial quotient arithmetic algorithm, online arithmetic unit, signed bit level, binary radix, binary rational representation, online delays, simulation, parallel computation, redundancy, interconnection, product, digital arithmetic, number theory, difference, quotient, sum |
26 | Sally G. Smith |
Comments on "A Signed Bit-Sequential Multiplier". |
IEEE Trans. Computers |
1989 |
DBLP DOI BibTeX RDF |
signed bit-sequential multiplier, unsigned operands, digital arithmetic |
26 | James W. Watterson, Jill J. Hallenbeck |
Modulo 3 Residue Checker: New Results on Performance and Cost. |
IEEE Trans. Computers |
1988 |
DBLP DOI BibTeX RDF |
modulo-3 residue code checker, pipelined serial multiplier, concurrent self-test, minimum error latency, multiplier input operands, 4- mu m NMOS, standard cell design, performance evaluation, integrated circuit testing, error detection, automatic testing, digital arithmetic, pipeline processing, multiplying circuits, built in test, field effect integrated circuits, error detection coverage |
23 | Xin Qiao, Qingyu Guo, Xiyuan Tang, Jiahao Song, Renjie Wei, Meng Li 0004, Runsheng Wang, Yuan Wang 0001 |
A 16.38TOPS and 4.55POPS/W SRAM Computing-in-Memory Macro for Signed Operands Computation and Batch Normalization Implementation. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
|
23 | Constantinos Efstathiou, Ioannis Kouretas, Paris Kitsos |
On the modulo 2n+1 addition and subtraction for weighted operands. |
Microprocess. Microsystems |
2023 |
DBLP DOI BibTeX RDF |
|
23 | Peter Fritz |
Operands and Instances. |
Rev. Symb. Log. |
2023 |
DBLP DOI BibTeX RDF |
|
23 | Simon Friedrich, Shambhavi Balamuthu Sampath, Robert Wittig, Manoj Rohit Vemparala, Nael Fasfous, Emil Matús, Walter Stechele, Gerhard P. Fettweis |
Lightweight Instruction Set for Flexible Dilated Convolutions and Mixed-Precision Operands. |
ISQED |
2023 |
DBLP DOI BibTeX RDF |
|
23 | Vishesh Mishra, Urbi Chatterjee |
VMEO: Vector Modeling Errors and Operands for Approximate adders. |
IACR Cryptol. ePrint Arch. |
2022 |
DBLP BibTeX RDF |
|
23 | Rui Liu, Xiaoyu Zhang 0009, Xiaoming Chen 0003, Yinhe Han 0001, Minghua Tang |
FeMIC: Multi-Operands in-Memory Computing Based on FeFETs. |
ASP-DAC |
2022 |
DBLP DOI BibTeX RDF |
|
23 | David J. Schlais, Heng Zhuo, Mikko H. Lipasti |
Work-in-Progress: NoRF: A Case Against Register File Operands in Tightly-Coupled Accelerators. |
CASES |
2022 |
DBLP DOI BibTeX RDF |
|
23 | Xin Wang, Wei Zhang |
Reducing GPU Energy Consumption by Packing Narrow-Width Operands. |
J. Comput. Sci. Eng. |
2021 |
DBLP DOI BibTeX RDF |
|
23 | Jiaqi Gu, Zheng Zhao 0003, Chenghao Feng, Zhoufeng Ying, Ray T. Chen, David Z. Pan |
O2NN: Optical Neural Networks with Differential Detection-Enabled Optical Operands. |
DATE |
2021 |
DBLP DOI BibTeX RDF |
|
23 | Meng Li 0004, Yilei Li, Vikas Chandra |
Improving Efficiency in Neural Network Accelerator using Operands Hamming Distance Optimization. |
ASP-DAC |
2021 |
DBLP DOI BibTeX RDF |
|
23 | Sanlin Chen, Gang Cai, Zhihong Huang |
An Enhanced DSP Block Architecture for FPGA Supporting Multi-operands Addition Operation. |
ASICON |
2021 |
DBLP DOI BibTeX RDF |
|
23 | Zhiting Lin, Honglan Zhan, Xuan Li, Chunyu Peng, Wenjuan Lu, Xiulong Wu, Junning Chen |
In-Memory Computing With Double Word Lines and Three Read Ports for Four Operands. |
IEEE Trans. Very Large Scale Integr. Syst. |
2020 |
DBLP DOI BibTeX RDF |
|
23 | Ram Rangan, Mark W. Stephenson, Aditya Ukarande, Shyam Murthy, Virat Agarwal, Marc Blackstein |
Zeroploit: Exploiting Zero Valued Operands in Interactive Gaming Applications. |
ACM Trans. Archit. Code Optim. |
2020 |
DBLP DOI BibTeX RDF |
|
23 | Meng Li 0004, Yilei Li, Pierce Chuang, Liangzhen Lai, Vikas Chandra |
Improving Efficiency in Neural Network Accelerator Using Operands Hamming Distance optimization. |
CoRR |
2020 |
DBLP BibTeX RDF |
|
23 | Dibakar Gope, Jesse G. Beu, Matthew Mattina |
High Throughput Matrix-Matrix Multiplication between Asymmetric Bit-Width Operands. |
CoRR |
2020 |
DBLP BibTeX RDF |
|
23 | Daniel Jancarczyk, Volodymyr Rudnytskyi, Roksolana Breus, Mykhailo Pustovit, Olga Veselska, Ruslana Ziubina |
Two-Operand Operations of Strict Stable Cryptographic Coding with Different Operands' Bits. |
IDAACS-SWS |
2020 |
DBLP DOI BibTeX RDF |
|
23 | Xin Wang 0056, Wei Zhang 0002 |
Packing Narrow-Width Operands to Improve Energy Efficiency of General-Purpose GPU Computing. |
HPEC |
2020 |
DBLP DOI BibTeX RDF |
|
23 | Poulami Das 0003, Debapriya Basu Roy, Debdeep Mukhopadhyay |
Automatic generation of HCCA-resistant scalar multiplication algorithm by proper sequencing of field multiplier operands. |
J. Cryptogr. Eng. |
2019 |
DBLP DOI BibTeX RDF |
|
23 | Vasileios Leon, Sotirios Xydis, Dimitrios Soudris, Kiamal Z. Pekmestzi |
Energy-efficient VLSI implementation of multipliers with double LSB operands. |
IET Circuits Devices Syst. |
2019 |
DBLP DOI BibTeX RDF |
|
23 | Li Jiang |
The identical operands commutative encryption and watermarking based on homomorphism. |
Multim. Tools Appl. |
2018 |
DBLP DOI BibTeX RDF |
|
23 | Xin Wang 0056, Wei Zhang 0002 |
Packing Narrow-Width Operands to Improve GPU Performance. |
J. Comput. Sci. Eng. |
2018 |
DBLP DOI BibTeX RDF |
|
23 | Serhii Mashchenko |
Intersections and unions of fuzzy sets of operands. |
Fuzzy Sets Syst. |
2018 |
DBLP DOI BibTeX RDF |
|
23 | Eduardo Chielle, Oleg Mazonka, Nektarios Georgios Tsoutsos, Michail Maniatakos |
E3: A Framework for Compiling C++ Programs with Encrypted Operands. |
IACR Cryptol. ePrint Arch. |
2018 |
DBLP BibTeX RDF |
|
23 | Chibuike Ugwuoke, Zekeriya Erkin, Reginald L. Lagendijk |
Secure Fixed-point Division for Homomorphically Encrypted Operands. |
ARES |
2018 |
DBLP DOI BibTeX RDF |
|
23 | Krishna Bhowal, Debasree Sarkar, Susanta Biswas, Partha Pratim Sarkar |
A steganographic approach to hide secret data in digital audio based on XOR operands triplet property with high embedding rate and good quality audio. |
Turkish J. Electr. Eng. Comput. Sci. |
2017 |
DBLP DOI BibTeX RDF |
|
23 | Xin Wang 0056, Wei Zhang 0002 |
GPU Register Packing: Dynamically Exploiting Narrow-Width Operands to Improve Performance. |
TrustCom/BigDataSE/ICESS |
2017 |
DBLP DOI BibTeX RDF |
|
23 | Poulami Das 0003, Debapriya Basu Roy, Debdeep Mukhopadhyay |
Automatic Generation of HCCA Resistant Scalar Multiplication Algorithm by Proper Sequencing of Field Multiplier Operands. |
PROOFS |
2017 |
DBLP DOI BibTeX RDF |
|
23 | Wafaa S. Sayed, Hossam A. H. Fahmy |
What are the Correct Results for the Special Values of the Operands of the Power Operation? |
ACM Trans. Math. Softw. |
2016 |
DBLP DOI BibTeX RDF |
|
23 | Darjn Esposito, Davide De Caro, Antonio Giuseppe Maria Strollo |
Variable Latency Speculative Parallel Prefix Adders for Unsigned and Signed Operands. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2016 |
DBLP DOI BibTeX RDF |
|
23 | Mehran Mozaffari Kermani, Rajkumar Ramadoss, Reza Azarderakhsh |
Efficient error detection architectures for CORDIC through recomputing with encoded operands. |
ISCAS |
2016 |
DBLP DOI BibTeX RDF |
|
23 | Kiamal Z. Pekmestzi, Kostas Tsoumanis, Constantinos Efstathiou |
Fused modulo 2n + 1 add-multiply unit for weighted operands. |
DTIS |
2016 |
DBLP DOI BibTeX RDF |
|
23 | Poulami Das 0003, Debapriya Basu Roy, Debdeep Mukhopadhyay |
Exploiting the Order of Multiplier Operands: A Low Cost Approach for HCCA Resistance. |
IACR Cryptol. ePrint Arch. |
2015 |
DBLP BibTeX RDF |
|
23 | Takeshi Sugawara 0001, Daisuke Suzuki, Minoru Saeki |
Two Operands of Multipliers in Side-Channel Attack. |
IACR Cryptol. ePrint Arch. |
2015 |
DBLP BibTeX RDF |
|
23 | Takeshi Sugawara 0001, Daisuke Suzuki, Minoru Saeki |
Two Operands of Multipliers in Side-Channel Attack. |
COSADE |
2015 |
DBLP DOI BibTeX RDF |
|
23 | Xiaoxiao Zhang, Farid Boussaïd, Amine Bermak |
32 Bit ×32 Bit Multiprecision Razor-Based Dynamic Voltage Scaling Multiplier With Operands Scheduler. |
IEEE Trans. Very Large Scale Integr. Syst. |
2014 |
DBLP DOI BibTeX RDF |
|
23 | Xiaofei Guo, Debdeep Mukhopadhyay, Chenglu Jin, Ramesh Karri |
NREPO: Normal Basis Recomputing with Permuted Operands. |
IACR Cryptol. ePrint Arch. |
2014 |
DBLP BibTeX RDF |
|
23 | Kostas Tsoumanis, Constantinos Efstathiou, Kiamal Z. Pekmestzi |
Modulo 2n+1 addition and multiplication for redundant operands. |
IDT |
2014 |
DBLP DOI BibTeX RDF |
|
23 | Mohamed Karroumi, Benjamin Richard, Marc Joye |
Addition with Blinded Operands. |
COSADE |
2014 |
DBLP DOI BibTeX RDF |
|
23 | Xiaofei Guo, Debdeep Mukhopadhyay, Chenglu Jin, Ramesh Karri |
NREPO: Normal basis Recomputing with Permuted Operands. |
HOST |
2014 |
DBLP DOI BibTeX RDF |
|
23 | Xiaofei Guo, Ramesh Karri |
Recomputing with Permuted Operands: A Concurrent Error Detection Approach. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2013 |
DBLP DOI BibTeX RDF |
|
23 | Xiaofei Guo, Ramesh Karri |
Recomputing with Permuted Operands: A Concurrent Error Detection Approach. |
IACR Cryptol. ePrint Arch. |
2013 |
DBLP BibTeX RDF |
|
23 | Jongwon Lee, Jonghee M. Youn, Jihoon Lee, Minwook Ahn, Yunheung Paek |
Dynamic Operands Insertion for VLIW Architecture with a Reduced Bit-width Instruction Set. |
IPDPS |
2012 |
DBLP DOI BibTeX RDF |
|
23 | Hirotaka Kawashima, Naofumi Takagi |
Partial Product Generation Utilizing the Sum of Operands for Reduced Area Parallel Multipliers. |
IPSJ Trans. Syst. LSI Des. Methodol. |
2011 |
DBLP DOI BibTeX RDF |
|
23 | José-Luis Sánchez-Romero, Higinio Mora Mora, Jerónimo Mora Pascual, Antonio Jimeno-Morenilla |
Function approximation on decimal operands. |
Digit. Signal Process. |
2011 |
DBLP DOI BibTeX RDF |
|
23 | Shlomi Dolev, Sergey Frenkel, Dan E. Tamir |
Computer Arithmetic Preserving Hamming Distance of Operands in Operation Result |
CoRR |
2011 |
DBLP BibTeX RDF |
|
23 | Bijan Alizadeh, Masahiro Fujita |
Modular equivalence verification of polynomial datapaths with multiple word-length operands. |
HLDVT |
2011 |
DBLP DOI BibTeX RDF |
|
23 | Kenshu Seto, Masahiro Fujita |
Custom Instruction Generation for Configurable Processors with Limited Numbers of Operands. |
IPSJ Trans. Syst. LSI Des. Methodol. |
2010 |
DBLP DOI BibTeX RDF |
|
23 | Ilknur Cansu Kaynak, Yusuf Onur Koçberber, Oguz Ergin |
Reducing the Energy Dissipation of the Issue Queue by Exploiting Narrow Immediate Operands. |
J. Circuits Syst. Comput. |
2010 |
DBLP DOI BibTeX RDF |
|
23 | Costas Efstathiou |
Efficient modulo 2N+1 subtractors for weighted operands. |
ICECS |
2010 |
DBLP DOI BibTeX RDF |
|
23 | Shailendra Jain, Vasantha Erraguntla, Sriram R. Vangal, Yatin Vasant Hoskote, Nitin Borkar, Tulasi Mandepudi, V. P. Karthik |
A 90mW/GFlop 3.4GHz Reconfigurable Fused/Continuous Multiply-Accumulator for Floating-Point and Integer Operands in 65nm. |
VLSI Design |
2010 |
DBLP DOI BibTeX RDF |
multiply-accumulate, Fused and continuous MAC, VLSI, Floating-point |
23 | Liang-Kai Wang, Michael J. Schulte |
A Decimal Floating-Point Adder with Decoded Operands and a Decimal Leading-Zero Anticipator. |
IEEE Symposium on Computer Arithmetic |
2009 |
DBLP DOI BibTeX RDF |
|
23 | Miklós Erdélyi-Szabó, László Kálmán, Agi Kurucz |
Towards a natural language semantics without functors and operands. |
J. Log. Lang. Inf. |
2008 |
DBLP DOI BibTeX RDF |
Finite axiomatisability, Finite entailment problem, Function/argument metaphor, Pieces of evidence, Measurements, Completeness, Compositionality, Decision algorithm, Natural language semantics |
23 | Eduardo A. C. da Costa, José Monteiro 0001, Sergio Bampi |
A new array architecture for signed multiplication using Gray encoded radix-2m operands. |
Integr. |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Ajay Kumar Verma, Paolo Ienne |
Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
multiplier-like circuits, XOR-dominated circuits, datapath design, netlist optimization, carry-save form, column compressors, XOR operations, logic synthesizers, algebraic factoring, computer arithmetic, logic synthesis, digital design, parallel multipliers |
23 | Naveed Ali, Shoab A. Khan, Naveed Sarfraz Khattak |
Equivalence Verification of Arithmetic Data Paths With Multiple Word-Length Operands. |
FCS |
2007 |
DBLP BibTeX RDF |
|