Search results for "out-of-order"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
45	Eun-Gu Jung, Jeong-Gun Lee, Sanghoon Kwak, Kyoung-Sun Jhang, Jeong-A Lee, Dong-Soo Har	High performance asynchronous on-chip bus with multiple issue and out-of-order/in-order completion.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	asynchronous on-chip bus, in-order completion, multiple issue, out-of-order completion, SoC, GALS
43	Kiyeon Lee, Sangyeun Cho	In-N-Out: Reproducing Out-of-Order Superscalar Processor Behavior from Reduced In-Order Traces.	MASCOTS	2011	DBLP DOI BibTeX RDF	Superscalar out-of-order processor, performance modeling, trace-driven simulation
43	Graham Cormode, Flip Korn, Srikanta Tirthapura	Time-decaying aggregates in out-of-order streams.	PODS	2008	DBLP DOI BibTeX RDF	asynchronous data streams, out-of-order arrivals
43	Roger Espasa, Mateo Valero, James E. Smith 0001	Out-of-Order Vector Architectures.	MICRO	1997	DBLP DOI BibTeX RDF	memory traffic elimination, microarchitecture, out-of-order execution, memory latency, register renaming, vector architecture, precise interrupts
42	Hans Vandierendonck, Philippe Manet, Thibault Delavallee, Igor Loiselle, Jean-Didier Legat	By-passing the out-of-order execution pipeline to increase energy-efficiency.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	instruction wake-up, energy-efficiency, instruction scheduling, out-of-order execution
42	Jared Stark, Paul Racunas, Yale N. Patt	Reducing the Performance Impact of Instruction Cache Misses by Writing Instructions into the Reservation Stations Out-of-Order.	MICRO	1997	DBLP DOI BibTeX RDF	instruction supply, superscalar processors, out-of-order execution
39	Wade Walker, Harvey G. Cragon	Interrupt Processing in Concurrent Processors.	Computer	1995	DBLP DOI BibTeX RDF	Interrupt processing, imprecise interrupts, concurrent processors, checkpointing, taxonomy, superscalar processors, pipelined processors, out- of-order execution, out-of-order issue, precise interrupts
39	Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith 0001	A mechanistic performance model for superscalar out-of-order processors.	ACM Trans. Comput. Syst.	2009	DBLP DOI BibTeX RDF	Superscalar out-of-order processor, balanced processor design, mechanistic modeling, overprovisioned processor design, pipeline depth, pipeline width, resource scaling, wide front-end dispatch processors, performance modeling, analytical modeling
39	Mingzhu Wei, Mo Liu 0001, Ming Li 0008, Denis Golovnya, Elke A. Rundensteiner, Kajal T. Claypool	Supporting a spectrum of out-of-order event processing technologies: from aggressive to conservative methodologies.	SIGMOD Conference	2009	DBLP DOI BibTeX RDF	out-of-order data, stream processing, complex event processing
39	Xianfeng Li, Abhik Roychoudhury, Tulika Mitra	Modeling out-of-order processors for WCET analysis.	Real Time Syst.	2006	DBLP DOI BibTeX RDF	Worst-case execution time (WCET) analysis, Out-of-order superscalar processor, Branch prediction, Instruction cache
37	Madhavi Gopal Valluri, R. Govindarajan	Evaluating Register Allocation and Instruction Scheduling Techniques in Out-Of-Order Issue Processors.	IEEE PACT	1999	DBLP DOI BibTeX RDF	Out-of-order Issue Processors, Instruction-Level Parallelism, Register Allocation, Instruction Scheduling, Integrated Methods
36	David Tarjan, Michael Boyer, Kevin Skadron	Federation: repurposing scalar cores for out-of-order instruction issue.	DAC	2008	DBLP DOI BibTeX RDF	CMP, multicore, federation, out-of-order
36	Ernie Chan, Enrique S. Quintana-Ortí, Gregorio Quintana-Ortí, Robert A. van de Geijn	Supermatrix out-of-order scheduling of matrix operations for SMP and multi-core architectures.	SPAA	2007	DBLP DOI BibTeX RDF	data affinity, data-flow parallelism, dense linear algebra libraries, dynamic scheduling, out-of-order execution
35	Eric Schnarr, James R. Larus	Fast Out-Of-Order Processor Simulation Using Memoization.	ASPLOS	1998	DBLP DOI BibTeX RDF	out-of-order processor simulation, memoization, direct-execution
34	Eun-Gu Jung, Jeong-Gun Lee, Kyoung-Son Jhang, Jeong-A Lee, Dong-Soo Har	Asynchronous Layered Interface of Multimedia SoCs for Multiple Outstanding Transactions.	J. VLSI Signal Process.	2007	DBLP DOI BibTeX RDF	multiple outstanding transactions, in-order/out-of-order transaction completion, asynchronous on-chip bus, GALS
34	Weiwu Hu, Ji-Ye Zhao, Shi-Qiang Zhong, Xu Yang, Elio Guidetti, Chris Wu	Implementing a 1GHz Four-Issue Out-of-Order Execution Microprocessor in a Standard Cell ASIC Methodology.	J. Comput. Sci. Technol.	2007	DBLP DOI BibTeX RDF	superscalar pipeline, non-blocking cache, synthesis flow, bit-sliced placement, crafted cell, performance evaluation, physical design, out-of-order execution, general-purpose processor
34	Feng Wang, Yongguang Zhang	Improving TCP performance over mobile ad-hoc networks with out-of-order detection and response.	MobiHoc	2002	DBLP DOI BibTeX RDF	MANET, mobile ad hoc networks, TCP, out-of-order
31	Sudarshan K. Srinivasan	Automatic Refinement Checking of Pipelines with Out-of-Order Execution.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	Pipelined machine verification, refinement, out-of-order execution
31	Siddhesh S. Mhambrey, Lawrence T. Clark, Satendra Kumar Maurya, Krzysztof S. Berezowski	Out-of-order issue logic using sorting networks.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	out-of-order processing, ILP, micro-architecture, issue queue, high speed circuits
31	Houman Homayoun, Sudeep Pasricha, Mohammad A. Makhzan, Alexander V. Veidenbaum	Improving performance and reducing energy-delay with adaptive resource resizing for out-of-order embedded processors.	LCTES	2008	DBLP DOI BibTeX RDF	energy-delay, out-of-order embedded processor, resource resizing, performance, architecture
31	Julian Satran, Dafna Sheinwald, Ilan Shimony	Out of Order Incremental CRC Computation.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	cyclic redundancy codes, out-of-order computation, RDMA, CRC
31	Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere	Solving Out-of-Order Communication in Kahn Process Networks.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	producer/consumer pair, in-order, reordering memory, lower bound, rank function, Kahn Process Network, out-of-order
31	Adrián Cristal, José F. Martínez, Josep Llosa, Mateo Valero	A Case for Resource-conscious Out-of-order Processors.	IEEE Comput. Archit. Lett.	2003	DBLP DOI BibTeX RDF	checkpointing, instruction-level parallelism, resource utilization, memory latency, Out-of-order processor
31	Hwa C. Torng, Martin Day	Interrupt Handling for Out-of-Order Execution Processors.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	out-of-order execution processors, low-level execution concurrency, vexing problem, hardware mechanism, concurrency control, latency, exception handling, exception handling, interrupts, superscalars, performance degradation, performance enhancement, instruction window, multiple instructions, interrupt handling
28	Andrew D. Hilton, Amir Roth	Ginger: control independence using tag rewriting.	ISCA	2007	DBLP DOI BibTeX RDF	control independence, out-of-order renaming, selective re-dispatch, branch misprediction
28	Milad Mohammadi, Tor M. Aamodt, William J. Dally	CG-OoO: Energy-Efficient Coarse-Grain Out-of-Order Execution Near In-Order Energy with Near Out-of-Order Performance.	ACM Trans. Archit. Code Optim.	2017	DBLP DOI BibTeX RDF
28	Pavan Balaji, Wu-chun Feng, Sitha Bhagvat, Dhabaleswar K. Panda 0001, Rajeev Thakur, William Gropp	Analyzing the impact of supporting out-of-order communication on in-order performance with iWARP.	SC	2007	DBLP DOI BibTeX RDF
27	Mo Liu 0001, Ming Li 0008, Denis Golovnya, Elke A. Rundensteiner, Kajal T. Claypool	Sequence Pattern Query Processing over Out-of-Order Event Streams.	ICDE	2009	DBLP DOI BibTeX RDF
26	Soner Önder, Rajiv Gupta 0001	Dynamic Memory Disambiguation in the Presence of Out-of-Order Store Issuing.	MICRO	1999	DBLP DOI BibTeX RDF
26	Ronald D. Barnes, John W. Sias, Erik M. Nystrom, Sanjay J. Patel, Nacho Navarro, Wen-mei W. Hwu	Beating In-Order Stalls with "Flea-Flicker" Two-Pass Pipelining.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	cache-miss tolerance, prefetching, out-of-order execution, Runahead execution
25	Stijn Eyerman, Lieven Eeckhout, Koen De Bosschere	Efficient design space exploration of high performance embedded out-of-order processors.	DATE	2006	DBLP DOI BibTeX RDF
25	Ramon Canal, Antonio González 0001	A low-complexity issue logic.	ICS	2000	DBLP DOI BibTeX RDF	in-order issue, instruction issue logic, wide-issue superscalar, out-of-order issue
24	Sibin Mohan, Frank Mueller 0001	Hybrid Timing Analysis of Modern Processor Pipelines via Hardware/Software Interactions.	IEEE Real-Time and Embedded Technology and Applications Symposium	2008	DBLP DOI BibTeX RDF	hybrid timing anlalysis, hardware/software interactions, real-time systems, embedded systems, computer architecture, timing analysis, worst-case execution time, out-of-order execution
24	Weiwu Hu, Fuxin Zhang, Zusong Li	Microarchitecture of the Godson-2 Processor.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF	superscalar pipeline, dynamic scheduling non-blocking cache, load speculation, branch prediction, out-of-order execution, register renaming
24	Emre Özer 0001, Sumedh W. Sathaye, Kishore N. Menezes, Sanjeev Banerjia, Matthew D. Jennings, Thomas M. Conte	A Fast Interrupt Handling Scheme for VLIW Processors.	IEEE PACT	1998	DBLP DOI BibTeX RDF	Interrupt, VLIW, Embedded Processors, ILP, Superscalar, Out-of-order Issue
24	Jiani Guo, Laxmi N. Bhuyan	Load Balancing in a Cluster-Based Web Server for Multimedia Applications.	IEEE Trans. Parallel Distributed Syst.	2006	DBLP DOI BibTeX RDF	Online prediction, partial predictor, global predictor, adaptive partioning, prediction-based load balancing, out-of-order rate
24	Suchitra Raman, Hari Balakrishnan, Murari Srinivasan	An Image Transport Protocol for the Internet.	ICNP	2000	DBLP DOI BibTeX RDF	image transport protocol, Web downloads, in-order byte-stream abstraction, loss-prone congested networks, user-perceived latency, application level framing, out-of-order application data unit, receiver-driven selective reliability, image formats, receiver post-processing algorithms, Internet, Internet, image processing, image processing, wireless networks, transport protocols, image quality, JPEG, JPEG2000, visual communication, UDP, error concealment, PSNR, receiver, network congestion, image transmission, image data, peak signal-to-noise ratio, image rendering, reconstructed images, congestion manager, interactive performance
22	Miquel Pericàs, Adrián Cristal, Rubén González 0001, Daniel A. Jiménez	Chained In-Order/Out-of-Order DoubleCore Architecture.	SBAC-PAD	2005	DBLP DOI BibTeX RDF
22	Jose Renau, James Tuck 0001, Wei Liu 0014, Luis Ceze, Karin Strauss, Josep Torrellas	Tasking with out-of-order spawn in TLS chip multiprocessors: microarchitecture and compilation.	ICS	2005	DBLP DOI BibTeX RDF
22	J. P. Grossman	Cheap Out-of-Order Execution Using Delayed Issue.	ICCD	2000	DBLP DOI BibTeX RDF
22	Jens U. Skakkebæk, Robert B. Jones, David L. Dill	Formal Verification of Out-of-Order Execution Using Incremental Flushing.	CAV	1998	DBLP DOI BibTeX RDF
22	Amit Golander, Shlomo Weiss	Checkpoint allocation and release.	ACM Trans. Archit. Code Optim.	2009	DBLP DOI BibTeX RDF	early register release, misprediction, Checkpoint, leakage, out-of-order execution, rollback
22	Amit Golander, Shlomo Weiss	Hiding the misprediction penalty of a resource-efficient high-performance processor.	ACM Trans. Archit. Code Optim.	2008	DBLP DOI BibTeX RDF	misprediction, Checkpoints, out-of-order execution, scalable architecture, rollback
22	Gregorio Quintana-Ortí, Enrique S. Quintana-Ortí, Ernie Chan, Robert A. van de Geijn, Field G. Van Zee	Scheduling of QR Factorization Algorithms on SMP and Multi-Core Architectures.	PDP	2008	DBLP DOI BibTeX RDF	linear algebra libraries, high-performance, dynamic scheduling, out-of-order execution, QR factorization
22	Gregorio Quintana-Ortí, Enrique S. Quintana-Ortí, Alfredo Remón, Robert A. van de Geijn	An Algorithm-by-Blocks for SuperMatrix Band Cholesky Factorization.	VECPAR	2008	DBLP DOI BibTeX RDF	linear algebra libraries, high-performance, dynamic scheduling, out-of-order execution, Cholesky factorization, band matrices
22	Ernie Chan, Field G. Van Zee, Paolo Bientinesi, Enrique S. Quintana-Ortí, Gregorio Quintana-Ortí, Robert A. van de Geijn	SuperMatrix: a multithreaded runtime scheduling system for algorithms-by-blocks.	PPoPP	2008	DBLP DOI BibTeX RDF	algorithms-by-blocks, dynamic scheduling, dependency analysis, out-of-order execution
22	Kyu-Han Kim, Kang G. Shin	PRISM: Improving the Performance of Inverse-Multiplexed TCP in Wireless Networks.	IEEE Trans. Mob. Comput.	2007	DBLP DOI BibTeX RDF	Mobile collaborative community, out-of-order packet delivery, TCP, multi-homing, bandwidth aggregation
22	Shigeru Watanabe, Kenshu Seto, Yuji Ishikawa, Satoshi Komatsu, Masahiro Fujita	Protocol Transducer Synthesis using Divide and Conquer approach.	ASP-DAC	2007	DBLP DOI BibTeX RDF	out-of-order transactions, large scale system on a chip, IP-based design, automatic protocol transducer synthesis, nonblocking transactions, design methodologies, communication protocols, protocol conversion, divide and conquer approach
22	Jose Renau, Karin Strauss, Luis Ceze, Wei Liu 0014, Smruti R. Sarangi, James Tuck 0001, Josep Torrellas	Energy-Efficient Thread-Level Speculation.	IEEE Micro	2006	DBLP DOI BibTeX RDF	out-of-order task spawning, chip multiprocessors, Thread-level speculation
22	Oleg Bessonov, Dominique Fougère, Bernard Roux	Analysis of Architecture and Design of Linear Algebra Kernels for Superscalar Processors.	PaCT	2003	DBLP DOI BibTeX RDF	linear algebra kernels, LINPACK benchmark, performance measurements, instruction level parallelism, cache memories, microarchitecture, out-of-order processors
22	Marco Antonio Ramírez, Adrián Cristal, Alexander V. Veidenbaum, Luis Villa, Mateo Valero	A Simple Low-Energy Instruction Wakeup Mechanism.	ISHPC	2003	DBLP DOI BibTeX RDF	Instruction wake up, Low power, Superscalar processors, Out of order execution, CAM, Instruction window
22	Andreas Moshovos	Checkpointing alternatives for high performance, power-aware processors.	ISLPED	2003	DBLP DOI BibTeX RDF	checkpointing, power-aware, out-of-order execution, renaming, power density
22	Kevin Skadron, Pritpal S. Ahuja, Margaret Martonosi, Douglas W. Clark	Branch Prediction, Instruction-Window Size, and Cache Size: Performance Trade-Offs and Simulation Techniques.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	instruction window size, register-update unit, simulation, cache, sampling, branch prediction, Microarchitecture, trade-offs, out-of-order execution
22	Rad Silvera, Jian Wang, Ramaswamy Govindarajan, Guang R. Gao	A Register Pressure Sensitive Instruction Scheduler for Dynamic Issue Processors.	IEEE PACT	1997	DBLP DOI BibTeX RDF	Scheduling, register renaming, out-of-order issue, Register Pressure
22	Graham P. Jones, Nigel P. Topham	A Comparison of Data Prefetching on an Access Decoupled and Superscalar Machine.	MICRO	1997	DBLP DOI BibTeX RDF	Access Decoupling, Superscalar, out of order execution, latency hiding
22	Dileep Bhandarkar, Jianxun Jason Ding	Performance Characterization of the Pentium(r) Pro Processor.	HPCA	1997	DBLP DOI BibTeX RDF	Pentium® Pro processor, SPEC CPU95, SYSmark/NT, performance evaluation, computer architecture, workload characterization, speculative execution, out of order execution
22	Mayan Moudgill, Stamatis Vassiliadis	Precise Interrupts.	IEEE Micro	1996	DBLP DOI BibTeX RDF	interrupt handlers, out-of-order issue processors, instruction level parallel processors, pipelining, exceptions, superscalar processors, traps, precise interrupts
22	Manu Gulati, Nader Bagherzadeh	Performance Study of a Multithreaded Superscalar Microprocessor.	HPCA	1996	DBLP DOI BibTeX RDF	multithreading, instruction-level parallelism, Superscalars, out-of-order execution
22	Steven Wallace, Nirav Dagli, Nader Bagherzadeh	Design and implementation of a 100 MHz centralized instruction window for a superscalar microprocessor.	ICCD	1995	DBLP DOI BibTeX RDF	centralized instruction window, four instructions per cycle, compact layout, full-custom design, computer architecture, microprocessor chips, superscalar architecture, superscalar microprocessor, out-of-order issue, 100 MHz
22	William F. Richardson, Erik Brunvand	Precise exception handling for a self-timed processor.	ICCD	1995	DBLP DOI BibTeX RDF	precise exception handling, self-timed processor, multiple concurrent processes, self-timed queues, decoupled computer architectures, micropipelined processor, Fred, pipelined computer architecture, out-of-order instruction completion, parallel architectures, exception handling, instruction level parallelism, self-adjusting systems, self-timed systems
21	Rafael Ubal, Julio Sahuquillo, Salvador Petit, Pedro López 0001, José Duato	The impact of out-of-order commit in coarse-grain, fine-grain and simultaneous multithreaded architectures.	IPDPS	2008	DBLP DOI BibTeX RDF
20	Ming Li 0008, Mo Liu 0001, Luping Ding, Elke A. Rundensteiner, Murali Mani	Event Stream Processing with Out-of-Order Data Arrival.	ICDCS Workshops	2007	DBLP DOI BibTeX RDF
20	Takashi Takenaka, Junji Kitamichi, Teruo Higashino, Kenichi Taniguchi	Formal Design Verification for Correctness of Pipelined Microprocessors with Out-of-order Instruction Execution.	ASP-DAC	1999	DBLP DOI BibTeX RDF
20	Sailesh Krishnamurthy, Michael J. Franklin, Jeffrey Davis, Daniel Farina, Pasha Golovko, Alan Li, Neil Thombre	Continuous analytics over discontinuous streams.	SIGMOD Conference	2010	DBLP DOI BibTeX RDF	streams, continuous queries, order, out-of-order
20	Georgios Keramidas, Vasileios Spiliopoulos, Stefanos Kaxiras	Interval-based models for run-time DVFS orchestration in superscalar processors.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	performance and power modeling, superscalar out-of-order processors, dynamic voltage and frequency scaling
20	Gregorio Quintana-Ortí, Francisco D. Igual, Enrique S. Quintana-Ortí, Robert A. van de Geijn	Solving dense linear systems on platforms with multiple hardware accelerators.	PPoPP	2009	DBLP DOI BibTeX RDF	algorithms-by-blocks, depencency analysis, dynamic scheduling, out-of-order execution, gpus
20	Marco Antonio Ramírez, Adrián Cristal, Mateo Valero, Alexander V. Veidenbaum, Luis Villa	A New Pointer-based Instruction Queue Design and Its Power-Performance Evaluation.	ICCD	2005	DBLP DOI BibTeX RDF	Instruction Wakeup, Low Power, CAM, Issue Queue, Out-of-Order Processors
20	Allon Adir, Hagit Attiya, Gil Shurek	Information-Flow Models for Shared Memory with an Application to the PowerPC Architecture.	IEEE Trans. Parallel Distributed Syst.	2003	DBLP DOI BibTeX RDF	PowerPC architecture, synchronization instructions, models, specification, consistency, Shared memory, multiprocessor systems, out-of-order execution
20	Nam Sung Kim, Trevor N. Mudge	Reducing register ports using delayed write-back queues and operand pre-fetch.	ICS	2003	DBLP DOI BibTeX RDF	write queue, low power, instruction level parallelism, register file, out-of-order processor
20	Nam Sung Kim, Trevor N. Mudge	The microarchitecture of a low power register file.	ISLPED	2003	DBLP DOI BibTeX RDF	write queue, low power, instruction level parallelism, register file, out-of-order processor
20	Huamin Chen, Prasant Mohapatra	CATP: A Context-Aware Transportation Protocol for HTTP.	ICDCS Workshops	2003	DBLP DOI BibTeX RDF	out-of-order rendering, Transportation protocol, HTTP, UDP, head-of-line blocking
20	Sébastien Nussbaum, James E. Smith 0001	Statistical Simulation of Symmetric Multiprocessor Systems.	Annual Simulation Symposium	2002	DBLP DOI BibTeX RDF	SimpleMP, Simulation, Performance, Architecture, multiprocessor, Statistical, Memory Hierarchy, systems, SMP, superscalar, Fast, shared bus, out-of-order
20	Eric Schnarr, Mark D. Hill, James R. Larus	Facile: A Language and Compiler for High-Performance Processor Simulators.	PLDI	2001	DBLP DOI BibTeX RDF	micro-architecture simulation, out-of-order processor simulation, partial evaluation, memoization
20	Ramon Canal, Antonio González 0001	Reducing the complexity of the issue logic.	ICS	2001	DBLP DOI BibTeX RDF	complexity-effective design, instruction issue logic, wide-issue superscalar, out-of-order issue
20	Jiannong Cao 0001, Y. Liu, Li Xie 0001, Kang Zhang 0001	Portable Runtime Support for Graph-oriented Parallel and Distributed Programming.	ISPAN	2000	DBLP DOI BibTeX RDF	dynamic speculation of data dependence, instruction reissue, register update unit, Instruction level parallelism, out-of-order execution
20	Thomas Lundqvist, Per Stenström	Timing Anomalies in Dynamically Scheduled Microprocessors.	RTSS	1999	DBLP DOI BibTeX RDF	timing anomaly, Real-time systems, resource allocation, timing analysis, worst-case execution time, out-of-order execution, dynamically scheduled processor
20	Toshinori Sato	Data Dependence Speculation Using Data Address Prediction and its Enhancement with Instruction Reissue.	EUROMICRO	1998	DBLP DOI BibTeX RDF	dynamic speculation of data dependence, instruction reissue, instruction level parallelism, out-of-order execution, address prediction
20	Mateo Valero, Tomás Lang, Montse Peiron, Eduard Ayguadé	Conflict-Free Access for Streams in Multimodule Memories.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF	decoupled access, multimodule memories, out-of-order access, streams with constant strides, vector processors, Conflict-free access, storage schemes
20	Eric Hao, Po-Yung Chang, Yale N. Patt	The effect of speculatively updating branch history on branch prediction accuracy, revisited.	MICRO	1994	DBLP DOI BibTeX RDF	two-level adaptive branch prediction, speculative execution, superscalar processors, out-of-order execution, dynamic branch prediction
20	Eric Sprangle, Yale N. Patt	Facilitating superscalar processing via a combined static/dynamic register renaming scheme.	MICRO	1994	DBLP DOI BibTeX RDF	superscalar processors, out-of-order execution, register renaming, predicated execution
20	B. Ramakrishna Rau	Dynamically scheduled VLIW processors.	MICRO	1993	DBLP DOI BibTeX RDF	multiple operation issue, scoreboarding, dynamic scheduling, out-of-order execution, VLIW processors
20	Mateo Valero, Tomás Lang, Eduard Ayguadé	Conflict-free access of vectors with power-of-two strides.	ICS	1992	DBLP DOI BibTeX RDF	multi-module memories, out-of-order access, power-of-two strides, vector processors, conflict-free access, storage schemes
19	Perry H. Wang, Hong Wang 0003, Jamison D. Collins, Ed Grochowski, Ralph-Michael Kling, John Paul Shen	Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs. Speculative Precomputation.	HPCA	2002	DBLP DOI BibTeX RDF
19	Weihaw Chuang, Brad Calder	Predicate prediction for efficient out-of-order execution.	ICS	2003	DBLP DOI BibTeX RDF	predicate prediction, predicated execution
18	Yu Bai 0001, R. Iris Bahar	A low-power in-order/out-of-order issue queue.	ACM Trans. Archit. Code Optim.	2004	DBLP DOI BibTeX RDF	instruction issue logic, low power, High-performance
18	Yu Bai 0001, R. Iris Bahar	A Dynamically Reconfigurable Mixed In-Order/Out-of-Order Issue Queue for Power-Aware Microprocessors.	ISVLSI	2003	DBLP DOI BibTeX RDF
18	Cheol-Ho Jeong, Woo-Chan Park, Tack-Don Han, Moon Key Lee, Sang-Woo Kim	In-Order Issue Out-of-Order Execution Floating-Point Coprocessor for CalmRISC32.	IEEE Symposium on Computer Arithmetic	2001	DBLP DOI BibTeX RDF
18	Miroslav N. Velev	Using Rewriting Rules and Positive Equality to Formally Verify Wide-Issue Out-of-Order Microprocessors with a Reorder Buffer.	DATE	2002	DBLP DOI BibTeX RDF
17	Alok Garg, Fernando Castro, Michael C. Huang 0001, Daniel Chaver, Luis Piñuel, Manuel Prieto 0001	Substituting associative load queue with simple hash tables in out-of-order microprocessors.	ISLPED	2006	DBLP DOI BibTeX RDF	LSQ, scalability, hash table, memory disambiguation
17	Christian Jacobi 0002	Formal Verification of Complex Out-of-Order Pipelines by Combining Model-Checking and Theorem-Proving.	CAV	2002	DBLP DOI BibTeX RDF
17	Shuvendu K. Lahiri, Sanjit A. Seshia, Randal E. Bryant	Modeling and Verification of Out-of-Order Microprocessors in UCLID.	FMCAD	2002	DBLP DOI BibTeX RDF
17	Daniel Tate, Gordon B. Steven, Fleur L. Steven	Static Scheduling for Out-of-order Instruction Issue Processors.	ACAC	2000	DBLP DOI BibTeX RDF
17	Parthasarathy Ranganathan, Kourosh Gharachorloo, Sarita V. Adve, Luiz André Barroso	Performance of Database Workloads on Shared-Memory Systems with Out-of-Order Processors.	ASPLOS	1998	DBLP DOI BibTeX RDF
17	Stéphan Jourdan, Pascal Sainrat, Daniel Litaize	Exploring Configurations of Functional Units in an Out-of-Order Superscalar Processor.	ISCA	1995	DBLP DOI BibTeX RDF
17	Eduardo Quiñones, Joan-Manuel Parcerisa, Antonio González 0001	Early Register Release for Out-of-Order Processors with RegisterWindows.	PACT	2007	DBLP DOI BibTeX RDF
17	Eduardo Quiñones, Joan-Manuel Parcerisa, Antonio González 0001	Improving Branch Prediction and Predicated Execution in Out-of-Order Processors.	HPCA	2007	DBLP DOI BibTeX RDF
17	Joseph J. Sharkey, Dmitry Ponomarev 0001	Balancing ILP and TLP in SMT Architectures through Out-of-Order Instruction Dispatch.	ICPP	2006	DBLP DOI BibTeX RDF
17	Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt	An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-Order and Runahead Execution Processors.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	processor performance modeling, speculative execution, runahead execution, Single data stream architectures
17	Adrián Cristal, José F. Martínez, Josep Llosa, Mateo Valero	A case for resource-conscious out-of-order processors: towards kilo-instruction in-flight processors.	SIGARCH Comput. Archit. News	2004	DBLP DOI BibTeX RDF
17	Xianfeng Li, Abhik Roychoudhury, Tulika Mitra	Modeling Out-of-Order Processors for Software Timing Analysis.	RTSS	2004	DBLP DOI BibTeX RDF