|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 6 occurrences of 6 keywords
|
|
|
Results
Found 1 publication records. Showing 1 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
290 | Varna Puvvada, S. Potla, S. Tamizh Selvam, P. R. Suresh |
A simulation study on the effectiveness of n-guardring/p-guardring on latchup in 0.8 μm CMOS technology. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
integrated circuit technology, n-guardring, p-guardring, latchup prevention, remote transient, I/O buffer n-channel transistor, 2D device simulator, TMA-MEDICI, substrate resistance, 0.8 micron, VLSI, circuit analysis computing, CMOS integrated circuits, CMOS technology, transients, steady state simulation |
Displaying result #1 - #1 of 1 (100 per page; Change: )
|
|