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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 383 occurrences of 273 keywords
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Results
Found 489 publication records. Showing 489 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
171 | John L. Gustafson |
Reevaluating Amdahl's Law. |
Commun. ACM |
1988 |
DBLP DOI BibTeX RDF |
|
54 | Len Dekker, Edward E. E. Frietman |
Optical link and processor clustering in the Delft parallel processor. |
ICS |
1988 |
DBLP DOI BibTeX RDF |
|
36 | Andreas Svolos, Charalampos Konstantopoulos, Christos Kaklamanis |
A Parallel Solution in Texture Analysis Employing a Massively Parallel Processor (Research Note). |
Euro-Par |
2002 |
DBLP DOI BibTeX RDF |
hypercube, texture analysis, co-occurrence matrix, massively parallel processor |
31 | Alexey Kupriyanov, Dmitrij Kissler, Frank Hannig, Jürgen Teich |
Efficient event-driven simulation of parallel processor architectures. |
SCOPES |
2007 |
DBLP DOI BibTeX RDF |
embedded tools, simulation, modeling, processor arrays |
31 | Jack L. Rosenfeld |
A case study in programming for parallel-processors. |
Commun. ACM |
1969 |
DBLP DOI BibTeX RDF |
Gauss-Seidel, Jacobi, storage interference, simulation, parallel programming, parallelism, multiprocessor, convergence, tasking, multiprogramming, relaxation, parallel-processor, electrical network |
30 | Dirk Fimmel, Renate Merker |
Propagation of I/O-Variables in Massively Parallel Processor Arrays. |
PDP |
1996 |
DBLP DOI BibTeX RDF |
parallel processor arrays, systems of recurrence equations, automatic design methods, massive parallelism |
29 | Lorenz A. Schmitt, Stephen S. Wilson |
The AIS-5000 Parallel Processor. |
IEEE Trans. Pattern Anal. Mach. Intell. |
1988 |
DBLP DOI BibTeX RDF |
AIS-5000, parallel memory organization, image-based algorithms, computer vision, computer vision, parallel architecture, parallel architectures, computerised picture processing, computerised picture processing, microprocessor chips, parallel processor, SIMD architecture |
28 | Xingzhi Wen, Uzi Vishkin |
Fpga-based prototype of a pram-on-chip processor. |
Conf. Computing Frontiers |
2008 |
DBLP DOI BibTeX RDF |
ease-of-programming, explicit multi-threading, on-chip parallel processor, pram, parallel algorithms, xmt |
27 | Shorin Kyo, Takuya Koga, Hanno Lieske, Shouhei Nomoto, Shin'ichiro Okazaki |
A low-cost mixed-mode parallel processor architecture for embedded systems. |
ICS |
2007 |
DBLP DOI BibTeX RDF |
embedded systems, parallel architectures, SIMD, MIMD, multimedia processing, tile architectures, mixed-mode |
26 | Ahmed Louri |
An Optical Content-Adressable Parallel Processor for Fast Searching and Retrieving. |
PARLE (1) |
1991 |
DBLP DOI BibTeX RDF |
|
25 | Falk D. Kübler, Friedrich Lücking |
Cluster oriented architecture for the mapping of parallel processor networks to high performance applications. |
ICS |
1988 |
DBLP DOI BibTeX RDF |
|
24 | M. R. Brown, S. DasGupta |
Design of a general purpose meta-assembler for parallel processor environment in ISPS. |
Annual Simulation Symposium |
1989 |
DBLP DOI BibTeX RDF |
ISPS |
24 | Ken'ichirou Kimura, Hirofumi Amano, Akifumi Makinouchi |
Dynamic Performance Optimization Mechanism for Parallel Object-Oriented Database Programming Languages. |
IDEAS |
2000 |
DBLP DOI BibTeX RDF |
dynamic performance optimization, parallel object-oriented database programming languages, distributed-memory parallel processor, remote object referencing, biased distribution, object relocation, simulation tests, topology, parallel languages, performance degradation, inter-processor communication, load imbalance, object allocation |
23 | Andreas Svolos, Charalampos Konstantopoulos, Christos Kaklamanis |
fficient Binary Morphological Algorithms on a Massively Parallel Processor. |
IPDPS |
2000 |
DBLP DOI BibTeX RDF |
hypercube, mathematical morphology, dilation, massively parallel processor, erosion, associative processor |
23 | Rainer Hauser, Reinhard Männer, Mikhail Makhaniok |
NERV: a parallel processor for standard genetic algorithms. |
IPPS |
1995 |
DBLP DOI BibTeX RDF |
standard genetic algorithms, MIMD multiprocessor system, NERV hardware, NERV multiprocessor, genetic algorithms, parallel algorithms, parallel architectures, parallel machines, GA, parallel processor, parallel genetic algorithms |
23 | Giuseppe Ascia, Vincenzo Catania |
Design of a VLSI parallel processor for fuzzy computing. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
VLSI parallel processor, fuzzy computing, /spl alpha/-level sets theory, memory resources, processing units, 50 MHz, scalability, VLSI, parallelism, fuzzy logic, parallel architectures, inference mechanisms, fuzzy set theory, integrated circuit design, microprocessor chips, membership functions, fuzzy inferences, clock frequency, 8 bit |
23 | Albert Y. Zomaya, Matthew Clements, Stephan Olariu |
A Framework for Reinforcement-Based Scheduling in Parallel Processor Systems. |
IEEE Trans. Parallel Distributed Syst. |
1998 |
DBLP DOI BibTeX RDF |
scheduling, Neural networks, parallel processing, reinforcement learning, randomization, task allocation |
22 | Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Julien Lallet, Olivier Sentieys, Sébastien Pillement |
Modeling of Interconnection Networks in Massively Parallel Processor Architectures. |
ARCS |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Krishna Kumar Rangan, Philip A. Wilsey, Nilesh Pisolkar, Nael B. Abu-Ghazaleh |
PPIM-SIM: An Efficient Simulator for a Parallel Processor in Memory. |
Annual Simulation Symposium |
2001 |
DBLP DOI BibTeX RDF |
|
22 | James A. Lupo |
Benchmarking UHGROMOS. |
HICSS (5) |
1995 |
DBLP DOI BibTeX RDF |
GROMOS, parallel Fortran preprocessor, Pfortran, Intel Corporation, IBM Corporation, massively parallel processor machines, Intel iPSC/860, Caltech Intel DELTA, IBM SP1, UHGROMOS molecular dynamics program, test application, parallel performance analysis, parallel programming, benchmarking, FORTRAN, parallel machines, parallel machines, software performance evaluation, physics, parallel languages, software portability, physics computing, porting, Intel Paragon, program processors, molecular dynamics method |
21 | Andrea Di Blas, David M. Dahle, Mark Diekhans, Leslie Grate, Jeffrey D. Hirschberg, Kevin Karplus, Hansjörg Keller, Mark Kendrick, Francisco J. Mesa-Martinez, David Pease, Eric Rice, Angela Schultz, Don Speck, Richard Hughey |
The UCSC Kestrel Parallel Processor. |
IEEE Trans. Parallel Distributed Syst. |
2005 |
DBLP DOI BibTeX RDF |
VLSI system design, image processing, Parallel processing, high performance computing, computer architecture, systolic array, SIMD, DNA, computational chemistry, biological sequence analysis |
21 | Thomas Schmitt 0002, Dirk Fimmel, Mathias Kortke, Renate Merker |
Parallel Processor Array for Tomographic Reconstruction Algorithms. |
EUROCAST |
1999 |
DBLP DOI BibTeX RDF |
|
21 | Tomoo Fukazawa, Takashi Kimura, Masaaki Tomizawa, Kazumitsu Takeda, Yoshitaka Itoh |
R256: A Research Parallel Processor for Scientific Computation. |
ISCA |
1989 |
DBLP DOI BibTeX RDF |
|
21 | James D. Feldman, Louis C. Fulmer |
RADCAP: an operational parallel processing facility. |
AFIPS National Computer Conference |
1974 |
DBLP DOI BibTeX RDF |
|
21 | Dimitris Syrivelis, Spyros Lalis |
Extracting Coarse-Grained Pipelined Parallelism Out of Sequential Applications for Parallel Processor Arrays. |
ARCS |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Edward W. Davis |
Application of the massively parallel processor to database management systems. |
AFIPS National Computer Conference |
1983 |
DBLP DOI BibTeX RDF |
|
20 | Richard Hughey, Andrea Di Blas |
Finding the Next Computational Model: Experience with the UCSC Kestrel. |
J. Signal Process. Syst. |
2008 |
DBLP DOI BibTeX RDF |
biological sequence comparison, VLSI system design, application-specific array processor, parallel processing, parallel programming, computer architecture, systolic array, SIMD, sequence analysis, shared registers |
20 | Ian Buck |
GPU Computing: Programming a Massively Parallel Processor. |
CGO |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Sonny Tham, John Morris |
Performance of the Achilles Router. |
Asia-Pacific Computer Systems Architecture Conference |
2003 |
DBLP DOI BibTeX RDF |
Parallel processor interconnection, cross-bar switching, networks of workstations |
19 | Kazutoshi Kobayashi, Masao Aramoto, Yoichi Yuyama, Akihiko Higuchi, Hidetoshi Onodera |
A resource-shared VLIW processor architecture for area-efficient on-chip multiprocessing. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Albert Y. Zomaya, Matthew Clements, Stephan Olariu |
Randomized Reinforcement Based Scheduling In Parallel Processor Systems. |
HICSS (1) |
1997 |
DBLP DOI BibTeX RDF |
|
19 | Arindam Saha |
A simulator for real-time parallel processing architectures. |
Annual Simulation Symposium |
1995 |
DBLP DOI BibTeX RDF |
real-time parallel processing architectures, time-driven flit-based wormhole-routed parallel processor network simulator, user-friendly graphical user interface, prioritized queues, resource allocation policies, message priorities, average latency convergence, throughput monitoring, communication characteristics, performance, real-time systems, resource allocation, parallel architectures, graphical user interfaces, virtual machines, concurrency control, convergence, deadlocks, virtual channel, overlaps, real-time networks |
18 | Benoît Dupont de Dinechin |
Kalray MPPA®: Massively parallel processor array: Revisiting DSP acceleration with the Kalray MPPA Manycore processor. |
Hot Chips Symposium |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Murali Krishnamurthi, Robert E. Young |
A multitasking implementation of system simulation: The emulation of an asynchronous parallel processor for system simulation using a single processor. |
WSC |
1984 |
DBLP BibTeX RDF |
|
18 | Zhe Liu 0005, JeoungChill Shim, Hiroyuki Kurino, Mitsumasa Koyanagi |
Design of A Novel Real-Shared Memory Module for High Performance Parallel Processor System with Shared Memory. |
AINA (2) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | David C. Wong 0002, Edward W. Davis, Jeffrey O. Young |
A Software Approach to Avoiding Spatial Cache Collisions in Parallel Processor Systems. |
IEEE Trans. Parallel Distributed Syst. |
1998 |
DBLP DOI BibTeX RDF |
Cache collision, cache offset, highly parallel systems, sequential DO-loops, direct-mapped cache |
18 | Su-Hui Chiang, Rajesh K. Mansharamani, Mary K. Vernon |
Use of Application Characteristics and Limited Preemption for Run-to-Completion Parallel Processor Scheduling Policies. |
SIGMETRICS |
1994 |
DBLP DOI BibTeX RDF |
|
18 | Richard L. Shoemaker, Harrison H. Barrett, R. H. Seacat III |
TRIMM: A Parallel Processor for Image Reconstruction by Simulated Annealing. |
PPSN |
1990 |
DBLP DOI BibTeX RDF |
|
18 | Gary J. Nutt |
A parallel processor for evaluation studies. |
AFIPS National Computer Conference |
1976 |
DBLP DOI BibTeX RDF |
|
17 | Jeffrey C. Gealow, Frederick P. Herrmann, L. T. Hsu, Charles G. Sodini |
System design for pixel-parallel image processing. |
IEEE Trans. Very Large Scale Integr. Syst. |
1996 |
DBLP DOI BibTeX RDF |
|
17 | Fong-Chih Shao, A. Yavuz Oruç |
Efficient Nonblocking Switching Networks for Interprocessor Communications in Multiprocessor Systems. |
IEEE Trans. Parallel Distributed Syst. |
1995 |
DBLP DOI BibTeX RDF |
|
17 | Taisuke Boku, Masayuki Umemura, Junichiro Makino, Toshiyuki Fukushige, Hajime Susa, Akira Ukawa |
Heterogeneous multi-computer system: a new platform for multi-paradigm scientific simulation. |
ICS |
2002 |
DBLP DOI BibTeX RDF |
CP-PACS, GRAPE, heterogeneous computing |
17 | David B. Thomas, Lee W. Howes, Wayne Luk |
A comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation. |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
mppa, fpga, monte-carlo, random numbers, gpu |
17 | Albert Y. Zomaya, Chris Ward, Benjamin S. Macey |
Genetic Scheduling for Parallel Processor Systems: Comparative Studies and Performance Issues. |
IEEE Trans. Parallel Distributed Syst. |
1999 |
DBLP DOI BibTeX RDF |
Genetic algorithms, scheduling, parallel processing, heuristics, randomization |
17 | Albert Y. Zomaya, Chris Ward, Benjamin S. Macey |
An Evolutionary Approach for Scheduling in Parallel Processor Systems. |
ISPAN |
1997 |
DBLP DOI BibTeX RDF |
Genetic algorithms, scheduling, load balancing, parallel processing |
17 | Hercule Kwan, Edward J. Powers, Earl E. Swartzlander Jr. |
Realization of a nonlinear digital filter on a DSP array processor. |
ASAP |
1997 |
DBLP DOI BibTeX RDF |
nonlinear digital filter, third-order Volterra digital filtering algorithm, AT&T DSP-3 parallel processor, nonlinear communication channel equalization, 64-QAM signal constellation, performance evaluation, digital signal processing chips, time-skewing |
17 | Eric A. Brewer, Paul Gauthier, Armando Fox, Angela Schuett |
Software Techniques for Improving MPP Bulk-Transfer Performance. |
IPPS |
1996 |
DBLP DOI BibTeX RDF |
software techniques, bulk-transfer performance, traffic interleaving, Thinking Machines CM-5, one-on-one communication, MIT Alewife machine, token-passing scheme, distributed dynamic scheduling, irregular traffic patterns, traffic massaging, near-permutations, performance evaluation, parallel machines, processor scheduling, software performance evaluation, telecommunication traffic, preprocessing, barriers, network congestion, algorithm performance, Intel Paragon, static scheduling, massively parallel processor, global state |
17 | Mun Choon Chan, Giovanni Pacifici, Rolf Stadler |
Prototyping Network Architectures on a Supercomputer. |
HPDC |
1996 |
DBLP DOI BibTeX RDF |
network architecture prototyping, dynamic behavior evaluation, overall performance evaluation, functional properties, interactive emulation platform, multimedia network services, load patterns, network management operations, KSR-1, SP2 parallel processor, graphics workstation, ATM links, performance evaluation, real-time systems, parallel programming, interactive systems, multimedia communication, data visualisation, supercomputer, software prototyping, software prototype, network operating systems, telecommunication computing, network control systems, engineering graphics, telecommunication network management, telecommunication control, real-time visualization, network sizes, dynamic properties, control system CAD |
17 | Dejan S. Milojicic, David L. Black 0001, Steven J. Sears |
Operating system support for concurrent remote task creation. |
IPPS |
1995 |
DBLP DOI BibTeX RDF |
concurrent remote task creation, application startup, multiple nodes, remote task creation, multiple remote tasks, distributed virtual memory, paging path, operating systems, distributed memory systems, operating system kernels, virtual storage, massively parallel processor, Mach |
17 | Ranga S. Ramanujan, Jordan Bonney, Kenneth J. Thurber |
Network Shared Memory: A New Approach for Clustering Workstations for Parallel Processing. |
HPDC |
1995 |
DBLP DOI BibTeX RDF |
network shared memory, clustering workstations, shared memory parallel processor, performance evaluation, performance evaluation, parallel processing, parallel processing, shared memory systems, implementation model |
17 | Minsu Choi, Nohpill Park, Fabrizio Lombardi |
Hardware-Software Co-Reliability in Field Reconfigurable Multi-Processor-Memory Systems. |
IPDPS |
2002 |
DBLP DOI BibTeX RDF |
Multi-Processor-Memory System, Field Reconfiguration, HW/SW Co-reliability, Modular Redundancy |
17 | Konstantina Karagianni, Vassilis Paliouras, George Diamantakos, Thanos Stouraitis |
Operation-Saving VLSI Architectures for 3D Geometrical Transformations. |
IEEE Trans. Computers |
2001 |
DBLP DOI BibTeX RDF |
Elementary geometrical transformations, vector unit, VLSI architecture, graphics processor |
17 | Henk Corporaal, J. G. E. Olk |
A Scalable Communication Processor Design supporting Systolic Communication. |
EDMCC |
1991 |
DBLP DOI BibTeX RDF |
high performance communication processor, fine-grain communication, scalability of design, message compression, routing, virtual connections |
17 | Arun Kejariwal, Alexandru Nicolau |
An Efficient Load Balancing Scheme for Grid-based High Performance Scientific Computing. |
ISPDC |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Sumit Ghosh, Meng-Lin Yu |
An Asynchronous Distributed Approach for the Simulation of Behavior-Level Models on Parallel Processors. |
IEEE Trans. Parallel Distributed Syst. |
1995 |
DBLP DOI BibTeX RDF |
|
15 | Arjuna Madanayake, Leonard T. Bruton |
A high performance distributed-parallel-processor architecture for 3D IIR digital filters. |
ISCAS (2) |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Stephanie McBader, Luca Clementel, Alvise Sartori, Andrea Boni, Peter Lee 0002 |
SoftTOTEM: An FPGA Implementation of the TOTEM Parallel Processor. |
FPL |
2002 |
DBLP DOI BibTeX RDF |
|
15 | Saravut Charcranoon, Thomas G. Robertazzi, Serge Luryi |
Parallel Processor Configuration Design with Processing/Transmission Costs. |
IEEE Trans. Computers |
2000 |
DBLP DOI BibTeX RDF |
single-level tree network, local search, economics, Cost, heuristic algorithm, divisible load, star network |
15 | Renate Merker, Ulrich Eckhardt, Dirk Fimmel, H. Schreiber |
A System for Designing Parallel Processor Arrays. |
EUROCAST |
1997 |
DBLP DOI BibTeX RDF |
|
15 | A. L. Kimball, Raimond L. Winslow |
Modeling the retinal horizontal cell layer on a massively parallel processor: a detailed neural network model. |
SPDP |
1990 |
DBLP DOI BibTeX RDF |
|
15 | Kazuaki J. Murakami, Shin-ichiro Mori, Akira Fukuda, Toshinori Sueyoshi, Shinji Tomita |
The Kyushu University reconfigurable parallel processor: design of memory and intercommunicaiton architectures. |
ICS |
1989 |
DBLP DOI BibTeX RDF |
|
15 | Claus Traulsen, Reinhard von Hanxleden |
Reactive parallel processing for synchronous dataflow. |
SAC |
2010 |
DBLP DOI BibTeX RDF |
Scade, reactive processors, synchronous languages, parallel execution, synchronous dataflow, Lustre |
15 | Xiaoyong Wen, Faycal Bensaali, Reza Sotudeh |
Dynamic Co-operative Intelligent Memory. |
DELTA |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Masaitsu Nakajima, Takao Yamamoto, Masayuki Yamasaki, Tetsu Hosoki, Masaya Sumita |
Low Power Techniques for Mobile Application SoCs Based on Integrated Platform "UniPhier". |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Sam Sander, Linda M. Wills |
Retargeting Image-Processing Algorithms to Varying Processor Grain Sizes. |
ICPP Workshops |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Lewis Benton Baumstark Jr., Linda M. Wills |
Retargeting Sequential Image-Processing Programs for Data Parallel Execution. |
IEEE Trans. Software Eng. |
2005 |
DBLP DOI BibTeX RDF |
explicitly parallel program representation, program recognition, Reengineering, SIMD processors, data-level parallelization |
15 | Marshall C. Pease |
Matrix Inversion Using Parallel Processing. |
J. ACM |
1967 |
DBLP DOI BibTeX RDF |
|
15 | Daniel Madroñal, Raquel Lazcano, Himar Fabelo, Samuel Ortega, Gustavo Marrero Callicó, Eduardo Juárez 0001, César Sanz |
Hyperspectral image classification using a parallel implementation of the linear SVM on a Massively Parallel Processor Array (MPPA) platform. |
DASIP |
2016 |
DBLP DOI BibTeX RDF |
|
15 | Hideaki Ito, Masaru Shimizu, Saburou Iida |
Parallel Algorithms of Basic Image Processing Implemented on a Linearly Connected Parallel Processor - Gray-scale and Binary Images -. |
J. Next Gener. Inf. Technol. |
2011 |
DBLP DOI BibTeX RDF |
|
15 | Peng Yin Choo, Abram Detofsky, Ahmed Louri |
A Multi-Wavelength Optical Content-Addressable Parallel Processor (MW-OCAPP) for High-Speed Parallel Relational Database Processing: Architectural Concepts and Preliminary Experimental System. |
IPPS/SPDP Workshops |
1999 |
DBLP DOI BibTeX RDF |
|
15 | Jim Weston, Marek Szularz, Maurice Clint, Kieran Murphy |
The Parallel Computation of Partial Eigensolutions of Large Matrices on a Massively Parallel Processor. |
Euro-Par, Vol. II |
1996 |
DBLP DOI BibTeX RDF |
|
15 | Anthonie B. Ruighaver, R. F. Holt, J. Semkiw |
Pandora Networks for a Massively Parallel Decoupled Parallel Processor. |
EUROSIM |
1994 |
DBLP BibTeX RDF |
|
15 | C. S. Lin, A. L. Thring, J. Koga, E. J. Seiler |
A Parallel Particle-in-Cell Model for the Massively Parallel Processor. |
J. Parallel Distributed Comput. |
1990 |
DBLP DOI BibTeX RDF |
|
15 | Thomas J. LeBlanc, Michael L. Scott, Christopher M. Brown |
Large-Scale Parallel Programming: Experience with the BBN Butterfly Parallel Processor. |
PPOPP/PPEALS |
1988 |
DBLP DOI BibTeX RDF |
|
15 | Constantine D. Polychronopoulos, David J. Kuck, David A. Padua |
Execution of Parallel Loops on Parallel Processor Systems. |
ICPP |
1986 |
DBLP BibTeX RDF |
|
14 | Manoel T. F. Cunha, Jose C. F. Telles, Alvaro L. G. A. Coutinho |
On the Implementation of Boundary Element Engineering Codes on the Cell Broadband Engine. |
VECPAR |
2008 |
DBLP DOI BibTeX RDF |
Parallel Programming, SIMD, Vectorization, Cell Broadband Engine, Boundary Element Method, Boundary Elements |
14 | Rainer Schaffer, Renate Merker |
Parameterized Mapping of Algorithms onto Processor Arrays with Sub-Word Parallelism. |
ICSAMOS |
2006 |
DBLP DOI BibTeX RDF |
|
14 | O. Volberg, Jay Walter Larson, Robert L. Jacob, John Michalakes |
Registration and Resource Allocation Mechanisms in High-Performance Application Frameworks. |
CLUSTER |
2005 |
DBLP DOI BibTeX RDF |
|
14 | Taisuke Boku, Junichiro Makino, Hajime Susa, Masayuki Umemura, Toshiyuki Fukushige, Akira Ukawa |
Heterogeneous Multi-Computer System: A New Paradigm of Parallel Processing. |
PARELEC |
2002 |
DBLP DOI BibTeX RDF |
|
14 | Teruo Utsumi, Masayuki Ikeda, Moriyuki Takamura |
Architecture of the VPP500 parallel supercomputer. |
SC |
1994 |
DBLP DOI BibTeX RDF |
|
13 | Stefan Janson, Martin Middendorf |
Flexible Particle Swarm Optimization Tasks for Reconfigurable Processor Arrays. |
IPDPS |
2005 |
DBLP DOI BibTeX RDF |
|
13 | Richard P. Kleihorst, Mi-Suen Lee, Anteneh A. Abbo, Eric Cohen-Solal |
Real time skin-region detection with a single-chip digital camera. |
ICIP (3) |
2001 |
DBLP DOI BibTeX RDF |
|
13 | Seon Wook Kim, Rudolf Eigenmann |
Compiling for Speculative Architectures. |
LCPC |
1999 |
DBLP DOI BibTeX RDF |
|
13 | Kenneth E. Batcher |
MPP: a supersystem for satellite image processing. |
AFIPS National Computer Conference |
1982 |
DBLP DOI BibTeX RDF |
|
13 | Stanley Tzeng, Li-Yi Wei |
Parallel white noise generation on a GPU via cryptographic hash. |
SI3D |
2008 |
DBLP DOI BibTeX RDF |
GPU techniques, parallel computation, texturing, noise, random number generation |
13 | Chih Jeng Kenneth Tan, J. A. Rod Blais |
PLFG: A Highly Scalable Parallel Pseudo-random Number Generator for Monte Carlo Simulations. |
HPCN |
2000 |
DBLP DOI BibTeX RDF |
Lagged Fibonnaci Generator, Parallel computation, Monte Carlo method, Pseudo-random number generator, Randomized computation |
12 | Anna Nepomniaschaya |
Associative Version of the Ramalingam Decremental Algorithm for Dynamic Updating the Single-Sink Shortest-Paths Subgraph. |
PaCT |
2009 |
DBLP DOI BibTeX RDF |
Directed weighted graph, subgraph of the shortest paths, decremental algorithm, associative parallel processor, access data by contents, adjacency matrix |
12 | George C. Caragea, A. Beliz Saybasili, Xingzhi Wen, Uzi Vishkin |
Brief announcement: performance potential of an easy-to-program PRAM-on-chip prototype versus state-of-the-art processor. |
SPAA |
2009 |
DBLP DOI BibTeX RDF |
ease of programming, explicit multi-treading, on-chip parallel processor, paraleap, parallel algorithms, PRAM, xmt |
12 | Erik Lindholm, John Nickolls, Stuart F. Oberman, John Montrym |
NVIDIA Tesla: A Unified Graphics and Computing Architecture. |
IEEE Micro |
2008 |
DBLP DOI BibTeX RDF |
SIMT, unified graphics and parallel computing architecture, cooperative thread array, GPU, graphics processing unit, SIMD, parallel processor, Tesla, Hot Chips 19 |
12 | Wenjun Xiao, Behrooz Parhami |
A Group Construction Method with Applications to Deriving Pruned Interconnection Networks. |
IEEE Trans. Parallel Distributed Syst. |
2007 |
DBLP DOI BibTeX RDF |
geometric group theory, parallel processor architecture, pruning scheme, VLSI realization, distributed system, interconnection network, Cayley graph, network diameter, Algebraic structure |
12 | Xingzhi Wen, Uzi Vishkin |
PRAM-on-chip: first commitment to silicon. |
SPAA |
2007 |
DBLP DOI BibTeX RDF |
ease-of-programming, explicit multi-threading, on-chip parallel processor, parallel algorithms, PRAM, XMT |
12 | A. S. Nepomniaschaya, Zbigniew Kokosinski |
Associative Graph Processor and Its Properties. |
PARELEC |
2004 |
DBLP DOI BibTeX RDF |
associative parallel processor, bit-parallel processing, associative graph processing, multiple-search |
12 | Hyesook Lim, Vincenzo Piuri, Earl E. Swartzlander Jr. |
A Serial-Parallel Architecture for Two-Dimensional Discrete Cosine and Inverse Discrete Cosine Transforms. |
IEEE Trans. Computers |
2000 |
DBLP DOI BibTeX RDF |
Application specific processor architecture, Inverse Discrete Cosine Transform, serial-parallel processor, image compression, Discrete Cosine Transform, systolic array |
12 | A. S. Nepomniaschaya |
An Associative Parallel Algorithm for Finding a Critical Cycle in Directed Graphs. |
ICPADS |
2000 |
DBLP DOI BibTeX RDF |
Directed weighted graph, critical cycle, optimum branching, bit-serial processing, associative parallel processor, time complexity |
12 | Craig S. Freedman, Josef Burger, David J. DeWitt |
SPIFFI-A Scalable Parallel File System for the Intel Paragon. |
IEEE Trans. Parallel Distributed Syst. |
1996 |
DBLP DOI BibTeX RDF |
scalability, file system, high performance, Parallel I/O, massively parallel processor |
12 | Peggy Li, William H. Duquette, David W. Curkendall |
RIVA: A Versatile Parallel Rendering System for Interactive Scientific Visualization. |
IEEE Trans. Vis. Comput. Graph. |
1996 |
DBLP DOI BibTeX RDF |
Parallel terrain rendering, feed forward rendering, massively parallel processor (MPP), scientific visualization |
12 | Barry S. Fagin |
Fast Addition of Large Integers. |
IEEE Trans. Computers |
1992 |
DBLP DOI BibTeX RDF |
computation time asymmetry, large integers, massively parallel algorithms, average case behavior, large n-bit additions, multiple bits, parallel algorithms, computational model, digital arithmetic, massively parallel processor, binary addition, carry-lookahead |
12 | J. M. Herron, J. Farley, Kendall Preston Jr., H. Sellner |
A General-Purpose High-Speed Logical Transform Image Processor. |
IEEE Trans. Computers |
1982 |
DBLP DOI BibTeX RDF |
peripheral processor, image processor, neighborhood transform, parallel processor, Array processing, cellular logic |
12 | David C. van Voorhis, Thomas H. Morrin |
Memory Systems for Image Processing. |
IEEE Trans. Computers |
1978 |
DBLP DOI BibTeX RDF |
array storage, image processing, memory system, Array processor, parallel processor, parallel memory |
12 | Jeffrey L. DeVeber |
Letters to the editor: correction's to Stone's compiler procedures. |
Commun. ACM |
1968 |
DBLP DOI BibTeX RDF |
one-pass compilation, compilation, parallel processor |
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