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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 74 occurrences of 58 keywords
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Results
Found 8 publication records. Showing 8 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
26 | Bapiraju Vinnakota, Niraj K. Jha |
Design of Algorithm-Based Fault-Tolerant Multiprocessor Systems for Concurrent Error Detection and Fault Diagnosis. |
IEEE Trans. Parallel Distributed Syst. |
1994 |
DBLP DOI BibTeX RDF |
fault-tolerant multiprocessor systems, algorithm-basedmultiprocessor systems, algorithm-based faulttolerance, low-overhead system-level error detection, fault location scheme, ABFTsystems, design procedure, data element sharing, ABFT system design, reliability, fault diagnosis, fault tolerant computing, multiprocessing systems, fault location, system recovery, concurrent error detection, parallelarchitectures |
26 | George Karypis, Vipin Kumar 0001 |
Unstructured Tree Search on SIMD Parallel Computers. |
IEEE Trans. Parallel Distributed Syst. |
1994 |
DBLP DOI BibTeX RDF |
unstructured tree search, SIMD parallelcomputers, unstructured tree computations, large-scale SIMD machines, triggering mechanism, search spaceredistribution, load-balancing methods, load-balancing schemes, 15-puzzle problem, CM-2 SIMD parallel computer, performance evaluation, scalability, load balancing, resource allocation, parallel machines, trees (mathematics), search problems, tree search, SIMD machine, MIMD architectures, parallelarchitectures |
26 | Alok N. Choudhary, Janak H. Patel, Narendra Ahuja |
NETRA: A Hierarchical and Partitionable Architecture for Computer Vision Systems. |
IEEE Trans. Parallel Distributed Syst. |
1993 |
DBLP DOI BibTeX RDF |
NETRA, partitionable architecture, tree-type control hierarchy, broadcast capability, block-level control, memorymanagement, scheduling, performance, computer vision, computer vision, load balancing, topology, SIMD, data flow, MIMD, multiprocessor architecture, CVS, hierarchical architecture, parallelarchitectures, Systolic, flexible architecture |
26 | Bapiraju Vinnakota, Niraj K. Jha |
Synthesis of Algorithm-Based Fault-Tolerant Systems from Dependence Graphs. |
IEEE Trans. Parallel Distributed Syst. |
1993 |
DBLP DOI BibTeX RDF |
algorithm-based fault-tolerant systems, computation-intensive tasks, ABFT scheme, synthesis method, fault-tolerant median filter, reliability, graph theory, parallel architectures, fault tolerant computing, dependence graphs, parallelarchitectures |
26 | Dan I. Moldovan, Wing Lee, Changhwa Lin |
SNAP: A Market-Propagation Architecture for Knowledge Processing. |
IEEE Trans. Parallel Distributed Syst. |
1992 |
DBLP DOI BibTeX RDF |
knowledge storage, market-propagation architecture, semantic network array processor, artificialintelligence, custom-designedchips, reasoning mechanisms, marker propagation rules, 16 kB, knowledge representation, knowledge representation, parallel architecture, knowledge based systems, natural languages, knowledge base, natural language understanding, printed circuit boards, knowledge processing, SNAP, parallelarchitectures |
26 | Chita R. Das, Jong Kim 0001 |
A Unified Task-Based Dependability Model for Hypercube Computers. |
IEEE Trans. Parallel Distributed Syst. |
1992 |
DBLP DOI BibTeX RDF |
task-based dependability, subcube TBD, reliability, fault tolerant computing, dependability, hypercube, availability, hypercube networks, parallelarchitectures, hypercube architectures |
26 | Charles M. Fiduccia |
Bused Hypercubes and Other Pin-Optimal Networks. |
IEEE Trans. Parallel Distributed Syst. |
1992 |
DBLP DOI BibTeX RDF |
pin minimisation, simultaneous data exchange, pin-optimal networks, massively parallelarchitectures, chassis, bused hypercubeinterconnection network, clock tick, hypercube networks, processing elements, ports, chip, board |
26 | Krishnan Padmanabhan |
Design and Analysis of Even-Sized Binary Shuffle-Exchange Networks for Multiprocessors. |
IEEE Trans. Parallel Distributed Syst. |
1991 |
DBLP DOI BibTeX RDF |
control tags, traffic capacity, binary shuffle-exchange networks, distributed tag-based controlalgorithm, stochastic environment, buffercapacity, performance evaluation, performance, architecture, multiprocessors, connectivity, multiprocessor interconnection networks, multiprocessing systems, structural properties, destination, source, dynamic properties, parallelarchitectures |
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