Search results for "parasitics"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
72	Edoardo Charbon, Paolo Miliozzi, Enrico Malavasi, Alberto L. Sangiovanni-Vincentelli	Generalized constraint generation in the presence of non-deterministic parasitics.	ICCAD	1996	DBLP DOI BibTeX RDF	constraint-driven layout synthesis, non-deterministic parasitics, constraint generation
61	Zheng Liu, Lihong Zhang	Performance-constrained template-driven retargeting for analog and RF layouts.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	optimization, performance, layout, retargeting, parasitics
61	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos	Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	dual oxide technology, nano-cmos, performance aware design, vco, process variation, parasitics, power aware design
49	Carsten Wegener, Michael Peter Kennedy	Overcoming Test Setup Limitations by Applying Model-Based Testing to High-Precision ADCs.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	model-based ADC test, device interface parasitics, Design-for-Test
49	Sambuddha Bhattacharya, Nuttorn Jangkrajarng, C.-J. Richard Shi	Template-driven parasitic-aware optimization of analog integrated circuit layouts.	DAC	2005	DBLP DOI BibTeX RDF	analog layout automation, optimization, sensitivity, parasitics
49	Raoul F. Badaoui, Hemanth Sampath, Anuradha Agarwal, Ranga Vemuri	A high level language for pre-layout extraction in parasite-aware analog circuit synthesis.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	MSL, pre-layout extraction, parasitics, analog VLSI
48	Chenggang Xu, Ranjit Gharpurey, Terri S. Fiez, Kartikeya Mayaram	Extraction of Parasitics in Inhomogeneous Substrates With a New Green Function-Based Method.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
48	Nishath K. Verghese, David J. Allstot	SUBTRACT: a program for the efficient evaluation of substrate parasitics in integrated circuits.	ICCAD	1995	DBLP DOI BibTeX RDF
48	Ranjit Gharpurey, Srinath Hosur	Transform domain techniques for efficient extraction of substrate parasitics.	ICCAD	1997	DBLP DOI BibTeX RDF	Green Function, orthonormal transforms, parasitics, substrate coupling
37	Nancy Ying Zhou, Rouwaida Kanj, Kanak Agarwal, Zhuo Li 0001, Rajiv V. Joshi, Sani R. Nassif, Weiping Shi	The impact of BEOL lithography effects on the SRAM cell performance and yield.	ISQED	2009	DBLP DOI BibTeX RDF
37	Zheng Liu, Lihong Zhang	Performance-constrained parasitic-aware retargeting and optimization of analog layouts.	CCECE	2009	DBLP DOI BibTeX RDF
37	Lihong Zhang, Nuttorn Jangkrajarng, Sambuddha Bhattacharya, C.-J. Richard Shi	Parasitic-Aware Optimization and Retargeting of Analog Layouts: A Symbolic-Template Approach.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
37	N. S. Nagaraj, Tom Bonifield, Abha Singh, Roger Griesmer, Poras T. Balsara	Interconnect Modeling for Copper/Low-k Technologies.	VLSI Design	2004	DBLP DOI BibTeX RDF
37	N. S. Nagaraj, Tom Bonifield, Abha Singh, Frank Cano, Usha Narasimha, Mak Kulkarni, Poras T. Balsara, Cyrus D. Cantrell	Benchmarks for Interconnect Parasitic Resistance and Capacitance.	ISQED	2003	DBLP DOI BibTeX RDF
37	Mohamed Dessouky, Marie-Minerve Louërat	A Layout Approach for Electrical and Physical Design Integration of High-Performance Analog Circuits.	ISQED	2000	DBLP DOI BibTeX RDF	Analog layout, layout generation
37	Rex Lowther	Compact modeling of interconnect and substrate coupling at GHz frequencies.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
37	Andrew B. Kahng, Chung-Wen Albert Tsao	Practical Bounded-Skew Clock Routing.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
37	Umakanta Choudhury, Alberto L. Sangiovanni-Vincentelli	Automatic generation of parasitic constraints for performance-constrained physical design of analog circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
37	Umakanta Choudhury, Alberto L. Sangiovanni-Vincentelli	Constraint Generation for Routing Analog Circuits.	DAC	1990	DBLP DOI BibTeX RDF
36	Nuttorn Jangkrajarng, Lihong Zhang, Sambuddha Bhattacharya, Nathan Kohagen, C.-J. Richard Shi	Template-based parasitic-aware optimization and retargeting of analog and RF integrated circuit layouts.	ICCAD	2006	DBLP DOI BibTeX RDF	analog/RF integrated circuits, layout automation, layout symmetry, design reuse, parasitics
36	Bikram Baidya, Tamal Mukherjee	Extraction and LVS for mixed-domain integrated MEMS layouts.	ICCAD	2002	DBLP DOI BibTeX RDF	MEMS LVS, MEMS extraction, integrated MEMS, verification, parasitics
36	Frederik Beeftink, Arjan J. van Genderen, N. P. van der Meijs	Accurate and efficient layout-to-circuit extraction for high-speed MOS and bipolar/BiCMOS integrated circuits.	ICCD	1995	DBLP DOI BibTeX RDF	MOS integrated circuits, bipolar integrated circuits, BiCMOS integrated circuits, layout-to-circuit extraction, high-speed MOS integrated circuits, bipolar/BiCMOS integrated circuits, device recognition, equivalent network, layout parasitics, interconnects, circuit analysis computing, circuit layout CAD, Space, Spice, device modeling
36	Nancy Ying Zhou, Zhuo Li 0001, Yuxin Tian, Weiping Shi, Frank Liu 0001	A New Methodology for Interconnect Parasitics Extraction Considering Photo-Lithography Effects.	ASP-DAC	2007	DBLP DOI BibTeX RDF
36	Eunseok Song, Heeseok Lee, Jungtae Lee, Woojin Jin, Kiwon Choi, Sa-Yoon Kang	Upper/Lower Boundary Estimation of Package Interconnect Parasitics for Chip-Package Co-Design.	ISQED	2007	DBLP DOI BibTeX RDF
36	Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram	An error control method for application of the discrete cosine transform to extraction of substrate parasitics in ICs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
36	Ajit Sharma, Patrick Birrer, Sasi Kumar Arunachalam, Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram	Accurate Prediction of Substrate Parasitics in Heavily Doped CMOS Processes Using a Calibrated Boundary Element Solver.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
36	Michael W. Beattie, Lawrence T. Pileggi	Parasitics extraction with multipole refinement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
36	Martin R. Frerichs	Precise extraction of ultra deep submicron interconnect parasitics with parameterizable 3D-modeling: invited talk.	ASP-DAC	2001	DBLP DOI BibTeX RDF
36	H. Levy, W. Scott, Don MacMillen, Jacob White 0001	A rank-one update method for efficient processing of interconnect parasitics in timing analysis.	DAC	2000	DBLP DOI BibTeX RDF
36	Mariusz Niewczas, Adam Wojtasik	Modeling of VLSI RC parasitics based on the network reduction algorithm.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
36	Teng-Sin Pong, Martin A. Brooke	A parasitics extraction and network reduction algorithm for analog VLSI.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
36	Jacques Wenin, Johan Verhasselt, Marc Van Camp, Jean Leonard, Pierre Guebels	Rule-based VLSI Verification System Constrained by Layout Parasitics.	DAC	1989	DBLP DOI BibTeX RDF
25	Vinayak Honkote, Baris Taskin	PEEC based parasitic modeling for power analysis on custom rotary rings.	ISLPED	2010	DBLP DOI BibTeX RDF	resonant clocking, simulation, modeling, interconnect
25	Ali Davoudi, Juri Jatskevich, Patrick L. Chapman	Computer-Aided Average-Value Modeling of Fourth-Order PWM DC-DC Converters.	ISCAS	2007	DBLP DOI BibTeX RDF
25	Massimo Alioto, Gaetano Palumbo	Design of Fast Large Fan-In CMOS Multiplexers Accounting for Interconnects.	ISCAS	2007	DBLP DOI BibTeX RDF
25	Scott B. Kuntze, Lacra Pavel, J. Stewart Aitchison	Novel gain control in a multichannel semiconductor optical amplifier with equivalent circuit using nonlinear state-space methods.	BROADNETS	2007	DBLP DOI BibTeX RDF
25	Ning Fu, Mitsutoshi Mineshima, Shigetoshi Nakatake	Multi-SP: A Representation with United Rectangles for Analog Placement and Routing.	ISVLSI	2006	DBLP DOI BibTeX RDF
25	Di Long, Xianlong Hong, Sheqin Dong	Signal-path driven partition and placement for analog circuit.	ASP-DAC	2006	DBLP DOI BibTeX RDF	analog placement, device merging, layout automation, signal-path, symmetry constrain, circuit partition
25	Amitava Bhaduri, Ranga Vemuri	Parasitic Aware Routing Methodology Based on Higher Order RLCK Moment Metrics.	VLSI Design	2006	DBLP DOI BibTeX RDF
25	Anuradha Agarwal, Ranga Vemuri	Layout-Aware RF Circuit Synthesis Driven by Worst Case Parasitic Corners.	ICCD	2005	DBLP DOI BibTeX RDF
25	Hiroaki Yoshida, Kaushik De, Vamsi Boppana	Accurate pre-layout estimation of standard cell characteristics.	DAC	2004	DBLP DOI BibTeX RDF	cell characterization, transistor-level optimization, standard cell
25	Lin Jia, Alper Cabuk, Jianguo Ma, Kiat Seng Yeo	A 52 GHz VCO with Low Phase Noise Implemented in SiGe BiCMOS Technology.	IWSOC	2003	DBLP DOI BibTeX RDF
25	Xin Li 0001, Peng Li 0001, Yang Xu 0017, Lawrence T. Pileggi	Analog and RF circuit macromodels for system-level analysis.	DAC	2003	DBLP DOI BibTeX RDF	analog/RF circuits, macromodel
25	Carl De Ranter, Geert Van der Plas, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen	CYCLONE: automated design and layout of RF LC-oscillators.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
25	Peng Li 0001, Lawrence T. Pileggi	A Linear-Centric Modeling Approach to Harmonic Balance Analysis.	DATE	2002	DBLP DOI BibTeX RDF
25	Andrew B. Kahng, Chung-Wen Albert Tsao	More Practical Bounded-Skew Clock Routing.	DAC	1997	DBLP DOI BibTeX RDF
24	Chuanyi Yang, Swagato Chakraborty, Dipanjan Gope, Vikram Jandhyala	A parallel low-rank multilevel matrix compression algorithm for parasitic extraction of electrically large structures.	DAC	2006	DBLP DOI BibTeX RDF	parallel, MPI, compression, parasitics
24	Dipanjan Gope, Indranil Chowdhury, Vikram Jandhyala	DiMES: multilevel fast direct solver based on multipole expansions for parasitic extraction of massively coupled 3D microelectronic structures.	DAC	2005	DBLP DOI BibTeX RDF	non-iterative, parasitics, multilevel, multipole
24	Dipanjan Gope, Swagato Chakraborty, Vikram Jandhyala	A fast parasitic extractor based on low-rank multilevel matrix compression for conductor and dielectric modeling in microelectronics and MEMS.	DAC	2004	DBLP DOI BibTeX RDF	conductors and dielectrics, low-rank, parasitics, multilevel
24	Marian K. Kazimierczuk, Fabio Corti, Gabriele Maria Lozito, Alberto Reatti	Non-Isolated Zeta PWM DC-DC Power Converter Analysis for CCM Including Parasitics.	IEEE Access	2024	DBLP DOI BibTeX RDF
24	Eun-Bin Park, Taigon Song	Complementary FET (CFET) Standard Cell Design for Low Parasitics and Its Impact on VLSI Prediction at 3-nm Process.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
24	Rashmi Patel, Rajagopalan Chudamani	Experimental Investigation on Influence of Parasitics on Stability of Multi-Converter System and Analysis of Optimum Performance.	IECON	2023	DBLP DOI BibTeX RDF
24	Erez Zolkov, Emanuel Cohen	Analysis and Modeling of N-Path Circuits Peak Frequency Shift Caused by Switch Parasitics.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
24	Md Hasibul Amin, Mohammed E. Elbtity, Ramtin Zand	Interconnect Parasitics and Partitioning in Fully-Analog In-Memory Computing Architectures.	CoRR	2022	DBLP BibTeX RDF
24	Md Hasibul Amin, Mohammed E. Elbtity, Ramtin Zand	Xbar-Partitioning: A Practical Way for Parasitics and Noise Tolerance in Analog IMC Circuits.	IEEE J. Emerg. Sel. Topics Circuits Syst.	2022	DBLP DOI BibTeX RDF
24	Saurabh Sirohi, Beng Woon Lim, Ajay Raman, Frederick A. Anderson	Impact of Layout Parasitics and Thermal Coupling on PA performance and ruggedness in SiGe HBTs.	BCICTS	2022	DBLP DOI BibTeX RDF
24	Vidya A. Chhabria, Wenjing Jiang, Andrew B. Kahng, Sachin S. Sapatnekar	From Global Route to Detailed Route: ML for Fast and Accurate Wire Parasitics and Timing Prediction.	MLCAD	2022	DBLP DOI BibTeX RDF
24	Md Hasibul Amin, Mohammed E. Elbtity, Ramtin Zand	Interconnect Parasitics and Partitioning in Fully-Analog In-Memory Computing Architectures.	ISCAS	2022	DBLP DOI BibTeX RDF
24	Linkai Li, Qiao Zhang, Run Min, Kan Liu 0002, Qiaoling Tong, Dian Lyu	A Current Reshaping Strategy to Reduce Parasitics-Induced Current Distortion in Discontinuous Conduction Mode Boost Power Factor Correction Converter.	IEEE Trans. Ind. Electron.	2021	DBLP DOI BibTeX RDF
24	Hongyue Zhu, Xinhong Cheng, Wai Tung Ng, Dawei Xu, Xinchang Li, Yifei Xia	A Self-Adaptive Measurement System for IGBT Collector Current Using Package Parasitics.	IEEE Trans. Ind. Electron.	2021	DBLP DOI BibTeX RDF
24	David Berthiaume, Jean-Jacques Laurin, Nicolas G. Constantin	Anti-Series Varactor Network With Improved Linearity Performances in the Presence of Inductive and Capacitive Parasitics.	IEEE Access	2021	DBLP DOI BibTeX RDF
24	Rafid Adnan Khan, Mohammad Muhtady Muhaisin, Gordon W. Roberts	Extracting RLC Parasitics From a Flexible Electronic Hybrid Assembly Using On-Chip ESD Protection Circuits.	IEEE Trans. Circuits Syst. I Regul. Pap.	2021	DBLP DOI BibTeX RDF
24	Roberto Rubino, Paolo Stefano Crovetti, Francesco Musolino	FPGA-Based Relaxation D/A Converters With Parasitics-Induced Error Suppression and Digital Self-Calibration.	IEEE Trans. Circuits Syst. I Regul. Pap.	2021	DBLP DOI BibTeX RDF
24	Sherin A. Thomas, Sahibia Kaur Vohra, Rahul Kumar, Rohit Sharma, Devarshi Mrinal Das	Analysis of Parasitics on CMOS based Memristor Crossbar Array for Neuromorphic Systems.	MWSCAS	2021	DBLP DOI BibTeX RDF
24	Eun-Bin Park, Taigon Song	An Optimized Standard Cell Design Methodology Targeting Low Parasitics and Small Area for Complementary FETs (CFETs).	ISOCC	2021	DBLP DOI BibTeX RDF
24	Amira Nabil, Jose A. Bernardo, Yue Ma, Mohamed Abouelatta, Ahmed Shaker, Latifa Fakri-Bouchet, Hani F. Ragai, Christian Gontrand	Electrical modeling of tapered TSV including MOS-Field effect and substrate parasitics: Analysis and application.	Microelectron. J.	2020	DBLP DOI BibTeX RDF
24	Haoxing Ren, George F. Kokai, Walker J. Turner, Ting-Sheng Ku	ParaGraph: Layout Parasitics and Device Parameter Prediction using Graph Neural Networks.	DAC	2020	DBLP DOI BibTeX RDF
24	Vivek T. Bharambe, Jinwoo Ma, Michael D. Dickey, Jacob J. Adams	Planar, Multifunctional 3D Printed Antennas Using Liquid Metal Parasitics.	IEEE Access	2019	DBLP DOI BibTeX RDF
24	Antonio Alex-Amor, Javier Moreno-Núñez, Jose-Manuel Fernandez-Gonzalez, Pablo Padilla, Jaime Esteban	Parasitics Impact on the Performance of Rectifier Circuits in Sensing RF Energy Harvesting.	Sensors	2019	DBLP DOI BibTeX RDF
24	Martin Kovác, Daniel Arbet, Viera Stopjaková, Michal Sovcik, Lukás Nagy	Investigation of Low-Voltage, Sub-threshold Charge Pump with Parasitics Aware Design Methodology.	DDECS	2019	DBLP DOI BibTeX RDF
24	Zhixing Zhao, Patrick James Artz, Klaus Hempel, Juergen Faul, Tianbing Chen, Richard Taylor, Jerome Mazurier, Carsten Grass, Jan Hoentschel, David Harame, Steffen Lehmann, Luca Lucci, Yogadissen Andee, Alexis Divay, Luca Pirro, Tom Herrmann, Alban Zaka, Ricardo Sousa	22FDX® fMAX Optimization through Parasitics Reduction and GM Boost.	ESSDERC	2019	DBLP DOI BibTeX RDF
24	Piotr Zajac, Mariusz Jankowski, Piotr Amrozik, Michal Szermer	Application of Offset Trimming Circuit for Reducing the Impact of Parasitics in Capacitive Sensor Readout Circuit.	MIXDES	2019	DBLP DOI BibTeX RDF
24	Axel Hald, Pekka Herzogenrath, Jürgen Scheible, Jens Lienig, Johannes Seelhorst, Peter Brandl	Full custom MEMS design: A new method for the analysis of motion-dependent parasitics.	Integr.	2018	DBLP DOI BibTeX RDF
24	Anne Beyreuther, Norbert Herfurth, Elham Amini, Tomonori Nakamura, Ingrid De Wolf, Christian Boit	Photon emission as a characterization tool for bipolar parasitics in FinFET technology.	Microelectron. Reliab.	2018	DBLP DOI BibTeX RDF
24	Edi Emanovic, Drazen Jurisic, George S. Moschytz	Influence of CMOS CCII Parasitics in Realization of Two-Integrator Band-Pass Filter.	MWSCAS	2018	DBLP DOI BibTeX RDF
24	Georg Gläser, Martin Grabmann, Dirk Nuernbergk	Impact Rating of Layout Parasitics in Mixed-Signal Circuits: Finding a Needle in a Haystack.	SMACD	2018	DBLP DOI BibTeX RDF
24	Fábio Passos, Ricardo Martins 0003, Nuno C. Lourenço, Elisenda Roca, Rafael Castro-López, Ricardo Povoa, António Canelas, Nuno Horta, Francisco V. Fernández 0001	Handling the Effects of Variability and Layout Parasitics in the Automatic Synthesis of LNAs.	SMACD	2018	DBLP DOI BibTeX RDF
24	Debjani Chakraborty, Elena Breaz, Akshay Kumar Rathore, Fei Gao 0003	Parasitics-Assisted Soft-Switching and Secondary Modulated Snubberless Clamping Current-Fed Bidirectional Voltage Doubler for Fuel Cell Vehicles.	IEEE Trans. Veh. Technol.	2017	DBLP DOI BibTeX RDF
24	Hossein Ghafarian, Christian Moranz, Mahdi Rajabzadeh, Joachim Leicht, Yiannos Manoli	A fully integrated charge pump using parasitics to increase the usable capacitance by 25 % and the efficiency by up to 18 % with poly-poly capacitors.	MWSCAS	2017	DBLP DOI BibTeX RDF
24	Axel Hald, Johannes Seelhorst, Pekka Herzogenrath, Jürgen Scheible, Jens Lienig	A new method for the analysis of movement dependent parasitics in full custom designed MEMS sensors.	SMACD	2017	DBLP DOI BibTeX RDF
24	Moon Seok Kim, William Cane-Wissing, Xueqing Li, Jack Sampson, Suman Datta, Sumeet Kumar Gupta, Vijaykrishnan Narayanan	Comparative Area and Parasitics Analysis in FinFET and Heterojunction Vertical TFET Standard Cells.	ACM J. Emerg. Technol. Comput. Syst.	2016	DBLP DOI BibTeX RDF
24	Mayank Kumar 0001, Rajesh Gupta 0002	Stability and Sensitivity Analysis of Uniformly Sampled DC-DC Converter With Circuit Parasitics.	IEEE Trans. Circuits Syst. I Regul. Pap.	2016	DBLP DOI BibTeX RDF
24	Yulin Zhang, Edoardo Bonizzoni, Franco Maloberti	Mismatch and parasitics limits in capacitors-based SAR ADCs.	ICECS	2016	DBLP DOI BibTeX RDF
24	Ritwik Chattopadhyay, Mark A. Juds, Paul R. Ohodnicki, Subhashish Bhattacharya	Modelling, design and analysis of three limb high frequency transformer including transformer parasitics, for SiC Mosfet based three port DAB.	IECON	2016	DBLP DOI BibTeX RDF
24	Mina Wahib, Alois P. Freundorfer	A miniaturized lumped element directional coupler with parasitics compensation.	ISCAS	2016	DBLP DOI BibTeX RDF
24	Om. Prakash, Satish Maheshwaram, Mohit Sharma 0003, Anand Bulusu, A. K. Saxena, S. K. Manhas	A unified Verilog-A compact model for lateral Si nanowire (NW) FET incorporating parasitics for circuit simulation.	VDAT	2016	DBLP DOI BibTeX RDF
24	Jen-Huan Tsai, Sheng-An Ko, Chia-Wei Wang, Yang-Chi Yen, Hui-Huan Wang, Po-Chiun Huang, Po-Hsiang Lan, Meng-Hung Shen	A 1 V Input, 3 V-to-6 V Output, 58%-Efficient Integrated Charge Pump With a Hybrid Topology for Area Reduction and an Improved Efficiency by Using Parasitics.	IEEE J. Solid State Circuits	2015	DBLP DOI BibTeX RDF
24	Adam Rudzinski	Modelling of battery-powered boost DC-DC power LED driver with parasitics by multivariate power series expansion.	Int. J. Circuit Theory Appl.	2015	DBLP DOI BibTeX RDF
24	Chika Tanaka, Keiji Ikeda, Masumi Saitoh	New layout design methodology for monolithically integrated 3D CMOS logic circuits based on parasitics engineering.	ESSDERC	2015	DBLP DOI BibTeX RDF
24	Gábor Tóth, Attila Zolomy, Gábor Fehér, Tibor Berceli	Effect of parasitics in tunable X-band metamaterial isolators.	ICTON	2015	DBLP DOI BibTeX RDF
24	Debjani Chakraborty, Akshay Kumar Rathore, Elena Breaz, Fei Gao 0003	Parasitics assisted soft-switching and naturally commutated current-fed bidirectional push-pull voltage doubler.	IAS	2015	DBLP DOI BibTeX RDF
24	Ying Qiu, Xiyou Chen, Chongquan Zhong, Chen Qi	Uniform Models of PWM DC-DC Converters for Discontinuous Conduction Mode Considering Parasitics.	IEEE Trans. Ind. Electron.	2014	DBLP DOI BibTeX RDF
24	Ajay N. Bhoj, Niraj K. Jha	Parasitics-Aware Design of Symmetric and Asymmetric Gate-Workfunction FinFET SRAMs.	IEEE Trans. Very Large Scale Integr. Syst.	2014	DBLP DOI BibTeX RDF
24	Rachid Hamani, Cristian Andrei, Bernard Jarry, Mien Lintignat	LNA circuit design counting the interconnect line parasitics.	ICECS	2014	DBLP DOI BibTeX RDF
24	Alberto Rodríguez-Pérez, Manuel Delgado-Restituto, Fernando Medeiro	Impact of parasitics on even symmetric split-capacitor arrays.	Int. J. Circuit Theory Appl.	2013	DBLP DOI BibTeX RDF
24	Saraju P. Mohanty	A Special Issue on Power, Parasitics, and Process-Variation (P3) Awareness in Mixed-Signal Design.	J. Low Power Electron.	2012	DBLP DOI BibTeX RDF
24	Joris Lacord, Perrine Batude, Gérard Ghibaudo, Frédéric Boeuf	Analytical modeling of parasitics in monolithically integrated 3D inverters.	ICICDT	2012	DBLP DOI BibTeX RDF
24	Giuseppe Pasetti, Nico Costantino, Francesco Tinfena, Riccardo Serventi, Paolo D'Abramo, Sergio Saponara, Luca Fanucci	Characterization of an Intelligent Power Switch for LED driving with control of wiring parasitics effects.	DATE	2011	DBLP DOI BibTeX RDF
24	Kuen-Yu Tsai, Wei-Jhih Hsieh, Yuan-Ching Lu, Bo-Sen Chang, Sheng-Wei Chien, Yi-Chang Lu	A new method to improve accuracy of parasitics extraction considering sub-wavelength lithography effects.	ASP-DAC	2010	DBLP DOI BibTeX RDF
24	Samuel R. Cove, Martin Ordonez, John E. Quaicoe	Modeling of planar transformer parasitics using design of experiment methodology.	CCECE	2010	DBLP DOI BibTeX RDF