Search results for "pass-transistors"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
68	Mike Sheng, Jonathan Rose	Mixing buffers and pass transistors in FPGA routing architectures.	FPGA	2001	DBLP DOI BibTeX RDF
38	Spiridon Nikolaidis 0001, Haroula Pournara, Alexander Chatzigeorgiou	Output Waveform Evaluation of Basic Pass Transistor Structure.	PATMOS	2002	DBLP DOI BibTeX RDF
34	Eric Kusse, Jan M. Rabaey	Low-energy embedded FPGA structures.	ISLPED	1998	DBLP DOI BibTeX RDF	dual voltage, pass-transistors, FPGAs, interconnect network, embedded, power, low energy, low swing
31	Andrea Lodi 0002, Luca Ciccarelli, Roberto Giansante	Combining low-leakage techniques for FPGA routing design.	FPGA	2005	DBLP DOI BibTeX RDF	low leakage, FPGA, power
28	Hafiz Md. Hasan Babu, Moinul Islam Zaber, Md. Mazder Rahman, Md. Rafiqul Islam 0001	Implementation of Multiple-Valued Flip-Flips Using Pass Transistor Logic.	DSD	2004	DBLP DOI BibTeX RDF
28	Michel R. C. M. Berkelaar, Lukas P. P. P. van Ginneken	Efficient orthonormality testing for synthesis with pass-transistor selectors.	ICCAD	1995	DBLP DOI BibTeX RDF
24	Hafiz Md. Hasan Babu, Md. Rafiqul Islam 0001, Amin Ahsan Ali, Mohammad Musa Salehin Akon	A Technique for Logic Design of Voltage-Mode Pass Transistor Based Multi-Valued Multiple-Output Logic Circuits.	ISMVL	2003	DBLP DOI BibTeX RDF	Multi-valued logic (MVL), TMOS logic circuits, Support set, Residual, Literals
23	Anna Richelli, Luca Mensi, Luigi Colalongo, Zsolt Miklós Kovács-Vajna, Pier Luigi Rolandi	A 1.2V-5V High Efficiency CMOS Charge Pump for Non-Volatile Memories.	ISCAS	2007	DBLP DOI BibTeX RDF
23	Fatih Hamzaoglu, Yibin Ye, Ali Keshavarzi, Kevin Zhang 0001, Siva G. Narendra, Shekhar Borkar, Mircea R. Stan, Vivek De	Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
23	Guy G. Lemieux, David M. Lewis	Circuit design of routing switches.	FPGA	2002	DBLP DOI BibTeX RDF
23	Prateek Jain 0006, Amit Mahesh Joshi	Full-Wave Bridge Rectifier with CMOS Pass Transistors Configuration.	J. Circuits Syst. Comput.	2018	DBLP DOI BibTeX RDF
23	Suresh Alapati, Sreehari Rao Patri	Capacitor Less Voltage Regulator with Split Drive Error Amplifier for Segmented Pass Transistors.	J. Low Power Electron.	2018	DBLP DOI BibTeX RDF
23	Alireza Saberkari, Farima Qaraqanabadi, Vahideh Shirmohammadli, Herminio Martínez, Eduard Alarcón	Output-capacitorless segmented low-dropout voltage regulator with controlled pass transistors.	Int. J. Circuit Theory Appl.	2016	DBLP DOI BibTeX RDF
23	Anna Richelli, Luigi Colalongo, Luca Mensi, Alessio Cacciatori, Zsolt Miklós Kovács-Vajna	Charge Pump Architectures Based on Dynamic Gate Control of the Pass-Transistors.	IEEE Trans. Very Large Scale Integr. Syst.	2009	DBLP DOI BibTeX RDF
23	Luca Mensi, Luigi Colalongo, Anna Richelli, Zsolt Miklós Kovács-Vajna	A new integrated charge pump architecture using dynamic biasing of pass transistors.	ESSCIRC	2005	DBLP DOI BibTeX RDF
23	Kazuo Yano, Saburo Muroga	Pass Transistors.	The VLSI Handbook	1999	DBLP DOI BibTeX RDF
22	John F. McDonald 0001, Bryan S. Goda	Reconfigurable FPGA's in the 1-20 GHz Band with HBT BiCMOS.	Evolvable Hardware	1999	DBLP DOI BibTeX RDF
18	Rodrigo Jaramillo-Ramirez, Mohab Anis	A Dual-Threshold FPGA Routing Design for Subthreshold Leakage Reduction.	ISCAS	2007	DBLP DOI BibTeX RDF
18	Charan Thondapu, Praveen Elakkumanan, Ramalingam Sridhar	RG-SRAM: A Low Gate Leakage Memory Design.	ISVLSI	2005	DBLP DOI BibTeX RDF
17	Mutlu Avci, Tülay Yildirim	A coding method for 123 decision diagram pass transistor logic circuit synthesis.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
17	Christoph Scholl 0001, Bernd Becker 0001	On the Generation of Multiplexer Circuits for Pass Transistor Logic.	DATE	2000	DBLP DOI BibTeX RDF
12	David Choi, Kyu Choi, John D. Villasenor	New Non-Volatile Memory Structures for FPGA Architectures.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
12	Gian Carlo Cardarilli, Luca Di Nunzio, Marco Re, Alberto Nannarelli	ADAPTO: full-adder based reconfigurable architecture for bit level operations.	ISCAS	2008	DBLP DOI BibTeX RDF
12	Scott Miller, Mihai Sima, Michael McGuire	Alternatives in Designing Level-Restoring Buffers for Interconnection Networks in Field-Programmable Gate Arrays.	DSD	2007	DBLP DOI BibTeX RDF
12	Yoichi Sasaki 0001, Kazuteru Namba, Hideo Ito	Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit.	DFT	2006	DBLP DOI BibTeX RDF
12	Subhadeep Banik, Daibashish Gangopadhyay, T. K. Bhattacharyya	A Low Power 1.8 V 4-Bit 400-MHz Flash ADC in 0.18µ Digital CMOS.	VLSI Design	2006	DBLP DOI BibTeX RDF
12	Yuanzhong Wan, Maitham Shams	Optimization of Mixed Logic Circuits with Application to a 64-Bit Static Adder.	VLSI Design	2005	DBLP DOI BibTeX RDF
12	Aman Gayasen, Narayanan Vijaykrishnan, Mary Jane Irwin	Exploring technology alternatives for nano-scale FPGA interconnects.	DAC	2005	DBLP DOI BibTeX RDF	FPGA, interconnect, nanotechnology, nanoelectronics
12	Wen-Ben Jone, Jinn-Shyan Wang, Hsueh-I Lu, I. P. Hsu, J.-Y. Chen	Design theory and implementation for low-power segmented bus systems.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	OLA tree, bus graph model, bus segmentation, bus segmentation cell, low-power design flow, low-power design, ASIC design
12	Massimo Alioto, Gaetano Palumbo	Analysis and comparison on full adder block in submicron technology.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
12	Per Lindgren, Mikael Kerttu, Mitchell A. Thornton, Rolf Drechsler	Low power optimization technique for BDD mapped circuits.	ASP-DAC	2001	DBLP DOI BibTeX RDF
12	Bryan S. Goda, Russell P. Kraft, Steven R. Carlough, Thomas W. Krawczyk Jr., John F. McDonald 0001	Gigahertz Reconfigurable Computing Using SiGe HBT BiCMOS FPGAs.	FPL	2001	DBLP DOI BibTeX RDF
12	Wei Chen, Wing-Hung Ki, Philip K. T. Mok, Mansun Chan	Switched-capacitor power converters with integrated low dropout regulators.	ISCAS (3)	2001	DBLP DOI BibTeX RDF
12	J.-Y. Chen, Wen-Ben Jone, Jinn-Shyan Wang, Hsueh-I Lu, Tien-Fu Chen	Segmented bus design for low-power systems.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
12	Bassem A. Alhalabi, Qutaibah M. Malluhi, Rafic A. Ayoubi	Non-Refreshing Analog Neural Storage Tailored for On-Chip Learning.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	non-refreshing static storage, on-chip learning neural networks, analog learning