Search results for "pipeline"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
97	Zhenpei Li, Ping Li, Ming Wu	Digital oil and gas pipeline visualization using X3D.	Web3D	2009	DBLP DOI BibTeX RDF	Java native interface (JNI), OLE for process control (OPC), digital oil and gas pipeline, scene access interface (SAI), visualization, interaction, 3D modeling, extensible 3D (X3D)
85	Asger Munk Nielsen, David W. Matula, Chung Nan Lyu, Guy Even	Pipelined Packet-Forwarding Floating Point: II. An Adder.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	pipelined packet forwarding floating point, floating point addition algorithm, adder pipeline design, packet forwarding pipeline paradigm, data hazards, deeply pipelined floating point pipelines, four stage execution phase pipeline, short clock period, fifteen logic levels, addition algorithm, standard binary floating point format, standard IEEE 754 rounded result, two cycle latency, cooperating multiplier pipeline, packet forwarding operand, IEEE 754 binary floating point compatibility, pipeline arithmetic
81	Jinson Koppanalil, Prakash Ramrakhyani, Sameer Desai, Anu Vaidyanathan, Eric Rotenberg	A case for dynamic pipeline scaling.	CASES	2002	DBLP DOI BibTeX RDF	configurable pipeline, fetch gating, power and energy management, shallow and deep pipelines, variable-depth pipeline, dynamic voltage scaling, clock gating
73	Aristides Efthymiou, Jim D. Garside, Ioannis Papaefstathiou	A Low-Power Processor Architecture Optimized forWireless Devices.	ASAP	2005	DBLP DOI BibTeX RDF	Pipeline depth, configurable pipeline, power-adaptive processors, Low power, asynchronous circuits
69	Zeshan Chishti, T. N. Vijaykumar	Optimal Power/Performance Pipeline Depth for SMT in Scaled Technologies.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Power Management, Performance of Systems, Multithreaded processors
69	Hans M. Jacobson	Improved clock-gating through transparent pipelining.	ISLPED	2004	DBLP DOI BibTeX RDF	adaptive pipeline depth, dynamic pipeline scaling, optimal pipeline clocking, pipeline stage unification, transparent pipeline, low power, high performance, microarchitecture, circuits, clock gating
68	Chia-Hsing Chien, Mark A. Franklin, Tienyo Pan, Prithvi Prabhu	ARAS: asynchronous RISC architecture simulator.	ASYNC	1995	DBLP DOI BibTeX RDF	asynchronous RISC architecture simulator, ARAS, pipeline instruction simulator, benchmark programs, pipeline configuration, asynchronous pipeline architectures, performance evaluation, parallel architectures, virtual machines, performance measurements, pipeline processing
60	Heather Quinn, Laurie A. Smith King, Miriam Leeser, Waleed Meleis	Runtime Assignment of Reconfigurable Hardware Components for Image Processing Pipelines.	FCCM	2003	DBLP DOI BibTeX RDF
60	Aravindh Anantaraman, Kiran Seth, Kaustubh Patil, Eric Rotenberg, Frank Mueller 0001	Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems.	ISCA	2003	DBLP DOI BibTeX RDF
58	Allan Hartstein, Thomas R. Puzak	The Optimum Pipeline Depth for a Microprocessor.	ISCA	2002	DBLP DOI BibTeX RDF
58	Mark S. Squillante, David R. Kaeli, Himanshu Sinh	Analytic Models of Workload Behavior and Pipeline Performance.	MASCOTS	1997	DBLP DOI BibTeX RDF
58	Svetlana P. Kartashev, Steven I. Kartashev	Adaptable pipeline system with dynamic architecture.	AFIPS National Computer Conference	1981	DBLP DOI BibTeX RDF
57	Arthur Abnous, Nader Bagherzadeh	Pipelining and Bypassing in a VLIW Processor.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	VLIWprocessor, very long instruction word, pipeline data hazards, performance evaluation, performance, parallel architectures, computer architecture, pipeline processing, pipeline structure, bypassing
56	Ing-Jer Huang	Co-synthesis of pipelined structures and instruction reordering constraints for instruction set processors.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	compiler instruction optimization, instruction set processor, pipeline hazards, pipeline taxonomy, synthesis
56	Viswanathan Subramanian, Arun K. Somani	Conjoined Pipeline: Enhancing Hardware Reliability and Performance through Organized Pipeline Redundancy.	PRDC	2008	DBLP DOI BibTeX RDF
55	Sailesh Kumar, Michela Becchi, Patrick Crowley, Jonathan S. Turner	CAMP: fast and efficient IP lookup architecture.	ANCS	2006	DBLP DOI BibTeX RDF	IP lookup, longest prefix match, internet router
55	Seongwoo Kim, Arun K. Somani	SSD: An Affordable Fault Tolerant Architecture for Superscalar Processors.	PRDC	2001	DBLP DOI BibTeX RDF
53	Tao Feng, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi, Fred J. Meyer	Reliability Modeling and Assurance of Clockless Wave Pipeline.	DFT	2004	DBLP DOI BibTeX RDF
53	Ayman M. El-Khashab, Earl E. Swartzlander Jr.	An Architecture for a Radix-4 Modular Pipeline Fast Fourier Transform.	ASAP	2003	DBLP DOI BibTeX RDF
49	Sang Ok Koo, Hyuk Don Kwon, Chang Geol Yoon, Won Seok Seo, Soon Ki Jung	Visualization for a Multi-Sensor Data Analysis.	CGIV	2006	DBLP DOI BibTeX RDF
49	Prabhat Mishra 0001, Nikil D. Dutt	Modeling and validation of pipeline specifications.	ACM Trans. Embed. Comput. Syst.	2004	DBLP DOI BibTeX RDF	Modeling of processor pipeline, pipeline validation, pipelined processor specification, architecture description language
49	Masayuki Tsukisaka, Takashi Nanya	A testable design for asynchronous fine-grain pipeline circuits.	PRDC	2000	DBLP DOI BibTeX RDF	asynchronous fine-grain pipeline circuits, dynamic gates, high-performance datapath design, pipeline latches, scan latch libraries, logic testing, logic CAD, SPICE, CMOS technology, scan path, SPICE simulation, testable design
48	Shijing Wu, Qunli Li, Enyong Zhu, Jinjuan She, Ming Qin	A Hybrid Intelligent System for Pipeline Robot Navigation in Unknown Environment.	ICIRA (1)	2008	DBLP DOI BibTeX RDF	pipeline robot, neural network, navigation, fuzzy controller
48	John Biddiscombe, Berk Geveci, Ken Martin, Kenneth Moreland, David C. Thompson 0001	Time Dependent Processing in a Parallel Pipeline Architecture.	IEEE Trans. Vis. Comput. Graph.	2007	DBLP DOI BibTeX RDF	data-parallel visualization pipeline, time-varying data
48	Abhishek Tiwari 0002, Smruti R. Sarangi, Josep Torrellas	ReCycle: : pipeline adaptation to tolerate process variation.	ISCA	2007	DBLP DOI BibTeX RDF	pipeline, process variation, clock skew
48	Allan Hartstein, Thomas R. Puzak	The optimum pipeline depth considering both power and performance.	ACM Trans. Archit. Code Optim.	2004	DBLP DOI BibTeX RDF	Pipeline Depth, Power and Performance, Workload Specificity, Simulation
48	Kerstin Eder, Geoff Barrett	Achieving maximum performance: a method for the verification of interlocked pipeline control logic.	DAC	2002	DBLP DOI BibTeX RDF	interlock logic, pipeline stall, verification
47	Shinichi Yamagiwa, Leonel Sousa	Design and implementation of a tool for modeling and programming deadlock free meta-pipeline applications.	IPDPS	2008	DBLP DOI BibTeX RDF
47	Sudsanguan Ngamsuriyaroj, Ekasit Kijsipongse	Optimal Placement of Pipeline Applications on Grid.	ICPADS	2008	DBLP DOI BibTeX RDF
47	Wook-Shin Han, Soon Ki Jung, Jeyong Shin, Jinsoo Lee, Mina Yoon, Chang Geol Yoon, Won Seok Seo, Sang Ok Koo	A Scalable Pipeline Data Processing Framework Using Database and Visualization Techniques.	ICIC (1)	2007	DBLP DOI BibTeX RDF	Scalable processing, Intelligent PIGs, Time series data
47	Chang-Ching Yeh, Kuei-Chung Chang, Tien-Fu Chen, Chingwei Yeh	Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling.	HiPEAC	2007	DBLP DOI BibTeX RDF
47	Abdel Ejnioui, Abdelhalim Alsharqawi	Pipeline-Level Control of Self-Resetting Pipelines.	DSD	2004	DBLP DOI BibTeX RDF
45	Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Nilanjan Banerjee, Kaushik Roy 0001	Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies.	DATE	2005	DBLP DOI BibTeX RDF
45	Abdel Ejnioui, Abdelhalim Alsharqawi	Self-resetting stage logic pipelines.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	clockless, self-resetting, pipeline, asynchronous
45	Wei-keng Liao, Alok N. Choudhary, Donald D. Weiner, Pramod K. Varshney	Design and Evaluation of I/O Strategies for Parallel Pipelined STAP Applications.	IPDPS	2000	DBLP DOI BibTeX RDF	space-time adaptive processing, parallel processing, parallel I/O, parallel file system, parallel pipeline
44	Timothy J. Dysart, Branden J. Moore, Lambert Schaelicke, Peter M. Kogge	Cache implications of aggressively pipelined high performance microprocessors.	ISPASS	2004	DBLP DOI BibTeX RDF
43	Alexandre Yakovlev, Victor Varshavsky, Vyacheslav Marakhovsky, Alexei L. Semenov	Designing an asynchronous pipeline token ring interface.	ASYNC	1995	DBLP DOI BibTeX RDF	asynchronous pipeline token ring interface, speed-independent interface, reliable communication medium, on-board multicomputer, asynchronous buses, point-to-point interconnections, syntax-driven implementation, channel protocol controller, protocols, fairness, multiprocessor interconnection networks, local area networks, pipeline processing, deadlock-freedom, token networks
43	Hai Zhao, Nicole Marie Sabine, Edwin Hsing-Mean Sha	Improving self-timed pipeline ring performance through the addition of buffer loops.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	buffer circuits, self-timed pipeline ring performance, buffer loops, communication scheme, communication delay reduction, data communication delay, pace handshaking overhead, initial system configuration, performance evaluation, delays, timing, logic design, asynchronous circuits, pipeline processing
42	Amy S. Bruckman, Maureen Biggers, Barbara Ericson, Tom McKlin, Jill P. Dimond, Betsy James DiSalvo, Mike Hewner, Lijun Ni, Sarita Yardi	"Georgia computes!": improving the computing education pipeline.	SIGCSE	2009	DBLP DOI BibTeX RDF	computing education pipeline, summer camps, introductory courses
42	Angeles G. Navarro, Rafael Asenjo, Siham Tabik, Calin Cascaval	Load balancing using work-stealing for pipeline parallelism in emerging applications.	ICS	2009	DBLP DOI BibTeX RDF	work-stealing, load imbalance, parallel pipeline
42	Wu Liu, Min Li, Yi Liu, Yuan Xu, Xinglan Yang	Decision of optimal scheduling scheme for gas field pipeline network based on hybrid genetic algorithm.	GEC Summit	2009	DBLP DOI BibTeX RDF	natural gas pipeline network, genetic algorithm, optimization, scheduling scheme, differential evolution algorithm
42	Nary Subramanian	Improving Security of Oil Pipeline SCADA Systems Using Service-Oriented Architectures.	OTM Workshops	2008	DBLP DOI BibTeX RDF	petroleum, security, architecture, pipeline, services, SCADA
42	Che-Wei Lin, Jeen-Shing Wang, Chun-Chang Yu, Ting-Yu Chen	Synchronous Pipeline Circuit Design for an Adaptive Neuro-fuzzy Network.	ICIC (2)	2007	DBLP DOI BibTeX RDF	Synchronous pipeline design, neuro-fuzzy circuit, FPGA
42	Arnab Roy 0001, Subrat Kumar Panda, Rajeev Kumar 0004, P. P. Chakrabarti 0001	A framework for systematic validation and debugging of pipeline simulators.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	Simulation-based verification, dataflow equivalence, pipeline validation, design space exploration, instruction scheduling, pipelined architectures
42	Swarnalatha Radhakrishnan, Hui Guo 0001, Sri Parameswaran	Dual-pipeline heterogeneous ASIP design.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	dual-pipeline, instruction set generation, ASIP, superscalar
42	Tao Feng, Byoungjae Jin, J. Wang, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi	Fault tolerant clockless wave pipeline design.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	clockless wave pipeline, inter-wave fault, intra-wave fault, fault tolerance, reliability
42	Jia Di, Jiann-Shiun Yuan	Power-aware pipelined multiplier design based on 2-dimensional pipeline gating.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	2-D pipeline gating, power-awareness, array multiplier
42	Weirong Jiang, Qingbo Wang, Viktor K. Prasanna	Beyond TCAMs: An SRAM-Based Parallel Multi-Pipeline Architecture for Terabit IP Lookup.	INFOCOM	2008	DBLP DOI BibTeX RDF
42	Bassam Jamil Mohd, Adnan Aziz, Earl E. Swartzlander Jr.	The hazard-free superscalar pipeline fast fourier transform algorithm and architecture.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
42	Suryanarayana Tatapudi, José G. Delgado-Frias	A mesochronous pipeline scheme for high performance low power digital systems.	ISCAS	2006	DBLP DOI BibTeX RDF
42	Bing-Fei Wu, Chung-Fu Lin	A high-performance and memory-efficient pipeline architecture for the 5/3 and 9/7 discrete wavelet transform of JPEG2000 codec.	IEEE Trans. Circuits Syst. Video Technol.	2005	DBLP DOI BibTeX RDF
42	Steve MacDonald, Duane Szafron, Jonathan Schaeffer	Rethinking the Pipeline as Object-Oriented States with Transformations.	HIPS	2004	DBLP DOI BibTeX RDF
42	Seokwoo Lee, Shidhartha Das, Toan Pham, Todd M. Austin, David T. Blaauw, Trevor N. Mudge	Reducing pipeline energy demands with local DVS and dynamic retiming.	ISLPED	2004	DBLP DOI BibTeX RDF	dynamic retiming with global DVS, local DVS, razor
42	Chris Y. Chung, Ravi Managuli, Yongmin Kim 0001	Design and Evaluation of a Multimedia Computing Architecture Based on a 3D Graphics Pipeline.	ASAP	2002	DBLP DOI BibTeX RDF
42	Michael Golden, Trevor N. Mudge	A comparison of two pipeline organizations.	MICRO	1994	DBLP DOI BibTeX RDF	pipelines, cache memory, RISC, memory system, interlocks
40	Sreeram Duvvuru, Siamak Arya	Evaluation of a branch target address cache.	HICSS (1)	1995	DBLP DOI BibTeX RDF	branch target address cache evaluation, sequential flow, pipeline bubbles, branch penalty, cycles per instruction, multiple instruction issue processors, branch resolution scheme, target instruction fetch, unpredictable branches, fully predicated processor architecture, fetch stage, branch target caching policies, branch target address cache, register-relative branches, performance evaluation, interrupts, interrupt, program compilers, pipeline processing, cache storage, storage allocation, instructions, program control structures, cache sizes
40	Shinichi Yamagiwa, Leonel Sousa, Tomás Brandão	Meta-Pipeline: A New Execution Mechanism for Distributed Pipeline Processing.	ISPDC	2007	DBLP DOI BibTeX RDF
38	Kenneth Eguro, Scott Hauck	Armada: timing-driven pipeline-aware routing for FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF	pipeline FPGA, pipeline routing, reconfigurable computing
38	Prathima Agrawal, Antony Ng	Computing Network Flow on a Multiple Processor Pipeline.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	multiple processor pipeline, Goldberg-Tarjan algorithm, network graph, six processors, distributed algorithms, graph theory, network flow, pipeline processing, parallel implementations, performance estimates, maximum flow, partitioned algorithm, message-passing multicomputer
37	Kuan-Wei Cheng, Tzong-Yen Lin, Rong-Guey Chang	Profile-based dynamic pipeline scaling.	J. Supercomput.	2009	DBLP DOI BibTeX RDF	DPS, Pipeline mode, Loop region, DVS, IPC
37	Allan MacKenzie-Graham, Arash Payan, Ivo D. Dinov, John D. Van Horn, Arthur W. Toga	Neuroimaging Data Provenance Using the LONI Pipeline Workflow Environment.	IPAW	2008	DBLP DOI BibTeX RDF	Grid, Workflow, Pipeline, Provenance, Neuroimaging
37	Ding Feng 0001, Chaobin Huang, Kui Zhou, Peng Wang, Jin Liu, Shouyong Li	Crucial Technology Research on Pipeline Jet Cleaning Robot.	ICIRA (2)	2008	DBLP DOI BibTeX RDF	crucial technology, robot, pipeline, cleaning
37	Mahmoud Lotfi Anhar, Mohammad Ali Jabraeil Jamali	The Optimum Location of Delay Latches Between Dynamic Pipeline Stages.	APPT	2007	DBLP DOI BibTeX RDF	Minimum, MAL, Pipeline, Latency, Collision, Table, Reservation, Latch, Average
37	Je-Hoon Lee, Seung-Sook Lee, Kyoung-Rok Cho	Asynchronous ARM Processor Employing an Adaptive Pipeline Architecture.	ARC	2007	DBLP DOI BibTeX RDF	adaptive pipeline, processor, Asynchronous design
37	Jian Ruan, Zhiying Wang 0003, Kui Dai, Yong Li 0006	Latency Estimation of the Asynchronous Pipeline Using the Max-Plus Algebra.	International Conference on Computational Science (4)	2007	DBLP DOI BibTeX RDF	Asynchronous Pipeline, Timed Event Graph, Evolution Equation, Latency Estimation, Max-Plus Algebra
37	Stavros Souravlas, Manos Roumeliotis	A Pipeline Technique for Dynamic Data Transfer on a Multiprocessor Grid.	Int. J. Parallel Program.	2004	DBLP DOI BibTeX RDF	Block-cyclic redistribution, processor classes, pipeline tasks, High Performance Fortran
37	Nianmin Yao, Ming-Yang Zheng, Jiu-bin Ju	Pipeline: a new architecture of high performance servers.	ACM SIGOPS Oper. Syst. Rev.	2002	DBLP DOI BibTeX RDF	architecture, web, pipeline, high performance, server
37	Kenneth J. Janik, Shih-Lien Lu, Michael F. Miller	Advances of the Counterflow Pipeline Microarchitecture.	HPCA	1997	DBLP DOI BibTeX RDF	counterflow, CFPP, virtual register, architecture, pipeline, dataflow, VRP
37	Val Donaldson, Jeanne Ferrante	Determining Asynchronous Acyclic Pipeline Execution Times.	IPPS	1996	DBLP DOI BibTeX RDF	asynchronous pipelining, parallel execution time, loop parallelism, task graph scheduling, pipeline scheduling
36	Peng Zhou, JiangHe Yao, JiuLing Pei	Implementation of an energy-efficient scheduling scheme based on pipeline flux leak monitoring networks.	Sci. China Ser. F Inf. Sci.	2009	DBLP DOI BibTeX RDF	dynamic modulation scaling, reclaiming scheme, sensor networks, real-time scheduling, EDF
36	Rama Sangireddy, Jatan P. Shah	Operand-Load-Based Split Pipeline Architecture for High Clock Rate and Commensurable IPC.	IEEE Trans. Parallel Distributed Syst.	2008	DBLP DOI BibTeX RDF
36	Mohammad Ghasemazar, Massoud Pedram	Minimizing the energy cost of throughput in a linear pipeline by opportunistic time borrowing.	ICCAD	2008	DBLP DOI BibTeX RDF
36	Huaqing Mao, Fuling Bian	Research on Constructing 3-D Pipeline Connection Model By Using OpenGL.	CSSE (2)	2008	DBLP DOI BibTeX RDF
36	Zhongli Ma, Hongda Liu	Pipeline defect detection and sizing based on MFL data using immune RBF neural networks.	IEEE Congress on Evolutionary Computation	2007	DBLP DOI BibTeX RDF
36	Jinhai Liu, Huaguang Zhang, Jian Feng 0001, Heng Yue	A New Fault Detection and Diagnosis Method for Oil Pipeline Based on Rough Set and Neural Network.	ISNN (3)	2007	DBLP DOI BibTeX RDF
36	Pingli Huang, Yun Chiu	A Gradient-Based Algorithm for Sampling Clock Skew Calibration of SHA-less Pipeline ADCs.	ISCAS	2007	DBLP DOI BibTeX RDF
36	Abdel Ejnioui, Abdelhalim Alsharqawi	Pipeline Design Based on Self-Resetting Stage Logic.	ISVLSI	2004	DBLP DOI BibTeX RDF
36	Rob A. Rutenbar, Li-C. Wang, Kwang-Ting Cheng, Sandip Kundu	Static statistical timing analysis for latch-based pipeline designs.	ICCAD	2004	DBLP DOI BibTeX RDF
36	Allan Hartstein, Thomas R. Puzak	Optimum Power/Performance Pipeline Depth.	MICRO	2003	DBLP DOI BibTeX RDF
36	Brian A. Wandell	Color Appearance and the Digital Imaging Pipeline.	ICPR	2000	DBLP DOI BibTeX RDF
36	Christopher A. Healy, Robert D. Arnold, Frank Mueller 0001, David B. Whalley, Marion G. Harmon	Bounding Pipeline and Instruction Cache Performance.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	best case execution time, Real-time systems, pipelining, timing analysis, worst case execution time, instruction cache
35	Kai Hwang 0001, Zhiwei Xu	Multipipeline Networking for Compound Vector Processing.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	compound vector processing, multipipeline networking, pipeline chaining, pipeline nets, run-time techniques, Livermore loops, performance evaluation, performance analysis, parallel programming, compilation, parallel architectures, programming, program compilers, pipeline processing, scientific programs, vector-processing, systolization
34	Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith 0001	A mechanistic performance model for superscalar out-of-order processors.	ACM Trans. Comput. Syst.	2009	DBLP DOI BibTeX RDF	Superscalar out-of-order processor, balanced processor design, mechanistic modeling, overprovisioned processor design, pipeline depth, pipeline width, resource scaling, wide front-end dispatch processors, performance modeling, analytical modeling
34	David W. Matula, Asger Munk Nielsen	Pipelined Packet-Forwarding Floating Point: I. Foundations and a Rounder.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	pipelined packet forwarding floating point, packet forwarding floating point format, rounder design, packet forwarding format, standard binary IEEE 754 floating point format, multiplication algorithms, ALU pipeline paradigm, data hazards, pipelined floating point operations, execution phases, multiplier packet forwarding pipelines, execution phase, logic levels, multiplier pipelines, forwarding pipelines, IEEE 754 binary floating point compatibility, pipeline arithmetic, data dependent operations
34	Zbigniew M. Wójcik, Barbara E. Wójcik	Rough Grammar For Efficient and Fault-Tolerant Computing on a Distributed System.	IEEE Trans. Software Eng.	1991	DBLP DOI BibTeX RDF	global load balancing, dynamic task scheduling, multiprocessor machine, rough grammar, rough grammar production rules, pipeline fashion, statically scheduled multiprocessor, decentralized methodology, scheduling, fault tolerance, parallel processing, distributed computation, fault-tolerant computing, fault tolerant computing, concurrent program, grammars, pipeline processing
34	Weirong Jiang, Viktor K. Prasanna	Multi-terabit ip lookup using parallel bidirectional pipelines.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	ip lookup, terabit, pipeline, sram, bidirectional
34	Reuven Bar-Yehuda, Craig Gotsman	Time/Space Tradeoffs for Polygon Mesh Rendering.	ACM Trans. Graph.	1996	DBLP DOI BibTeX RDF	rendering, polygons, graphics pipeline
33	Praveen Jayachandran, Tarek F. Abdelzaher	Delay composition in preemptive and non-preemptive real-time pipelines.	Real Time Syst.	2008	DBLP DOI BibTeX RDF	Pipelined distributed systems, Delay composition, Schedulability, End-to-end delay
33	Montek Singh, Steven M. Nowick	MOUSETRAP: High-Speed Transition-Signaling Asynchronous Pipelines.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
33	Praveen Jayachandran, Tarek F. Abdelzaher	A Delay Composition Theorem for Real-Time Pipelines.	ECRTS	2007	DBLP DOI BibTeX RDF
33	Haitham Akkary, Srikanth T. Srinivasan, Rajendar Koltur, Yogesh Patil, Wael Refaai	Perceptron-Based Branch Confidence Estimation.	HPCA	2004	DBLP DOI BibTeX RDF
33	Christopher W. Milner, Jack W. Davidson	Quick piping: a fast, high-level model for describing processor pipelines.	LCTES-SCOPES	2002	DBLP DOI BibTeX RDF	embedded systems, pipelines, modeling of computer architecture
33	Oswaldo Cadenas, Graham M. Megson	Pipelining Considerations for an FPGA Case.	DSD	2001	DBLP DOI BibTeX RDF
32	Daniel Pak-Kong Lun, Wan-Chi Siu	A Pipeline Design for the Realization of the Prime Factor Algorithm Using the Extended Diagonal Structure.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	pipeline design, prime factor algorithm, input data sequenc, data loading, parallel algorithms, parallel architectures, signal processing, digital signal processing, retrieval, Chinese Remainder Theorem, pipeline architecture, multidimensional array
32	Veljko M. Milutinovic, David A. Fura, Walter A. Helbig	Pipeline Design Tradeoffs in a 32-bit Gallium Arsenide Microprocessor.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	instruction pipeline design, single-chip GaAs microprocessor, application-related parameters, pipelined memory pipeline, III-V semiconductors, performance evaluation, microprocessor chips, instruction sets, 32 bit, GaAs, gallium arsenide
32	Richard G. Cooper	The Distributed Pipeline.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	Array of computers, distributed pipeline (DP), multiple-instruction multiple-data-stream (MIMD) computer, distributed computer, multiprocessor, pipeline, computer network, computer architecture, microprocessor, microcomputer
31	Sherif Ghali	Sense and sidedness in the graphics pipeline via a passage through a separable space.	Vis. Comput.	2009	DBLP DOI BibTeX RDF	Oriented projective geometry, Separability, Projective geometry, Homogeneous coordinates, Graphics pipeline
31	Jarkko Ylipaavalniemi, Jyri Soppela	Arabica: Robust ICA in a Pipeline.	ICA	2009	DBLP DOI BibTeX RDF	pipeline, ICA, bootstrapping, fMRI, Toolbox
31	Álvaro García-Sánchez, Luis Miguel Arreche Bedia, Miguel Ortega-Mier	Combining Simulation and Tabu Search for Oil-derivatives Pipeline Scheduling.	Metaheuristics for Scheduling in Industrial and Manufacturing Applications	2008	DBLP DOI BibTeX RDF	Multi-commodity Pipeline, Real World Instances, Simulation, Scheduling, Tabu Search
31	John Giacomoni, Tipp Moseley, Manish Vachharajani	FastForward for efficient pipeline parallelism: a cache-optimized concurrent lock-free queue.	PPoPP	2008	DBLP DOI BibTeX RDF	fastforward, multiprocessors, multicore, queue, lock-free, linearizability, nonblocking synchronization, pipeline parallel