Search results for "pipelined"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
151	Swapan Kumar Ray	Large-Capacity High-Throughput Low-Cost Pipelined CAM Using Pipelined CTAM.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Content Addressable Memory (CAM), associative store, Associative Memory (AM), pipelined CAM, Content-To-Address Memory (CTAM), pipelined CTAM, Binary Search Processor (BSP), Pipelined Binary Search Processor (PBSP), pipelined binary search, Binary Search Pipeline (BSPL), pipelined search processor, pipelined search engine
76	Swapan Kumar Ray, Sabyasachi Dutta, Abhik Kumar Saha	A Low-Cost Pipelineed Multi-Lingual E-Dictionary Using a Pipelined CTAM.	ICCTA	2007	DBLP DOI BibTeX RDF	Address-To-Content Memory (ATCM), Content-To-Address Memory (CTAM), Pipelined CTAM (PCTAM), Low-Cost PCTAM, Content Addresseble Memory (CAM), Assosiative Memory (AM), Pipelined AM (PAM), Multi-Lingual E-Dictionary (MLeD), Pipelined MLeD (PMLeD), Universal Dictionary Server (UDS)
76	Ram K. Krishnamurthy, Ramalingam Sridhar	A CMOS wave-pipelined image processor for real-time morphology .	ICCD	1995	DBLP DOI BibTeX RDF	CMOS wave-pipelined image processor, real-time morphology, high-speed morphological image processor, wave-pipelined transmission gate logic, two-stage morphological skeleton transform filter, regular pipelined architectures, real-time systems, computational complexity, image processing, latency, pipeline processing, CMOS integrated circuits, hardware complexity
68	Chung-Ta King, Wen-Hwa Chou, Lionel M. Ni	Pipelined Data Parallel Algorithms-I: Concept and Modeling.	IEEE Trans. Parallel Distributed Syst.	1990	DBLP DOI BibTeX RDF	pipelined data-parallel algorithms, pipelined operations, data level partitioning, parallel algorithms, Petri nets, data parallelism
64	Patrick Schaumont, Bart Vanthournout, Ivo Bolsens, Hugo De Man	Synthesis of pipelined DSP accelerators with dynamic scheduling.	ISSS	1995	DBLP DOI BibTeX RDF	DSP algorithms, FFT butterfly accelerator block, application specific DSP accelerators, highly pipelined data paths, pipelined DSP accelerator synthesis, pipelined bit-parallel hardware, silicon, scheduling, parallel architectures, application specific integrated circuits, dynamic scheduling, pipeline processing, circuit CAD, digital signal processing chips, datapath, controller architecture, network synthesis, run-time schedules
62	Steven L. Scott, James R. Goodman	The Impact of Pipelined Channels on k-ary n-Cube Networks.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	pipelined channels, bisection constraints, optimaldimensionality, pipelined-channel networks, switching overhead, performance evaluation, multiprocessor interconnection networks, pipeline processing, cycle time, k-ary n-cube networks, message lengths
58	Leonardo Londero de Oliveira, Cristiano Santos, Daniel Lima Ferrão, Eduardo A. C. da Costa, José Monteiro 0001, João Baptista dos Santos Martins, Sergio Bampi, Ricardo Augusto da Luz Reis	A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
56	Akshay Sharma, Katherine Compton, Carl Ebeling, Scott Hauck	Exploration of pipelined FPGA interconnect structures.	FPGA	2004	DBLP DOI BibTeX RDF	PipeRoute, pipelined FPGA, pipelined interconnect, registered routing, architecture explorations
56	Krishna P. Mikkilineni, Stanley Y. W. Su	An Evaluation of Relational Join Algorithms in a Pipelined Query Processing Environment.	IEEE Trans. Software Eng.	1988	DBLP DOI BibTeX RDF	timing equations, relational join algorithms, pipelined query processing environment, nested block, sort-merge, pipelined sort-merge, performance evaluation, relational databases, relational databases, distributed processing, distributed databases, distributed databases, sorting, database theory, hash, pipeline processing, merging, query execution
55	Matthew Moe, Herman Schmit	Floorplanning of pipelined array modules using sequence pairs.	ISPD	2003	DBLP DOI BibTeX RDF	pipelined array, floorplan, sequence pair
53	Turki F. Al-Somani, Alaaeldin Amin	High performance elliptic curve point operations with pipelined GF(2m) field multiplier.	AICCSA	2008	DBLP DOI BibTeX RDF
53	Pitch Patarasuk, Ahmad Faraj, Xin Yuan 0001	Pipelined broadcast on Ethernet switched clusters.	IPDPS	2006	DBLP DOI BibTeX RDF
51	Michael J. Corinthios	Optimal Parallel and Pipelined Processing Through a New Class of Matrices with Application to Generalized Spectral Analysis.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	general-base matrices, sampling matrices, Poles, algorithm parameters, parallel pipelined processors, memory topology, access uniformity, shuffle complexity, algorithm factorizations, generalized perfect shuffle, Chrestenson generalized Walsh transform, generalized spectral analysis, parallel processing, parallel architectures, computer architecture, pipeline processing, pipelined processing, matrix algebra, pointers, pipelined architecture, zeros, matrices, spans, matrix theory
49	Anne Condon, Amol Deshpande, Lisa Hellerstein, Ning Wu	Algorithms for distributional and adversarial pipelined filter ordering problems.	ACM Trans. Algorithms	2009	DBLP DOI BibTeX RDF	Pipelined filter ordering, flow algorithms, selection ordering, query optimization
49	Panagiotis Manolios, Sudarshan K. Srinivasan	Automatic verification of safety and liveness for pipelined machines using WEB refinement.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	flushing, pipelined machines, verification, refinement, SAT, bisimulation, commitment, liveness, Refinement maps
49	Aggelos Ioannou, Manolis Katevenis	Pipelined heap (priority queue) management for advanced scheduling in high-speed networks.	IEEE/ACM Trans. Netw.	2007	DBLP DOI BibTeX RDF	high-speed network scheduling, pipelined hard-ware heap, synthesizable core, weighted fair queueing, priority queue, weighted round robin
49	Mary D. Brown, Yale N. Patt	Using Internal Redundant Representations and Limited Bypass to Support Pipelined Adders and Register Files.	HPCA	2002	DBLP DOI BibTeX RDF	redundant binary, limited bypass, pipelined register file, signed digit
47	Janardhan H. Satyanarayana, Keshab K. Parhi, Leilei Song, Yun-Nan Chang	Systematic analysis of bounds on power consumption in pipelined and non-pipelined multipliers.	ICCD	1996	DBLP DOI BibTeX RDF	pipelined multipliers, nonpipelined multipliers, Baugh-Wooley multiplier, binary tree multiplier, Wallace tree multiplier, STDs, sub circuits, energy values, cubic dependence, word length, quadratic dependence, digital CMOS circuits, CMOS adder, low power arithmetic units, power consumption, power consumption, switching activity, state transition diagrams
47	Mahmood Ahmadi, Stephan Wong	K-Stage Pipelined Bloom Filter for Packet Classification.	CSE (2)	2009	DBLP DOI BibTeX RDF
47	Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen	Wave-pipelined on-chip global interconnect.	ASP-DAC	2005	DBLP DOI BibTeX RDF
47	Mei Yang, Si-Qing Zheng	Pipelined Maximal Size Matching Scheduling Algorithms for CIOQ Switches..	ISCC	2003	DBLP DOI BibTeX RDF
47	Kenji Imasaki, Hong Nguyen, Sivarama P. Dandamudi	Performance Comparison of Pipelined Hash Joins on Workstation Clusters.	HiPC	2002	DBLP DOI BibTeX RDF
47	Shanq-Jang Ruan, Edwin Naroska, Chia-Lin Ho, Feipei Lai	Power Analysis of Bipartition and Dual-Encoding Architecture for Pipelined Circuits.	ICCD	2002	DBLP DOI BibTeX RDF
47	Sharad Malik, Kanwar Jit Singh, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Performance optimization of pipelined logic circuits using peripheral retiming and resynthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
44	Juha Plosila, Kaisa Sere	Action Systems in Pipelined Processor Design.	ASYNC	1997	DBLP DOI BibTeX RDF	pipelined processor design, asynchronous pipelined microprocessors, hazard situations, verifying refinement steps, circuit implementation, speed-independent techniques, refinement calculus, refinement calculus, action systems
44	Asger Munk Nielsen, David W. Matula, Chung Nan Lyu, Guy Even	Pipelined Packet-Forwarding Floating Point: II. An Adder.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	pipelined packet forwarding floating point, floating point addition algorithm, adder pipeline design, packet forwarding pipeline paradigm, data hazards, deeply pipelined floating point pipelines, four stage execution phase pipeline, short clock period, fifteen logic levels, addition algorithm, standard binary floating point format, standard IEEE 754 rounded result, two cycle latency, cooperating multiplier pipeline, packet forwarding operand, IEEE 754 binary floating point compatibility, pipeline arithmetic
44	David W. Matula, Asger Munk Nielsen	Pipelined Packet-Forwarding Floating Point: I. Foundations and a Rounder.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	pipelined packet forwarding floating point, packet forwarding floating point format, rounder design, packet forwarding format, standard binary IEEE 754 floating point format, multiplication algorithms, ALU pipeline paradigm, data hazards, pipelined floating point operations, execution phases, multiplier packet forwarding pipelines, execution phase, logic levels, multiplier pipelines, forwarding pipelines, IEEE 754 binary floating point compatibility, pipeline arithmetic, data dependent operations
44	Shobana Balakrishnan, Füsun Özgüner	Providing message delivery guarantees in pipelined flit-buffered multiprocessor networks.	IEEE Real Time Technology and Applications Symposium	1996	DBLP DOI BibTeX RDF	message delivery guarantees, pipelined flit-buffered multiprocessor networks, periodic messages, multiple virtual channels, unbounded priority inversion, global priority order, flow control mechanism, preemptive pipelined circuit switching, preemption history stack, flit level simulations, feasible messages, real-time systems, parallel processing, message passing, wormhole routing, distributed memory systems, pipeline processing, real-time applications, distributed memory multiprocessors
44	Ravi Ganesan, Shlomo Weiss	Scalar Memory References in Pipelined Multiprocessors: A Performance Study.	IEEE Trans. Software Eng.	1992	DBLP DOI BibTeX RDF	scalar memory references, pipelined multiprocessors, high memory bandwidth, memory cycle, processor cycle time, bank reservation time, bank busy time, performance evaluation, probability, Markov chain, Markov processes, parallel machines, Markov models, storage management, simulation results, pipeline processing, state space, transition probabilities, pipelined computers, memory bank
43	Gang Zhou, Harald Michalik, László Hinsenkamp	Improving Throughput of AES-GCM with Pipelined Karatsuba Multipliers on FPGAs.	ARC	2009	DBLP DOI BibTeX RDF	AES-GCM, pipelined Karatsuba multiplier, FPGAs, finite field arithmetic
43	Kun Suk Kim, Sartaj Sahni	Efficient Construction of Pipelined Multibit-Trie Router-Tables.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	multibit trie, pipelined router-table, dynamic programming, Packet routing, longest matching-prefix, controlled prefix expansion
43	Panagiotis Manolios, Sudarshan K. Srinivasan	A Framework for Verifying Bit-Level Pipelined Machines Based on Automated Deduction and Decision Procedures.	J. Autom. Reason.	2006	DBLP DOI BibTeX RDF	pipelined machines, bit-level, verification, refinement, automated reasoning, ACL2
43	Samuel Rodríguez, Bruce L. Jacob	Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm).	ISLPED	2006	DBLP DOI BibTeX RDF	nanometer design, pipelined caches, cache design
43	Abir Jaafar Hussain, Adam Knowles, Paulo J. G. Lisboa, Wael El-Deredy, Dhiya Al-Jumeily	Polynomial Pipelined Neural Network and Its Application to Financial Time Series Prediction.	Australian Conference on Artificial Intelligence	2006	DBLP DOI BibTeX RDF	Polynomial neural network, pipelined network, exchange rate time series and financial time series prediction
43	Fulvio Corno, Ernesto Sánchez 0001, Matteo Sonza Reorda, Giovanni Squillero	Code Generation for Functional Validation of Pipelined Microprocessors.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	pipelined micro processors, evolutionary algorithms, functional validation, automatic test program generation
43	Shen-Fu Hsiao, Jian-Ming Tseng	Parallel, Pipelined and Folded Architectures for Computation of 1-D and 2-D DCT in Image and Video Codec.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	VLSI, image compression, discrete cosine transform, fast algorithm, pipelined architectures
43	Chung-Ta King, Wen-Hwa Chou, Lionel M. Ni	Pipelined Data Parallel Algorithms-II: Design.	IEEE Trans. Parallel Distributed Syst.	1990	DBLP DOI BibTeX RDF	loop-carried dependencies, pipelined execution patterns, dependence relationships, performance evaluation, parallel algorithms, parallel program, parallelism, partitioning, grouping, nested loop, sequential algorithm, data parallel algorithms
41	V. Vireen, N. Venugopalachary, G. Seetharaman, B. Venkataramani	Built in Self Test Based Design of Wave-Pipelined Circuits in ASICs.	VLSI Design	2009	DBLP DOI BibTeX RDF
41	Wencheng Lu, Sartaj Sahni	Packet Classification Using Space-Efficient Pipelined Multibit Tries.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	fixed-stride tries, variable-stride tries, two-dimensional tries, dynamic programming, Packet classification, longest matching prefix, controlled prefix expansion
41	Akashi Satoh, Takeshi Sugawara 0001, Takafumi Aoki	High-Speed Pipelined Hardware Architecture for Galois Counter Mode.	ISC	2007	DBLP DOI BibTeX RDF
41	Allan Carroll, Carl Ebeling	Reducing the Space Complexity of Pipelined Routing Using Modified Range Encoding.	FPL	2006	DBLP DOI BibTeX RDF
41	Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara	Instruction-based delay fault self-testing of pipelined processor cores.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
41	Hanjun Jiang, Haibo Fei, Degang Chen 0001, Randall L. Geiger	A background digital self-calibration scheme for pipelined ADCs based on transfer curve estimation.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
41	Eduardo A. C. da Costa, Sergio Bampi, José Monteiro 0001	A New Pipelined Array Architecture for Signed Multiplication.	SBCCI	2003	DBLP DOI BibTeX RDF
41	Hong-Shin Jun, Sun-Young Hwang	Design of a pipelined datapath synthesis system for digital signal processing.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
38	Malay Kumar Pakhira, Rajat K. De	A hardware pipeline for function optimization using genetic algorithms.	GECCO	2005	DBLP DOI BibTeX RDF	hardware pipeline, pipelined GA, stochastic selection, genetic algorithms, function optimization
38	Akshay Sharma, Carl Ebeling, Scott Hauck	PipeRoute: a pipelining-aware router for FPGAs.	FPGA	2003	DBLP DOI BibTeX RDF	BFS, PipeRoute, retimed circuits, routing, pipelining, minimum spanning tree, retiming, pipelined circuits
36	Yi-Hua E. Yang, Viktor K. Prasanna	High throughput and large capacity pipelined dynamic search tree on FPGA.	FPGA	2010	DBLP DOI BibTeX RDF	2-3 tree, in-place update, ip forwarding, pipelined tree, b-tree, dynamic update, incremental update, openflow
36	Anne Condon, Amol Deshpande, Lisa Hellerstein, Ning Wu	Flow algorithms for two pipelined filter ordering problems.	PODS	2006	DBLP DOI BibTeX RDF	flow algorithms, pipelined filter ordering, selection ordering, query optimization
36	Tadaaki Tanimoto, Seiji Yamaguchi, Akio Nakata, Teruo Higashino	A real time budgeting method for module-level-pipelined bus based system using bus scenarios.	DAC	2006	DBLP DOI BibTeX RDF	bus based systems, cycle budgeting, real-time systems, pipelined processing, multimedia processing
36	Hua Li, Jianzhou Li	A High Performance Sub-Pipelined Architecture for AES.	ICCD	2005	DBLP DOI BibTeX RDF	sub-pipelined architecture, FPGA, cryptography, AES
36	Hesam Amir Aslanzadeh, Saeid Mehrmanesh, Mohammad B. Vahidfar, Amin Quasem Safarian, Reza Lotfi	A 1-V 1-mW high-speed class AB operational amplifier for high-speed low power pipelined A/D converters using "Slew Boost" technique.	ISLPED	2003	DBLP DOI BibTeX RDF	CMOS analog circuit, Slew Boost technique, class AB, low power, high speed, operational amplifier, pipelined analog to digital converter, ultra low voltage
36	Maria Athanasaki, Aristidis Sotiropoulos, Georgios Tsoukalas, Nectarios Koziris	Pipelined scheduling of tiled nested loops onto clusters of SMPs using memory mapped network interfaces.	SC	2002	DBLP DOI BibTeX RDF	memory mapped network interfaces, tile grouping, SMPs, DMA, pipelined schedules, communication overlapping
36	Eduardo J. Peralías, Adoración Rueda, José Luis Huertas	New BIST Schemes for Structural Testing of Pipelined Analog to Digital Converters.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	mixed-signal IC test, testable ADC, BIST, design for test, pipelined analog to digital converters
36	Chichyang Chen, Rui-Lin Chen, Chih-Huan Yang	Pipelined Computation of Very Large Word-Length LNS Addition/Subtraction with Polynomial Hardware Cost.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Logarithmic arithmetic, digit on-line algorithms, exponentials, pipelined architecture, logarithmic number system, logarithms
36	Michele Favalli, Cecilia Metra	Bridging Faults in Pipelined Circuits.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	fault modeling, bridging faults, CMOS circuits, pipelined circuits
36	Xijun Zhang, Chunming Qiao	Pipelined Transmission Scheduling in All-Optical TDM/WDM Rings.	ICCCN	1997	DBLP DOI BibTeX RDF	TDM/WDM, AAPC, Pipelined transmissions, Scheduling, Ring
36	Krishna P. Mikkilineni, Yuan-Chieh Chow, Stanley Y. W. Su	Petri-Net-Based Modeling and Evaluation of Pipelined Processing of Concurrent Database Queries.	IEEE Trans. Software Eng.	1988	DBLP DOI BibTeX RDF	concurrent database queries, integrated data network, intermediate data sharing, Petri nets, query processing, distributed databases, distributed databases, computer networks, program testing, digital simulation, pipelined processing, pipeline processing, Petri-net model, event-driven programming
36	Ming Su, Lili Zhou, C.-J. Richard Shi	Maximizing the throughput-area efficiency of fully-parallel low-density parity-check decoding with C-slow retiming and asynchronous deep pipelining.	ICCD	2007	DBLP DOI BibTeX RDF
36	Akshay Sharma, Carl Ebeling, Scott Hauck	PipeRoute: a pipelining-aware router for reconfigurable architectures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
36	J. Living, M. Moniri, S. B. Tennakoon	Efficient Recursive Digital Filters using Combined Look-Ahead Denominator Distribution and Numerator Decomposition.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	IIR digital filters, iteration bound, look ahead pipelining, resource minimisation
35	Marco Branca, Lorenzo Camerini, Fabrizio Ferrandi, Pier Luca Lanzi, Christian Pilato, Donatella Sciuto, Antonino Tumeo	Evolutionary algorithms for the mapping of pipelined applications onto heterogeneous embedded systems.	GECCO	2009	DBLP DOI BibTeX RDF	boa, sa, ts, ga, fpga, mapping, pipelining
35	Prabhat Mishra 0001, Nikil D. Dutt	Specification-driven directed test generation for validation of pipelined processors.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	Model checking, test generation, functional validation
35	Alireza Ejlali, Bashir M. Al-Hashimi	SEU-Hardened Energy Recovery Pipelined Interconnects for On-Chip Networks.	NOCS	2008	DBLP DOI BibTeX RDF
35	Erfu Yang, Ahmet T. Erdogan, Tughrul Arslan, Nick Barton	System-Level Modeling and Multi-objective Evolutionary Design of Pipelined FFT Processors for Wireless OFDM Receivers.	ICES	2007	DBLP DOI BibTeX RDF
35	Wei-Feng He, Meng-Lian Zhao, Chi-Ying Tsui, Zhi-Gang Mao	A Scalable Frame-Level Pipelined Architecture for FSBM Motion Estimation.	VLSI Design	2007	DBLP DOI BibTeX RDF
35	Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara	Instruction-Based Self-Testing of Delay Faults in Pipelined Processors.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
35	Wencheng Lu, Sartaj Sahni	Packet Classification Using Pipelined Two-Dimensional Multibit Tries.	ISCC	2006	DBLP DOI BibTeX RDF	fixed-stride tries, variable-stride tries, two-dimensional tries, dynamic programming, Packet classification, longest matching prefix, controlled prefix expansion
35	Wencheng Lu, Sartaj Sahni	Packet Forwarding Using Pipelined Multibit Tries.	ISCC	2006	DBLP DOI BibTeX RDF	fixed-stride tries, variable-stride tries, dynamic programming, Packet classification, longest matching prefix, controlled prefix expansion
35	Mohammad Taherzadeh-Sani, Anas A. Hamoui	Digital background calibration of interstage-gain and capacitor-mismatch errors in pipelined ADCs.	ISCAS	2006	DBLP DOI BibTeX RDF
35	Mohammad Taherzadeh-Sani, Anas A. Hamoui	Analysis of dynamic element matching (DEM) in pipelined ADCs.	ISCAS	2006	DBLP DOI BibTeX RDF
35	Miroslav N. Velev	Using Abstraction for Efficient Formal Verification of Pipelined Processors with Value Prediction.	ISQED	2006	DBLP DOI BibTeX RDF
35	Gopalakrishnan Lakshminarayanan, B. Venkataramani	Optimization Techniques for FPGA-Based Wave-Pipelined DSP Blocks.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
35	Prabhat Mishra 0001, Heon-Mo Koo, Zhuo Huang	Language-driven Validation of Pipelined Processors using Satisfiability Solvers.	MTV	2005	DBLP DOI BibTeX RDF
35	Prabhat Mishra 0001, Nikil D. Dutt	Functional Coverage Driven Test Generation for Validation of Pipelined Processors.	DATE	2005	DBLP DOI BibTeX RDF
35	Gyu Sang Choi, Jin-Ha Kim, Deniz Ersoz, Chita R. Das	A multi-threaded PIPELINED Web server architecture for SMP/SoC machines.	WWW	2005	DBLP DOI BibTeX RDF	asynchronous multi-process event-driven, single event-driven process, symmetric multi-processor, system-on-chip, multi-thread, multi-process
35	Kamesh Munagala, Shivnath Babu, Rajeev Motwani 0001, Jennifer Widom	The Pipelined Set Cover Problem.	ICDT	2005	DBLP DOI BibTeX RDF
35	Chih-Haur Huang, Kuen-Jong Lee, Soon-Jyh Chang	A Low-Cost Diagnosis Methodology for Pipelined A/D Converters.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
35	Masaru Takesue	Software Queue-Based Algorithms for Pipelined Synchronization on Multiprocessors.	ICPP Workshops	2003	DBLP DOI BibTeX RDF	queue-based locks, algorithms, synchronization, Multiprocessors, pipelining
35	Karam S. Chatha, Ranga Vemuri	Hardware-software partitioning and pipelined scheduling of transformative applications.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
35	Byung-Do Yang, Lee-Sup Kim, Hyun-Kyu Yu	A high speed direct digital frequency synthesizer using a low power pipelined parallel accumulator.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
35	Sridhar Rajagopal, Joseph R. Cavallaro	A bit-streaming, pipelined multiuser detector for wireless communication receivers.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
35	Shanq-Jang Ruan, Rung-Ji Shang, Feipei Lai, Shyh-Jong Chen, Xian-Jun Huang	A bipartition-codec architecture to reduce power in pipelined circuits.	ICCAD	1999	DBLP DOI BibTeX RDF
35	Javier Valls, Trini Sansaloni, Marcos Martínez-Peiró, Eduardo I. Boemo	Fast FPGA-based pipelined digit-serial/parallel multipliers.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
35	Sissades Tongsima, Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Nelson L. Passos	Reducing Data Hazards on Multi-pipelined DSP Architecture with Loop Scheduling.	J. VLSI Signal Process.	1998	DBLP DOI BibTeX RDF
35	Philippe Pucheral, Jean-Marc Thévenin	Pipelined Query Processing in the DBGraph Storage Model.	EDBT	1992	DBLP DOI BibTeX RDF
35	Mitsuhisa Sato, Shuichi Ichikawa, Eiichi Goto	Multiple instruction streams in a highly pipelined processor.	SPDP	1990	DBLP DOI BibTeX RDF
35	Chung-Ta King, Wen-Hwa Chou, Lionel M. Ni	Pipelined data parallel algorithms - concept and modeling.	ICS	1988	DBLP DOI BibTeX RDF
33	Jae-Tack Yoo, Erik Brunvand, Kent F. Smith	Automatic rapid prototyping of semi-custom VLSI circuits using Actel FPGAs.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	automatic rapid prototyping, semicustom VLSI circuits, Actel FPGAs, cell-matrix based environment, synchronous pipelined version, asynchronous pipelined version, field programmable gate arrays, field programmable gate arrays, VLSI, logic CAD, integrated circuit design, CMOS logic circuits, circuit CAD, array multiplier, CMOS IC
32	Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi	Instruction-level test methodology for CPU core self-testing.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	CPU core testing, Instruction level testing, test instruction set, BIST, pipelined processor, software-based self testing
32	James K. Huggins, David Van Campenhout	Specification and verification of pipelining in the ARM2 RISC microprocessor.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	ARM processor, formal verification, pipelining, abstract state machines, design verification, pipelined processors
30	Frank Sill, Davies W. de Lima Monteiro	Pipelined successive approximation conversion (PSAC) with error correction for a CMOS ophthalmic sensor.	SBCCI	2009	DBLP DOI BibTeX RDF	pipelined SAC, error correction, ADC
30	Fuqiang Xue, Lindong Ge, Bin Wang	Pipelined Genetic Algorithm Initialized RAN Based RBF Modulation Classifier.	ISNN (2)	2009	DBLP DOI BibTeX RDF	Resources allocation network, Pipelined genetic algorithm, RBF modulation classifier, Initialization
30	Horng-Ren Tsai	Parallel Algorithms for the Weighted Distance Transform on Linear Arrays with a Reconfigurable Pipelined Bus System.	ICA3PP	2009	DBLP DOI BibTeX RDF	linear array with a reconfigurable pipelined bus system, parallel algorithms, image processing, Distance transform
30	Francisco J. Jaime, Julio Villalba, Javier Hormigo, Emilio L. Zapata	Pipelined Architecture for Additive Range Reduction.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	range reduction, floating-point, pipelined architecture, modular arithmetic, redundant arithmetic
30	Martino Sykora, Giovanni Agosta, Cristina Silvano	Dynamic configuration of application-specific implicit instructions for embedded pipelined processors.	SAC	2008	DBLP DOI BibTeX RDF	implicit issue, reconfiguration, pipelined architecture
30	Lech Józwiak, Alexander Douglas	Hardware Synthesis for Reconfigurable Heterogeneous Pipelined Accelerators.	ITNG	2008	DBLP DOI BibTeX RDF	re-configurable computing, heterogeneous pipelined accelerators, hardware synthesis, EDA-tool
30	Kenneth Eguro, Scott Hauck	Enhancing timing-driven FPGA placement for pipelined netlists.	DAC	2008	DBLP DOI BibTeX RDF	timing-driven, FPGA, simulated annealing, pipelined, placement
30	Cheng-Yeh Wang, Chih-Bin Kuo, Jing-Yang Jou	Hybrid Wordlength Optimization Methods of Pipelined FFT Processors.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Pipelined FFT processor, Signal-to-quantization noise ratio, Wordlength optimization, Simulation-based analysis, Upper-bound wordlength, Lowerbound wordlength, Statistical analysis
30	Maria Athanasaki, Aristidis Sotiropoulos, Georgios Tsoukalas, Nectarios Koziris, Panayotis Tsanakas	Hyperplane Grouping and Pipelined Schedules: How to Execute Tiled Loops Fast on Clusters of SMPs.	J. Supercomput.	2005	DBLP DOI BibTeX RDF	tile grouping, loop tiling, hyperplanes, pipelined schedules, supernodes