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Searching for phrase power-gating (changed automatically) with no syntactic query expansion in all metadata.

Publication years (Num. hits)
2001-2004 (18) 2005 (15) 2006 (21) 2007 (34) 2008 (47) 2009 (37) 2010 (28) 2011 (43) 2012 (41) 2013 (25) 2014 (35) 2015 (31) 2016 (37) 2017 (20) 2018 (17) 2019-2020 (25) 2021-2022 (22) 2023-2024 (16)
Publication types (Num. hits)
article(171) incollection(1) inproceedings(337) phdthesis(3)
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Results
Found 512 publication records. Showing 512 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
131Fei Li 0003, Lei He 0001 Maximum current estimation considering power gating. Search on Bibsonomy ISPD The full citation details ... 2001 DBLP  DOI  BibTeX  RDF low-power design, ATPG, power estimation, power gating
113Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee Compilation for compact power-gating controls. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Compilers for low power, balanced scheduling, power-gating mechanisms, data-flow analysis, leakage-power reduction
111Chung-Yu Chang, Wei-Bin Yang, Ching-Ji Huang, Cheng-Hsing Chien New Power Gating Structure with Low Voltage Fluctuations by Bulk Controller in Transition Mode. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
108Anja Niedermeier, Kjetil Svarstad, Frank Bouwens, Jos Hulzink, Jos Huisken The challenges of implementing fine-grained power gating. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2010 DBLP  DOI  BibTeX  RDF leakage power minimization, analysis, power management, register-transfer-level, power modeling, power gating
102Ashoka Visweswara Sathanur, Andrea Calimera, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
100Harmander Singh, Kanak Agarwal, Dennis Sylvester, Kevin J. Nowka Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
98Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee A sink-n-hoist framework for leakage power reduction. Search on Bibsonomy EMSOFT The full citation details ... 2005 DBLP  DOI  BibTeX  RDF balanced scheduling, compilers for low power, power-gating mechanisms, data-flow analysis, leakage power reduction
97Zhigang Hu, Alper Buyuktosunoglu, Viji Srinivasan, Victor V. Zyuban, Hans M. Jacobson, Pradip Bose Microarchitectural techniques for power gating of execution units. Search on Bibsonomy ISLPED The full citation details ... 2004 DBLP  DOI  BibTeX  RDF execution units, low power, microarchitecture, power-gating
96Christophe Giacomotto, Mandeep Singh, Milena Vratonjic, Vojin G. Oklobdzija Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements. Search on Bibsonomy PATMOS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Clocked storage elements, VLSI, power consumption, flip-flops, voltage scaling, clock gating, power gating, energy optimization, MTCMOS, circuit optimization, circuit tuning, circuit analysis
94Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel, Kevin Stawiasz Experimental measurement of a novel power gating structure with intermediate power saving mode. Search on Bibsonomy ISLPED The full citation details ... 2004 DBLP  DOI  BibTeX  RDF system-on-a-chip (SOC) design, wake-up latency, clock gating, power gating, inductive noise, ground bounce
85Jun Seomun, Insup Shin, Youngsoo Shin Synthesis and implementation of active mode power gating circuits. Search on Bibsonomy DAC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF active leakage, active-mode power gating, low power
80Hailin Jiang, Malgorzata Marek-Sadowska Power-Gating Aware Floorplanning. Search on Bibsonomy ISQED The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
80Hailin Jiang, Malgorzata Marek-Sadowska, Sani R. Nassif Benefits and Costs of Power-Gating Technique. Search on Bibsonomy ICCD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
79Enrico Macii, Letícia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Massimo Poncino Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits. Search on Bibsonomy DSD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
78Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel Understanding and minimizing ground bounce during mode transition of power gating structures. Search on Bibsonomy ISLPED The full citation details ... 2003 DBLP  DOI  BibTeX  RDF system-on-a-chip (SOC) design, wake-up latency, clock gating, power gating, inductive noise, ground bounce
77Aida Todri, Malgorzata Marek-Sadowska, Shih-Chieh Chang Analysis and optimization of power-gated ICs with multiple power gating configurations. Search on Bibsonomy ICCAD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
72Deepa Kannan, Aviral Shrivastava, Vipin Mohan, Sarvesh Bhardwaj, Sarma B. K. Vrudhula Temperature and Process Variations Aware Power Gating of Functional Units. Search on Bibsonomy VLSI Design The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
70Hailin Jiang, Malgorzata Marek-Sadowska Power gating scheduling for power/ground noise reduction. Search on Bibsonomy DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF scheduling, power gating, power supply noise
69Yi-Ping You, Chingren Lee, Jenq Kuen Lee Compilers for leakage power reduction. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Compilers for low power, power-gating mechanisms, leakage-power reduction
69Nainesh Agarwal, Nikitas J. Dimopoulos Automated Power Gating of Registers Using CoDeL and FSM Branch Prediction. Search on Bibsonomy SAMOS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
66Philip Teichmann, Jürgen Fischer, Stephan Henzler, Ettore Amirante, Doris Schmitt-Landsiedel Power-Clock Gating in Adiabatic Logic Circuits. Search on Bibsonomy PATMOS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
66Andrea Calimera, Enrico Macii, Massimo Poncino NBTI-aware power gating for concurrent leakage and aging optimization. Search on Bibsonomy ISLPED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF aging, leakage, power-gating, nbti
66Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino A Scalable Algorithmic Framework for Row-Based Power-Gating. Search on Bibsonomy DATE The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
64Hyung-Ock Kim, Youngsoo Shin, Hyuk Kim, Iksoo Eo Physical design methodology of power gating circuits for standard-cell-based design. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF low power, leakage current, power gating
64Jungseob Lee, Nam Sung Kim Optimizing throughput of power- and thermal-constrained multicore processors using DVFS and per-core power-gating. Search on Bibsonomy DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF multicore processor, DVFS, power gating
63Seungwhun Paik, Youngsoo Shin Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements. Search on Bibsonomy DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF sleep vector, zigzag power gating, low power, leakage current, standard-cell
63Liangpeng Guo, Yici Cai, Qiang Zhou 0001, Le Kang, Xianlong Hong A novel performance driven power gating based on distributed sleep transistor network. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2008 DBLP  DOI  BibTeX  RDF physical design, power-gating, sleep transistors
59Aida Todri, Shih-Chieh Chang, Malgorzata Marek-Sadowska Electromigration and voltage drop aware power grid optimization for power gated ICs. Search on Bibsonomy ISLPED The full citation details ... 2007 DBLP  DOI  BibTeX  RDF power supply grid, power gating, electromigration
56Hsiang-Hui Huang, Ching-Hwa Cheng Using Clock-Vdd to Test and Diagnose the Power-Switch in Power-Gating Circuit. Search on Bibsonomy VTS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
56Yan Lin 0001, Fei Li 0003, Lei He 0001 Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
56Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF gate leakage current, nanometer-scale CMOS circuits, supply switching, ground collapse, standard-cell elements, 45 nm, 65 nm, power gating, subthreshold leakage current, 90 nm
55Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating. Search on Bibsonomy PATMOS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
54Magnus Själander, Mindaugas Drazdziulis, Per Larsson-Edefors, Henrik Eriksson A low-leakage twin-precision multiplier using reconfigurable power gating. Search on Bibsonomy ISCAS (2) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
53Anita Lungu, Pradip Bose, Alper Buyuktosunoglu, Daniel J. Sorin Dynamic power gating with quality guarantees. Search on Bibsonomy ISLPED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF execution units, low power, power management, microarchitecture, power gating
53Juan Chen 0001, Yong Dong, Huizhan Yi, Xuejun Yang Power Consumption Analysis of Embedded Multimedia Application. Search on Bibsonomy ICESS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
53Charbel J. Akl, Rafic A. Ayoubi, Magdy A. Bayoumi An effective staggered-phase damping technique for suppressing power-gating resonance noise during mode transition. Search on Bibsonomy ISQED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
53Ku He, Rong Luo, Yu Wang 0002 A power gating scheme for ground bounce reduction during mode transition. Search on Bibsonomy ICCD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
53Changbo Long, Jinjun Xiong, Yongpan Liu Techniques of Power-gating to Kill Sub-Threshold Leakage. Search on Bibsonomy APCCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
52Rahul Singh, AhReum Kim, SoYoung Kim, Suhwan Kim A three-step power-gating turn-on technique for controlling ground bounce noise. Search on Bibsonomy ISLPED The full citation details ... 2010 DBLP  DOI  BibTeX  RDF mode transition, system-on-a-chip (SOC) design, power-gating, inductive noise, ground bounce
52De-Shiuan Chiou, Shih-Hsin Chen, Shih-Chieh Chang, Chingwei Yeh Timing driven power gating. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF leakage current, power gating, IR drop
51Mototsugu Hamada, Takeshi Kitahara, Naoyuki Kawabe, Hironori Sato, Tsuyoshi Nishikawa, Takayoshi Shimazawa, Takahiro Yamashita, Hiroyuki Hara, Yukihito Oowaki An automated runtime power-gating scheme. Search on Bibsonomy ICCD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
51Hyung-Ock Kim, Youngsoo Shin Analysis and optimization of gate leakage current of power gating circuits. Search on Bibsonomy ASP-DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
50Seungwhun Paik, Sangmin Kim, Youngsoo Shin Wakeup synthesis and its buffered tree construction for power gating circuit designs. Search on Bibsonomy ISLPED The full citation details ... 2010 DBLP  DOI  BibTeX  RDF wakeup synthesis, leakage, power gating
50Shih-Hsu Huang, Chun-Hua Cheng Timing driven power gating in high-level synthesis. Search on Bibsonomy ASP-DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
50Ehsan Pakbaznia, Massoud Pedram Design and application of multimodal power gating structures. Search on Bibsonomy ISQED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
50Kanak Agarwal, Kevin J. Nowka, Harmander Deogun, Dennis Sylvester Power Gating with Multiple Sleep Modes. Search on Bibsonomy ISQED The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
49Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino Optimal sleep transistor synthesis under timing and area constraints. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2008 DBLP  DOI  BibTeX  RDF row-based, clustering, leakage power, power-gating, standard cell, sleep transistor
49Xiaotao Chang, Mingming Zhang, Ge Zhang 0007, Zhimin Zhang, Jun Wang Adaptive Clock Gating Technique for Low Power IP Core in SoC Design. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
48Houman Homayoun, Ted H. Szymanski Reducing the Instruction Queue Leakage Power in Superscalar Processors. Search on Bibsonomy CCECE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
48Masud H. Chowdhury, Juliana Gjanci, Pervez Khaled Innovative power gating for leakage reduction. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
48Michael D. Powell, Arijit Biswas, Joel S. Emer, Shubhendu S. Mukherjee, Basit R. Sheikh, Shrirang M. Yardi CAMP: A technique to estimate per-structure power at run-time using a few simple parameters. Search on Bibsonomy HPCA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
48Anmol Mathur, Qi Wang Power Reduction Techniques and Flows at RTL and System Level. Search on Bibsonomy VLSI Design The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
46Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi Supply Switching With Ground Collapse: Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
45Sven Rosinger, Domenik Helms, Wolfgang Nebel RTL Power Modeling and Estimation of Sleep Transistor Based Power Gating. Search on Bibsonomy PATMOS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
44Yi-Ping You, Chingren Lee, Jenq Kuen Lee Compiler Analysis and Supports for Leakage Power Reduction on Microprocessors. Search on Bibsonomy LCPC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
42Youngsoo Shin, Hyung-Ock Kim Cell-Based Semicustom Design of Zigzag Power Gating Circuits. Search on Bibsonomy ISQED The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
41Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks. Search on Bibsonomy NOCS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF low power, Network-on-Chip, virtual channels, NoC, DVFS, power gating
40Nainesh Agarwal, Nikitas J. Dimopoulos Towards Automated Power Gating of Registers using CoDeL. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
40Mindaugas Drazdziulis, Per Larsson-Edefors, Lars J. Svensson Overdrive Power-Gating Techniques for Total Power Minimization. Search on Bibsonomy ISVLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
39Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs. Search on Bibsonomy NOCS The full citation details ... 2010 DBLP  DOI  BibTeX  RDF low power, Network-on-Chip, router, power gating
39Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino Timing-driven row-based power gating. Search on Bibsonomy ISLPED The full citation details ... 2007 DBLP  DOI  BibTeX  RDF row-based, clustering, leakage power, power-gating, standard cell, sleep transistor
39Goran Panic, Daniel Dietterle, Zoran Stamenkovic Architecture of a Power-Gated Wireless Sensor Node. Search on Bibsonomy DSD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
39Soumyaroop Roy, Srinivas Katkoori, Nagarajan Ranganathan A Compiler Based Leakage Reduction Technique by Power-Gating Functional Units in Embedded Microprocessors. Search on Bibsonomy VLSI Design The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
38Ahmed Youssef, Mohab Anis, Mohamed I. Elmasry A Comparative Study Between Static and Dynamic Sleep Signal Generation Techniques for Leakage Tolerant Designs. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
38Po-Tsang Huang, Shu-Wei Chang, Wen-Yen Liu, Wei Hwang "Green" micro-architecture and circuit co-design for ternary content addressable memory. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
38Jianping Hu, Hong Li, Yangbo Wu Low-Power Register File Based on Adiabatic Logic Circuits. Search on Bibsonomy PATMOS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
38Harmander Deogun, Dennis Sylvester, Kevin J. Nowka Fine grained multi-threshold CMOS for enhanced leakage reduction. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
37Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hsien-Hsin S. Lee A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design. Search on Bibsonomy MICRO The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
37Fei Li 0003, Yan Lin 0001, Lei He 0001 Vdd programmability to reduce FPGA interconnect power. Search on Bibsonomy ICCAD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
37Weiping Liao, Joseph M. Basile, Lei He 0001 Leakage power modeling and reduction with data retention. Search on Bibsonomy ICCAD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
37Wei-Chih Hsieh, Wei Hwang In-situ self-aware adaptive power control system with multi-mode power gating network. Search on Bibsonomy SoCC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
37Debanjali Nath, Priyanka Choudhury, Sambhu Nath Pradhan Hybrid Approach of Within-Clock Power Gating and Normal Power Gating to Reduce Power. Search on Bibsonomy J. Circuits Syst. Comput. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
36Enric Musoll A Thermal-Friendly Load-Balancing Technique for Multi-Core Processors. Search on Bibsonomy ISQED The full citation details ... 2008 DBLP  DOI  BibTeX  RDF low power, hot spots, power gating, Multi-core architecture
36Yung-Chia Lin, Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee, Wei-Kuan Shih, TingTing Hwang Energy-aware scheduling and simulation methodologies for parallel security processors with multiple voltage domains. Search on Bibsonomy J. Supercomput. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Scheduling, Parallel processing, Power management, Dynamic voltage scaling, Power gating, Security processor
36Kaijian Shi, David Howard Challenges in sleep transistor design and implementation in low-power designs. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF methodology, low-power design, power gating, sleep transistor
36Cindy Eisner, Amir Nahir, Karen Yorav Functional Verification of Power Gated Designs by Compositional Reasoning. Search on Bibsonomy CAV The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
35Kimiyoshi Usami, Toshiaki Shirai, Tatsunori Hashida, Hiroki Masuda, Seidai Takeda, Mitsutaka Nakata, Naomi Seki, Hideharu Amano, Mitaro Namiki, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression. Search on Bibsonomy VLSI Design The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
35Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Daihan Wang Run-time power gating of on-chip routers using look-ahead routing. Search on Bibsonomy ASP-DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
35Ehsan Pakbaznia, Farzan Fallah, Massoud Pedram Charge Recycling in Power-Gated CMOS Circuits. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
35Weiping Liao, Joseph M. Basile, Lei He 0001 Microarchitecture-level leakage reduction with data retention. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
34Shota Ishihara, Masanori Hariyama, Michitaka Kameyama A low-power FPGA based on autonomous fine-grain power-gating. Search on Bibsonomy ASP-DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
34Songyao Tan, Yue Yin, Hanjun Jiang, Zhihua Wang 0001 A 0.7-V Clock-gating Cell with Power Gating Technology and 1.56-pA Sleep Power. Search on Bibsonomy ICTA The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
34Amit Ranjan Trivedi, Wen Yueh, Saibal Mukhopadhyay In Situ Power Gating Efficiency Learner for Fine-Grained Self-Adaptive Power Gating. Search on Bibsonomy IEEE Trans. Circuits Syst. II Express Briefs The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
34Debanjali Nath, Priyanka Choudhury, Sambhu Nath Pradhan Power Reduction by Integrated Within_Clock_Power Gating and Power Gating (WCPG_in_PG). Search on Bibsonomy VDAT The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
34Li Li, Ken Choi, Haiqing Nan Effective algorithm for integrating clock gating and power gating to reduce dynamic and active leakage power simultaneously. Search on Bibsonomy ISQED The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
32Afshin Abdollahi, Farzan Fallah, Massoud Pedram A Robust Power Gating Structure and Power Mode Transition Strategy for MTCMOS Design. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
32Kaijian Shi, Zhian Lin, Yi-Min Jiang A Power Network Synthesis Method for Industrial Power Gating Designs. Search on Bibsonomy ISQED The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
31Aida Todri, Malgorzata Marek-Sadowska Electromigration study of power-gated grids. Search on Bibsonomy ISLPED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF electromigration, power network
31Li Li, Ken Choi, Haiqing Nan Activity-Driven Fine-Grained Clock Gating and Run Time Power Gating Integration. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
31Mohammad Abdel-Majeed, Daniel Wong 0001, Murali Annavaram Warped gates: gating aware scheduling and power gating for GPGPUs. Search on Bibsonomy MICRO The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
31Karthikeyan Lingasubramanian, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating. Search on Bibsonomy PATMOS The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
30Ramon Canal, Antonio González 0001, James E. Smith 0001 Software-Controlled Operand-Gating. Search on Bibsonomy CGO The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
29Hao Xu 0010, Wen-Ben Jone, Ranga Vemuri Accurate energy breakeven time estimation for run-time power gating. Search on Bibsonomy ICCAD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
29Hao Xu 0010, Ranga Vemuri, Wen-Ben Jone Run-time Active Leakage Reduction by power gating and reverse body biasing: An eNERGY vIEW. Search on Bibsonomy ICCD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
29Andrea Calimera, Antonio Pullini, Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF layout, leakage power, insertion, standard-cell, sleep transistor
29Pietro Babighian, Luca Benini, Enrico Macii Sizing and Characterization of Leakage-Control Cells for Layout-Aware Distributed Power-Gating. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
28Youngsoo Shin, Seungwhun Paik, Hyung-Ock Kim Semicustom Design of Zigzag Power-Gated Circuits in Standard Cell Elements. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
28Harmander Deogun, Rahul M. Rao, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization. Search on Bibsonomy ISQED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
28Shih-Hung Weng, Yu-Min Kuo, Shih-Chieh Chang, Malgorzata Marek-Sadowska Timing analysis considering IR drop waveforms in power gating designs. Search on Bibsonomy ICCD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
25Eunjoo Choi, Changsik Shin, Youngsoo Shin ssr HLShbox-ssr pg: High-Level Synthesis of Power-Gated Circuits. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
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