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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 172 occurrences of 85 keywords
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Results
Found 512 publication records. Showing 512 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
131 | Fei Li 0003, Lei He 0001 |
Maximum current estimation considering power gating. |
ISPD |
2001 |
DBLP DOI BibTeX RDF |
low-power design, ATPG, power estimation, power gating |
113 | Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee |
Compilation for compact power-gating controls. |
ACM Trans. Design Autom. Electr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
Compilers for low power, balanced scheduling, power-gating mechanisms, data-flow analysis, leakage-power reduction |
111 | Chung-Yu Chang, Wei-Bin Yang, Ching-Ji Huang, Cheng-Hsing Chien |
New Power Gating Structure with Low Voltage Fluctuations by Bulk Controller in Transition Mode. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
108 | Anja Niedermeier, Kjetil Svarstad, Frank Bouwens, Jos Hulzink, Jos Huisken |
The challenges of implementing fine-grained power gating. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
leakage power minimization, analysis, power management, register-transfer-level, power modeling, power gating |
102 | Ashoka Visweswara Sathanur, Andrea Calimera, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
100 | Harmander Singh, Kanak Agarwal, Dennis Sylvester, Kevin J. Nowka |
Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating. |
IEEE Trans. Very Large Scale Integr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
98 | Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee |
A sink-n-hoist framework for leakage power reduction. |
EMSOFT |
2005 |
DBLP DOI BibTeX RDF |
balanced scheduling, compilers for low power, power-gating mechanisms, data-flow analysis, leakage power reduction |
97 | Zhigang Hu, Alper Buyuktosunoglu, Viji Srinivasan, Victor V. Zyuban, Hans M. Jacobson, Pradip Bose |
Microarchitectural techniques for power gating of execution units. |
ISLPED |
2004 |
DBLP DOI BibTeX RDF |
execution units, low power, microarchitecture, power-gating |
96 | Christophe Giacomotto, Mandeep Singh, Milena Vratonjic, Vojin G. Oklobdzija |
Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
Clocked storage elements, VLSI, power consumption, flip-flops, voltage scaling, clock gating, power gating, energy optimization, MTCMOS, circuit optimization, circuit tuning, circuit analysis |
94 | Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel, Kevin Stawiasz |
Experimental measurement of a novel power gating structure with intermediate power saving mode. |
ISLPED |
2004 |
DBLP DOI BibTeX RDF |
system-on-a-chip (SOC) design, wake-up latency, clock gating, power gating, inductive noise, ground bounce |
85 | Jun Seomun, Insup Shin, Youngsoo Shin |
Synthesis and implementation of active mode power gating circuits. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
active leakage, active-mode power gating, low power |
80 | Hailin Jiang, Malgorzata Marek-Sadowska |
Power-Gating Aware Floorplanning. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
80 | Hailin Jiang, Malgorzata Marek-Sadowska, Sani R. Nassif |
Benefits and Costs of Power-Gating Technique. |
ICCD |
2005 |
DBLP DOI BibTeX RDF |
|
79 | Enrico Macii, Letícia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Massimo Poncino |
Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits. |
DSD |
2008 |
DBLP DOI BibTeX RDF |
|
78 | Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel |
Understanding and minimizing ground bounce during mode transition of power gating structures. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
system-on-a-chip (SOC) design, wake-up latency, clock gating, power gating, inductive noise, ground bounce |
77 | Aida Todri, Malgorzata Marek-Sadowska, Shih-Chieh Chang |
Analysis and optimization of power-gated ICs with multiple power gating configurations. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
72 | Deepa Kannan, Aviral Shrivastava, Vipin Mohan, Sarvesh Bhardwaj, Sarma B. K. Vrudhula |
Temperature and Process Variations Aware Power Gating of Functional Units. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
70 | Hailin Jiang, Malgorzata Marek-Sadowska |
Power gating scheduling for power/ground noise reduction. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
scheduling, power gating, power supply noise |
69 | Yi-Ping You, Chingren Lee, Jenq Kuen Lee |
Compilers for leakage power reduction. |
ACM Trans. Design Autom. Electr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
Compilers for low power, power-gating mechanisms, leakage-power reduction |
69 | Nainesh Agarwal, Nikitas J. Dimopoulos |
Automated Power Gating of Registers Using CoDeL and FSM Branch Prediction. |
SAMOS |
2007 |
DBLP DOI BibTeX RDF |
|
66 | Philip Teichmann, Jürgen Fischer, Stephan Henzler, Ettore Amirante, Doris Schmitt-Landsiedel |
Power-Clock Gating in Adiabatic Logic Circuits. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
66 | Andrea Calimera, Enrico Macii, Massimo Poncino |
NBTI-aware power gating for concurrent leakage and aging optimization. |
ISLPED |
2009 |
DBLP DOI BibTeX RDF |
aging, leakage, power-gating, nbti |
66 | Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
A Scalable Algorithmic Framework for Row-Based Power-Gating. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
64 | Hyung-Ock Kim, Youngsoo Shin, Hyuk Kim, Iksoo Eo |
Physical design methodology of power gating circuits for standard-cell-based design. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
low power, leakage current, power gating |
64 | Jungseob Lee, Nam Sung Kim |
Optimizing throughput of power- and thermal-constrained multicore processors using DVFS and per-core power-gating. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
multicore processor, DVFS, power gating |
63 | Seungwhun Paik, Youngsoo Shin |
Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
sleep vector, zigzag power gating, low power, leakage current, standard-cell |
63 | Liangpeng Guo, Yici Cai, Qiang Zhou 0001, Le Kang, Xianlong Hong |
A novel performance driven power gating based on distributed sleep transistor network. |
ACM Great Lakes Symposium on VLSI |
2008 |
DBLP DOI BibTeX RDF |
physical design, power-gating, sleep transistors |
59 | Aida Todri, Shih-Chieh Chang, Malgorzata Marek-Sadowska |
Electromigration and voltage drop aware power grid optimization for power gated ICs. |
ISLPED |
2007 |
DBLP DOI BibTeX RDF |
power supply grid, power gating, electromigration |
56 | Hsiang-Hui Huang, Ching-Hwa Cheng |
Using Clock-Vdd to Test and Diagnose the Power-Switch in Power-Gating Circuit. |
VTS |
2007 |
DBLP DOI BibTeX RDF |
|
56 | Yan Lin 0001, Fei Li 0003, Lei He 0001 |
Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
56 | Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi |
Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
gate leakage current, nanometer-scale CMOS circuits, supply switching, ground collapse, standard-cell elements, 45 nm, 65 nm, power gating, subthreshold leakage current, 90 nm |
55 | Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
54 | Magnus Själander, Mindaugas Drazdziulis, Per Larsson-Edefors, Henrik Eriksson |
A low-leakage twin-precision multiplier using reconfigurable power gating. |
ISCAS (2) |
2005 |
DBLP DOI BibTeX RDF |
|
53 | Anita Lungu, Pradip Bose, Alper Buyuktosunoglu, Daniel J. Sorin |
Dynamic power gating with quality guarantees. |
ISLPED |
2009 |
DBLP DOI BibTeX RDF |
execution units, low power, power management, microarchitecture, power gating |
53 | Juan Chen 0001, Yong Dong, Huizhan Yi, Xuejun Yang |
Power Consumption Analysis of Embedded Multimedia Application. |
ICESS |
2005 |
DBLP DOI BibTeX RDF |
|
53 | Charbel J. Akl, Rafic A. Ayoubi, Magdy A. Bayoumi |
An effective staggered-phase damping technique for suppressing power-gating resonance noise during mode transition. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
|
53 | Ku He, Rong Luo, Yu Wang 0002 |
A power gating scheme for ground bounce reduction during mode transition. |
ICCD |
2007 |
DBLP DOI BibTeX RDF |
|
53 | Changbo Long, Jinjun Xiong, Yongpan Liu |
Techniques of Power-gating to Kill Sub-Threshold Leakage. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
52 | Rahul Singh, AhReum Kim, SoYoung Kim, Suhwan Kim |
A three-step power-gating turn-on technique for controlling ground bounce noise. |
ISLPED |
2010 |
DBLP DOI BibTeX RDF |
mode transition, system-on-a-chip (SOC) design, power-gating, inductive noise, ground bounce |
52 | De-Shiuan Chiou, Shih-Hsin Chen, Shih-Chieh Chang, Chingwei Yeh |
Timing driven power gating. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
leakage current, power gating, IR drop |
51 | Mototsugu Hamada, Takeshi Kitahara, Naoyuki Kawabe, Hironori Sato, Tsuyoshi Nishikawa, Takayoshi Shimazawa, Takahiro Yamashita, Hiroyuki Hara, Yukihito Oowaki |
An automated runtime power-gating scheme. |
ICCD |
2007 |
DBLP DOI BibTeX RDF |
|
51 | Hyung-Ock Kim, Youngsoo Shin |
Analysis and optimization of gate leakage current of power gating circuits. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
50 | Seungwhun Paik, Sangmin Kim, Youngsoo Shin |
Wakeup synthesis and its buffered tree construction for power gating circuit designs. |
ISLPED |
2010 |
DBLP DOI BibTeX RDF |
wakeup synthesis, leakage, power gating |
50 | Shih-Hsu Huang, Chun-Hua Cheng |
Timing driven power gating in high-level synthesis. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
50 | Ehsan Pakbaznia, Massoud Pedram |
Design and application of multimodal power gating structures. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
|
50 | Kanak Agarwal, Kevin J. Nowka, Harmander Deogun, Dennis Sylvester |
Power Gating with Multiple Sleep Modes. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
49 | Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
Optimal sleep transistor synthesis under timing and area constraints. |
ACM Great Lakes Symposium on VLSI |
2008 |
DBLP DOI BibTeX RDF |
row-based, clustering, leakage power, power-gating, standard cell, sleep transistor |
49 | Xiaotao Chang, Mingming Zhang, Ge Zhang 0007, Zhimin Zhang, Jun Wang |
Adaptive Clock Gating Technique for Low Power IP Core in SoC Design. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
48 | Houman Homayoun, Ted H. Szymanski |
Reducing the Instruction Queue Leakage Power in Superscalar Processors. |
CCECE |
2006 |
DBLP DOI BibTeX RDF |
|
48 | Masud H. Chowdhury, Juliana Gjanci, Pervez Khaled |
Innovative power gating for leakage reduction. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
48 | Michael D. Powell, Arijit Biswas, Joel S. Emer, Shubhendu S. Mukherjee, Basit R. Sheikh, Shrirang M. Yardi |
CAMP: A technique to estimate per-structure power at run-time using a few simple parameters. |
HPCA |
2009 |
DBLP DOI BibTeX RDF |
|
48 | Anmol Mathur, Qi Wang |
Power Reduction Techniques and Flows at RTL and System Level. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
46 | Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi |
Supply Switching With Ground Collapse: Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits. |
IEEE Trans. Very Large Scale Integr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
45 | Sven Rosinger, Domenik Helms, Wolfgang Nebel |
RTL Power Modeling and Estimation of Sleep Transistor Based Power Gating. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
44 | Yi-Ping You, Chingren Lee, Jenq Kuen Lee |
Compiler Analysis and Supports for Leakage Power Reduction on Microprocessors. |
LCPC |
2002 |
DBLP DOI BibTeX RDF |
|
42 | Youngsoo Shin, Hyung-Ock Kim |
Cell-Based Semicustom Design of Zigzag Power Gating Circuits. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
41 | Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano |
Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks. |
NOCS |
2008 |
DBLP DOI BibTeX RDF |
low power, Network-on-Chip, virtual channels, NoC, DVFS, power gating |
40 | Nainesh Agarwal, Nikitas J. Dimopoulos |
Towards Automated Power Gating of Registers using CoDeL. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
40 | Mindaugas Drazdziulis, Per Larsson-Edefors, Lars J. Svensson |
Overdrive Power-Gating Techniques for Total Power Minimization. |
ISVLSI |
2007 |
DBLP DOI BibTeX RDF |
|
39 | Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano |
Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs. |
NOCS |
2010 |
DBLP DOI BibTeX RDF |
low power, Network-on-Chip, router, power gating |
39 | Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
Timing-driven row-based power gating. |
ISLPED |
2007 |
DBLP DOI BibTeX RDF |
row-based, clustering, leakage power, power-gating, standard cell, sleep transistor |
39 | Goran Panic, Daniel Dietterle, Zoran Stamenkovic |
Architecture of a Power-Gated Wireless Sensor Node. |
DSD |
2008 |
DBLP DOI BibTeX RDF |
|
39 | Soumyaroop Roy, Srinivas Katkoori, Nagarajan Ranganathan |
A Compiler Based Leakage Reduction Technique by Power-Gating Functional Units in Embedded Microprocessors. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
38 | Ahmed Youssef, Mohab Anis, Mohamed I. Elmasry |
A Comparative Study Between Static and Dynamic Sleep Signal Generation Techniques for Leakage Tolerant Designs. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
38 | Po-Tsang Huang, Shu-Wei Chang, Wen-Yen Liu, Wei Hwang |
"Green" micro-architecture and circuit co-design for ternary content addressable memory. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
38 | Jianping Hu, Hong Li, Yangbo Wu |
Low-Power Register File Based on Adiabatic Logic Circuits. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
38 | Harmander Deogun, Dennis Sylvester, Kevin J. Nowka |
Fine grained multi-threshold CMOS for enhanced leakage reduction. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
37 | Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hsien-Hsin S. Lee |
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design. |
MICRO |
2006 |
DBLP DOI BibTeX RDF |
|
37 | Fei Li 0003, Yan Lin 0001, Lei He 0001 |
Vdd programmability to reduce FPGA interconnect power. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
37 | Weiping Liao, Joseph M. Basile, Lei He 0001 |
Leakage power modeling and reduction with data retention. |
ICCAD |
2002 |
DBLP DOI BibTeX RDF |
|
37 | Wei-Chih Hsieh, Wei Hwang |
In-situ self-aware adaptive power control system with multi-mode power gating network. |
SoCC |
2008 |
DBLP DOI BibTeX RDF |
|
37 | Debanjali Nath, Priyanka Choudhury, Sambhu Nath Pradhan |
Hybrid Approach of Within-Clock Power Gating and Normal Power Gating to Reduce Power. |
J. Circuits Syst. Comput. |
2016 |
DBLP DOI BibTeX RDF |
|
36 | Enric Musoll |
A Thermal-Friendly Load-Balancing Technique for Multi-Core Processors. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
low power, hot spots, power gating, Multi-core architecture |
36 | Yung-Chia Lin, Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee, Wei-Kuan Shih, TingTing Hwang |
Energy-aware scheduling and simulation methodologies for parallel security processors with multiple voltage domains. |
J. Supercomput. |
2007 |
DBLP DOI BibTeX RDF |
Scheduling, Parallel processing, Power management, Dynamic voltage scaling, Power gating, Security processor |
36 | Kaijian Shi, David Howard |
Challenges in sleep transistor design and implementation in low-power designs. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
methodology, low-power design, power gating, sleep transistor |
36 | Cindy Eisner, Amir Nahir, Karen Yorav |
Functional Verification of Power Gated Designs by Compositional Reasoning. |
CAV |
2008 |
DBLP DOI BibTeX RDF |
|
35 | Kimiyoshi Usami, Toshiaki Shirai, Tatsunori Hashida, Hiroki Masuda, Seidai Takeda, Mitsutaka Nakata, Naomi Seki, Hideharu Amano, Mitaro Namiki, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura |
Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
35 | Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Daihan Wang |
Run-time power gating of on-chip routers using look-ahead routing. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
35 | Ehsan Pakbaznia, Farzan Fallah, Massoud Pedram |
Charge Recycling in Power-Gated CMOS Circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
35 | Weiping Liao, Joseph M. Basile, Lei He 0001 |
Microarchitecture-level leakage reduction with data retention. |
IEEE Trans. Very Large Scale Integr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Shota Ishihara, Masanori Hariyama, Michitaka Kameyama |
A low-power FPGA based on autonomous fine-grain power-gating. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
34 | Songyao Tan, Yue Yin, Hanjun Jiang, Zhihua Wang 0001 |
A 0.7-V Clock-gating Cell with Power Gating Technology and 1.56-pA Sleep Power. |
ICTA |
2020 |
DBLP DOI BibTeX RDF |
|
34 | Amit Ranjan Trivedi, Wen Yueh, Saibal Mukhopadhyay |
In Situ Power Gating Efficiency Learner for Fine-Grained Self-Adaptive Power Gating. |
IEEE Trans. Circuits Syst. II Express Briefs |
2014 |
DBLP DOI BibTeX RDF |
|
34 | Debanjali Nath, Priyanka Choudhury, Sambhu Nath Pradhan |
Power Reduction by Integrated Within_Clock_Power Gating and Power Gating (WCPG_in_PG). |
VDAT |
2013 |
DBLP DOI BibTeX RDF |
|
34 | Li Li, Ken Choi, Haiqing Nan |
Effective algorithm for integrating clock gating and power gating to reduce dynamic and active leakage power simultaneously. |
ISQED |
2011 |
DBLP DOI BibTeX RDF |
|
32 | Afshin Abdollahi, Farzan Fallah, Massoud Pedram |
A Robust Power Gating Structure and Power Mode Transition Strategy for MTCMOS Design. |
IEEE Trans. Very Large Scale Integr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
32 | Kaijian Shi, Zhian Lin, Yi-Min Jiang |
A Power Network Synthesis Method for Industrial Power Gating Designs. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Aida Todri, Malgorzata Marek-Sadowska |
Electromigration study of power-gated grids. |
ISLPED |
2009 |
DBLP DOI BibTeX RDF |
electromigration, power network |
31 | Li Li, Ken Choi, Haiqing Nan |
Activity-Driven Fine-Grained Clock Gating and Run Time Power Gating Integration. |
IEEE Trans. Very Large Scale Integr. Syst. |
2013 |
DBLP DOI BibTeX RDF |
|
31 | Mohammad Abdel-Majeed, Daniel Wong 0001, Murali Annavaram |
Warped gates: gating aware scheduling and power gating for GPGPUs. |
MICRO |
2013 |
DBLP DOI BibTeX RDF |
|
31 | Karthikeyan Lingasubramanian, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino |
Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating. |
PATMOS |
2011 |
DBLP DOI BibTeX RDF |
|
30 | Ramon Canal, Antonio González 0001, James E. Smith 0001 |
Software-Controlled Operand-Gating. |
CGO |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Hao Xu 0010, Wen-Ben Jone, Ranga Vemuri |
Accurate energy breakeven time estimation for run-time power gating. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
|
29 | Hao Xu 0010, Ranga Vemuri, Wen-Ben Jone |
Run-time Active Leakage Reduction by power gating and reverse body biasing: An eNERGY vIEW. |
ICCD |
2008 |
DBLP DOI BibTeX RDF |
|
29 | Andrea Calimera, Antonio Pullini, Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
layout, leakage power, insertion, standard-cell, sleep transistor |
29 | Pietro Babighian, Luca Benini, Enrico Macii |
Sizing and Characterization of Leakage-Control Cells for Layout-Aware Distributed Power-Gating. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
28 | Youngsoo Shin, Seungwhun Paik, Hyung-Ock Kim |
Semicustom Design of Zigzag Power-Gated Circuits in Standard Cell Elements. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
28 | Harmander Deogun, Rahul M. Rao, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka |
Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
|
28 | Shih-Hung Weng, Yu-Min Kuo, Shih-Chieh Chang, Malgorzata Marek-Sadowska |
Timing analysis considering IR drop waveforms in power gating designs. |
ICCD |
2008 |
DBLP DOI BibTeX RDF |
|
25 | Eunjoo Choi, Changsik Shin, Youngsoo Shin |
ssr HLShbox-ssr pg: High-Level Synthesis of Power-Gated Circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2009 |
DBLP DOI BibTeX RDF |
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