Search results for "pre-charge"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
95	Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian	Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	Resistive-open defects, Pre-charge circuits, Memory testing, Dynamic faults
65	Ching-Hwa Cheng, Shih-Chieh Chang, Jinn-Shyan Wang, Wen-Ben Jone	Charge Sharing Fault Detection for CMOS Domino Logic Circuits.	DFT	1999	DBLP DOI BibTeX RDF	charge sharing, cs-vulnerability, pseudo gate, ATPG, domino circuit
65	Thomas Popp, Stefan Mangard	Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints.	CHES	2005	DBLP DOI BibTeX RDF	Hardware Countermeasures, MDPL, Masking Logic, Dual-Rail Pre-Charge Logic, DPA, Side-Channel Analysis
58	Zhimin Chen, Yujie Zhou	Dual-Rail Random Switching Logic: A Countermeasure to Reduce Side Channel Leakage.	CHES	2006	DBLP DOI BibTeX RDF	Gate Level Masking, DRSL, Dual-Rail, Pre-charge, Side Channel Attacks, DPA
49	Ching-Hwa Cheng	Adaptable Voltage Scan Testing of Charge-Sharing Faults for Domino Circuits.	DFT	2002	DBLP DOI BibTeX RDF
48	Toru Akishita, Masanobu Katagi, Yoshikazu Miyato, Asami Mizuno, Kyoji Shibutani	A Practical DPA Countermeasure with BDD Architecture.	CARDIS	2008	DBLP DOI BibTeX RDF	dual-rail pre-charge logic, DPA, Binary Decision Diagram, countermeasure
48	Saleh Abdel-Hafeez, Shadi M. Harb, William R. Eisenstadt	Low-Power Content Addressable Memory With Read/Write and Matched Mask Ports.	PATMOS	2007	DBLP DOI BibTeX RDF	pre-charge, sense amplifier, 6T-cell, 8T-cell, low power, CAM
46	Luigi Dilillo, Paul M. Rosinger, Bashir M. Al-Hashimi, Patrick Girard 0001	Minimizing test power in SRAM through reduction of pre-charge activity.	DATE	2006	DBLP DOI BibTeX RDF
36	Marco Bucci, Luca Giancane, Raimondo Luzzi, Alessandro Trifiletti	Three-Phase Dual-Rail Pre-charge Logic.	CHES	2006	DBLP DOI BibTeX RDF	dual-rail logic, SABL, security, DPA
29	Benedikt Gierlichs	DPA-Resistance Without Routing Constraints?	CHES	2007	DBLP DOI BibTeX RDF	Differential Side Channel Analysis, DSCA, Masked Dual-rail Pre-charge Logic, MDPL, Gate-level masking, DRP
26	H. Dine, S. Chuang, Phillip E. Allen, Paul E. Hasler	A rail to rail, slew-boosted pre-charge buffer.	ISCAS	2006	DBLP DOI BibTeX RDF
26	Daisuke Suzuki, Minoru Saeki	Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style.	CHES	2006	DBLP DOI BibTeX RDF
26	Naeem Maroof, Bai-Sun Kong	Charge sharing write driver and half- V DD pre-charge 8T SRAM with virtual ground for low-power write and read operation.	IET Circuits Devices Syst.	2018	DBLP DOI BibTeX RDF
26	Youngil Kim, Sangsun Lee	Soft pre-charge H/V switch for charge pump with NAND flash memory using external power.	IEICE Electron. Express	2013	DBLP DOI BibTeX RDF
23	Nitin Kumar, Manoj Kumar 0005	Low Power, Ring VCO with Pre-Charge and Pre-Discharge Circuit for 4 GHz-6.1 GHz Applications in 0.18 μm CMOS.	J. Circuits Syst. Comput.	2019	DBLP DOI BibTeX RDF
23	Igor Arsovski, Akhilesh Patil, Robert M. Houle, Michael Fragano, Ramon Rodriguez, Raymond Kim, Van Butler	1.4Gsearch/s 2-Mb/mm2 TCAM Using Two-Phase-Pre-Charge ML Sensing and Power-Grid Pre-Conditioning to Reduce Ldi/dt Power-Supply Noise by 50%.	IEEE J. Solid State Circuits	2018	DBLP DOI BibTeX RDF
23	Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian	March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit.	DDECS	2006	DBLP DOI BibTeX RDF
20	Saleh Abdel-Hafeez, Shadi M. Harb, William R. Eisenstadt	A low-power CAM using a 12-transistor design cell.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
20	Sergey Romanovsky, Arun Achyuthan, Sreedhar Natarajan, Wing Leung	Leakage Reduction techniques in a 0.13um SRAM Cell.	VLSI Design	2004	DBLP DOI BibTeX RDF
20	Jung-Lin Yang, Erik Brunvand	Using dynamic domino circuits in self-timed systems.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	asynchronous circuits, domino logic, self-timed circuits
16	Yumito Aoyagi, Koji Nii, Makoto Yabuuchi, Tomotaka Tanaka, Yuichiro Ishii, Yoshiaki Osada, Takaaki Nakazato, Isabel Wang, Yu-Hao Hsu, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang	A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48-1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
16	Tae-Bin Kim, Hyun-Jin Kim, Kee-Won Kwon	Fast and Efficient Offset Compensation by Noise-Aware Pre-Charge and Operation of DRAM Bit Line Sense Amplifier.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
16	Weijie Jiang, Pouya Houshmand, Marian Verhelst, Wim Dehaene	A 16nm 128kB high-density fully digital In Memory Compute macro with reverse SRAM pre-charge achieving 0.36TOPs/mm2, 256kB/mm2 and 23. 8TOPs/W.	ESSCIRC	2023	DBLP DOI BibTeX RDF
16	Yumito Aoyagi, Makoto Yabuuchi, Tomotaka Tanaka, Yuichiro Ishii, Yoshiaki Osada, Takaaki Nakazato, Koji Nii, Isabel Wang, Yu-Hao Hsu, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang	A 3-nm 27.6-Mbit/mm2 Self-timed SRAM Enabling 0.48 - 1.2 V Wide Operating Range with Far-end Pre-charge and Weak-Bit Tracking.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
16	Hao Tian 0004, Mingzhe Wu, Yun Wei Li 0001	Capacitor Pre-Charge Method for Back-to-Back Seven-Level Hybrid Clamped Converter Without Extra Power Supply.	IEEE Trans. Ind. Electron.	2022	DBLP DOI BibTeX RDF
16	Sivaneswaran Sankar, Po-Hung Chen, Maryam Shojaei Baghini	An Efficient Inductive Rectifier Based Piezo-Energy Harvesting Using Recursive Pre-Charge and Accumulation Operation.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
16	Tzu-Hsien Yang, Yong-Hwa Wen, Chun-Kai Chiu, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai	A Pre-Charge Tracking Technique in the 40 MHz High-Speed Switching 48-to-5 V GaN-Based DC-DC Buck Converter for Reducing Large Self-Commutation Loss and Achieving a High Efficiency of 95.4%.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
16	Junji Sone, Tatsuya Sato, Shinmyo Yanagawa, Katsumi Yamada, Liwei Lin	Study of Thin Polymer pre-charge Multi point Tactile device.	VR Workshops	2022	DBLP DOI BibTeX RDF
16	Chuang Wang 0004, Yan Lu 0002, Rui Paulo Martins	A Highly Integrated 3-Phase 4: 1 Resonant Switched-Capacitor Converter With Parasitic Loss Reduction and Fast Pre-Charge Startup.	IEEE Trans. Circuits Syst. II Express Briefs	2021	DBLP DOI BibTeX RDF
16	Tzu-Hsien Yang, Chun-Kai Chiu, Yong-Hwa Wen, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai	A Pre-Charge Tracking Technique in the 40MHz High-switching 48-to-5V DC-DC Buck Converter with GaN Switches for Reducing Large Self-commutation Loss and Achieving a High Efficiency of 95.4%.	ESSCIRC	2021	DBLP DOI BibTeX RDF
16	Partha De, Udaya Parampalli, Chittaranjan Mandal 0002	Secure Path Balanced BDD-Based Pre-Charge Logic for Masking.	IEEE Trans. Circuits Syst.	2020	DBLP DOI BibTeX RDF
16	Jooyoon Kim, Jongsun Park 0001	Variation-Tolerant Separated Pre-Charge Sense Amplifier for Resistive Non-Volatile logic circuit.	ISOCC	2020	DBLP DOI BibTeX RDF
16	Jiahao Yin, Chunmeng Dou, Danian Dong, Jie Yu 0027, Xiaoxin Xu, Qing Luo, Tiancheng Gong, Lu Tai, Peng Yuan, Xiaoyong Xue, Ming Liu 0022, Hangbing Lv	A 0.75 V reference clamping sense amplifier for low-power high-density ReRAM with dynamic pre-charge technique.	IEICE Electron. Express	2019	DBLP DOI BibTeX RDF
16	Graeme Horsman, Angela King	Policing and Crime Act 2017: Changes to pre-charge bail and the impact on digital forensic analysis.	Comput. Law Secur. Rev.	2018	DBLP DOI BibTeX RDF
16	Craig LaBoda, Chris Dwyer, Alvin R. Lebeck	Exploiting Dark Fluorophore States to Implement Resonance Energy Transfer Pre-Charge Logic.	IEEE Micro	2017	DBLP DOI BibTeX RDF
16	Ashiq A. Sakib, Scott C. Smith, Sudarshan K. Srinivasan	Formal modeling and verification for pre-charge half buffer gates and circuits.	MWSCAS	2017	DBLP DOI BibTeX RDF
16	Maoxin Ren, Lang Huang 0002, Xiliang Chen, Xu Yang 0012	Pre-charge strategy of modular multilevel converters with DC fault blocking capability based on multi-capacitor submodules.	IECON	2017	DBLP DOI BibTeX RDF
16	Dongye Li, Yichao Sun, Jianfeng Zhao 0001, Zhendong Ji	Fast pre-charge strategy of a modified MMC with enhanced DC fault ride-through capability.	ISIE	2017	DBLP DOI BibTeX RDF
16	Darshana Jayasinghe, Aleksandar Ignjatovic, Sri Parameswaran	NORA: Algorithmic Balancing without Pre-charge to Thwart Power Analysis Attacks.	VLSID	2017	DBLP DOI BibTeX RDF
16	Yongan Zheng, Lili Zhou, Fan Tian, Mingxiao He, Huailin Liao	A 51-nW 32.7-kHz CMOS relaxation oscillator with half-period pre-charge compensation scheme for ultra-low power systems.	ISCAS	2016	DBLP DOI BibTeX RDF
16	Chuhong Duan, Andreas J. Gotterba, Mahmut E. Sinangil, Anantha P. Chandrakasan	Reconfigurable, conditional pre-charge SRAM: Lowering read power by leveraging data statistics.	A-SSCC	2016	DBLP DOI BibTeX RDF
16	Sahar Sarafi, Abu Khari bin A'Ain, Javad Abbaszadeh, Amin Chegini	Pre-charge solution for low-power, area-efficient SAR ADC.	IEICE Electron. Express	2015	DBLP DOI BibTeX RDF
16	Nail Etkin Can Akkaya, Burak Erbagci, Raymond Carley, Ken Mai	A DPA-resistant self-timed three-phase dual-rail pre-charge logic family.	HOST	2015	DBLP DOI BibTeX RDF
16	Partha De, Kunal Banerjee 0001, Chittaranjan A. Mandal, Debdeep Mukhopadhyay	Designing DPA Resistant Circuits Using BDD Architecture and Bottom Pre-charge Logic.	DSD	2013	DBLP DOI BibTeX RDF
16	Simone Bongiovanni, Giuseppe Scotti, Alessandro Trifiletti	Security Evaluation and Optimization of the Delay-based Dual-rail Pre-charge Logic in Presence of Early Evaluation of Data.	SECRYPT	2013	DBLP BibTeX RDF
16	Gong Chen 0002, Bo Yang 0004, Yu Zhang, Qing Dong 0002, Shigetoshi Nakatake	A 9-bit 50msps SAR ADC with pre-charge VCM -based double input range algorithm.	ACM Great Lakes Symposium on VLSI	2013	DBLP DOI BibTeX RDF
16	Simone Bongiovanni, Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti	A flip-flop implementation for the DPA-resistant Delay-based Dual-rail Pre-charge Logic family.	MIXDES	2013	DBLP BibTeX RDF
16	Marco Bucci, Luca Giancane, Raimondo Luzzi, Alessandro Trifiletti	A Flip-Flop for the DPA Resistant Three-Phase Dual-Rail Pre-Charge Logic Family.	IEEE Trans. Very Large Scale Integr. Syst.	2012	DBLP DOI BibTeX RDF
16	Vikram B. Suresh, Wayne P. Burleson	Robust metastability-based TRNG design in nanometer CMOS with sub-vdd pre-charge and hybrid self-calibration.	ISQED	2012	DBLP DOI BibTeX RDF
16	Zhimin Chen 0002, Patrick Schaumont	Virtual Secure Circuit: Porting Dual-Rail Pre-charge Technique into Software on Multicore.	IACR Cryptol. ePrint Arch.	2010	DBLP BibTeX RDF
16	Marco Bucci, Luca Giancane, Raimondo Luzzi, Giuseppe Scotti, Alessandro Trifiletti	Delay-based dual-rail pre-charge logic.	ICECS	2009	DBLP DOI BibTeX RDF
16	Daisuke Suzuki, Minoru Saeki	An Analysis of Leakage Factors for Dual-Rail Pre-Charge Logic Style.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2008	DBLP DOI BibTeX RDF
16	Retdian Agung Nicodimus, Shigetaka Takagi, Nobuo Fujii	Reduction of Bootstrapped Switch Area Consumption Using Pre-Charge Phase.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2008	DBLP DOI BibTeX RDF
16	Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan	Resistive-open defect influence in SRAM pre-charge circuits: analysis and characterization.	ETS	2005	DBLP DOI BibTeX RDF
16	Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija	Conditional pre-charge techniques for power-efficient dual-edge clocking.	ISLPED	2002	DBLP DOI BibTeX RDF	clocked storage elements, dual edge-triggered flip-flop, power consumption, clocking, clock distribution
10	Alexandre Ney, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin	A Design-for-Diagnosis Technique for SRAM Write Drivers.	DATE	2008	DBLP DOI BibTeX RDF
10	Alexandre Ney, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin	An SRAM Design-for-Diagnosis Solution Based on Write Driver Voltage Sensing.	VTS	2008	DBLP DOI BibTeX RDF	write driver, design-for-diagnosis, diagnosis, SRAM
10	Satish Anand Verkila, Siva Kumar Bondada, Bharadwaj S. Amrutur	A 100MHz to 1GHz, 0.35V to 1.5V Supply 256 x 64 SRAM Block Using Symmetrized 9T SRAM Cell with Controlled Read.	VLSI Design	2008	DBLP DOI BibTeX RDF
10	Lucas Brusamarello, Roberto da Silva, Gilson I. Wirth, Ricardo A. L. Reis	Obtaining delay distribution of dynamic logic circuits by error propagation at the electrical level.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
10	Amir Moradi 0001, Mahmoud Salmasizadeh, Mohammad T. Manzuri Shalmani	Power Analysis Attacks on MDPL and DRSL Implementations.	ICISC	2007	DBLP DOI BibTeX RDF	DRSL, MDPL, Side-Channel Attacks, DPA, flip-flop
10	Jung-Lin Yang, Erik Brunvand	Self-Timed Design with Dynamic Domino Circuits.	ISVLSI	2003	DBLP DOI BibTeX RDF
10	Kuo-Hsing Cheng, Yang-Han Lee, Wei-Chun Chang	A new robust handshake for asymmetric asynchronous micro-pipelines.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
10	Kuo-Hsing Cheng, Wei-Chun Chang, Chia Ming Tu	A Robust Handshake for Asynchronous System.	IWSOC	2003	DBLP DOI BibTeX RDF
10	Victor Varshavsky, Vyacheslav Marakhovsky	A Neuron-MOS Threshold Element with Switching Capacitors.	Fuzzy Days	2001	DBLP DOI BibTeX RDF
10	Kamran Zarrineh, R. Dean Adams, Aneesha P. Deo	Defect Analysis and Realistic Fault Model Extensions for Static Random Access Memories.	MTDT	2000	DBLP DOI BibTeX RDF