Search results for "processor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
50	Peter Pirsch, Achim Freimann, C. Klar, Jens Peter Wittenburg	Processor Architectures for Multimedia Applications.	Embedded Processor Design Challenges	2002	DBLP DOI BibTeX RDF
48	Yung-Kang Chu, I-Ling Yen, Diane T. Rover	Guiding processor allocation with estimated execution time for mesh connected multiple processor systems.	HICSS (2)	1995	DBLP DOI BibTeX RDF	estimated execution time, mesh connected multiple processor systems, mesh connected parallel architectures, multiprocessor systems design, submesh allocation strategies, two-dimensional mesh systems, estimated execution times, submesh allocation, processor allocation strategies, extensive simulations, system performance improvement, execution failures, scheduling, performance, resource allocation, parallel architectures, response time, processor scheduling, software performance evaluation, execution time, processor allocation, standard deviation, job characteristics, load conditions
46	Edwin Rijpkema, Gerben J. Hekstra, Ed F. Deprettere, Jun Ma 0011	A strategy for determining a Jacobi specific dataflow processor.	ASAP	1997	DBLP DOI BibTeX RDF	Jacobi specific dataflow processor, Jacobi algorithms, real-lime adaptive signal processing applications, quasi regularity property, dependence graph representations, exploration iteration, processor template, mapper, hierarchical exploration method, mapping efficiency, lookahead techniques, pipelining, retiming, adaptive signal processing, application domain, array processing
46	Vojin Zivojnovic, Stefan Pees, C. Schälger, Markus Willems, Rainer Schoenen, Heinrich Meyr	DSP Processor/Compiler Co-Design: A Quantitative Approach.	ISSS	1996	DBLP DOI BibTeX RDF	processor/compiler codesign, benchmarking methodology, DSPstone, fast processor simulation, SuperSim, compiled processor simulation, performance evaluation, embedded systems, digital signal processing, digital signal processing chips, LISA, top-down approach, machine description
46	Sukhamoy Som, Roland R. Mielke, John W. Stoughton	Prediction of Performance and Processor Requirements in Real-Time Data Flow Architectures.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	processor requirements, ATAMM, Algorithm to Architecture Mapping Model, multiprocessor operating system, reliableperformance, four-processor architecture, VHSIC 1750A Instruction Set Processor, iterative control, signal processing algorithms, nonpreemptive, dynamicmultiprocessor scheduling, processor requirement prediction, faulttolerant computing, real-timesystems, scheduling, performance, real-time systems, multiprocessing systems, operating systems (computers), periodic, data flow graph, data flow architectures
46	Mark I. Halpern	Programming Languages: Toward a general processor for programming languages.	Commun. ACM	1968	DBLP DOI BibTeX RDF	compiler writing system, general processor, general translator, macro instruction processor, meta compiler, meta language processor, meta language translator, meta processor, programming language processor, programming language translator, compiler-compiler, translator writing system
46	Marcus Bednara, Frank Hannig, Jürgen Teich	Generation of Distributed Loop Control.	Embedded Processor Design Challenges	2002	DBLP DOI BibTeX RDF
44	Fuji Ren	Dialogue Machine Translation System Using Multiple Translation Processors.	DEXA Workshops	2000	DBLP DOI BibTeX RDF	dialogue machine translation system, multiple translation processors, natural dialogues, irregular expressions, natural conversation, ill-formed sentences, dialogue machine translation, MTP, translation processors, original language analysis, target language generation processing, Robust Parser based Translation Processor, Example Based Translation Processor, Family Modal based Translation Processor, Super Function based Translation Processor, information analysis model, syntactic constraint analysis model, semantic constraint analysis model, robust dialogue translation, language translation
44	Rajaa S. Shindi, Shaun Cooper	Evaluate the performance changes of processor simulator benchmarks When context switches are incorporated.	SIGAda	2006	DBLP DOI BibTeX RDF	sim-alpha, cache, cpu, context switches, processor simulators
44	Jason Yu, Christopher Eagleston, Christopher Han-Yu Chou, Maxime Perreault, Guy G. Lemieux	Vector Processing as a Soft Processor Accelerator.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	parallelism, Computer architecture, embedded processor, vector processor, multimedia processing, soft processor
43	Jürgen Teich, Lothar Thiele	Exact Partitioning of Affine Dependence Algorithms.	Embedded Processor Design Challenges	2002	DBLP DOI BibTeX RDF
42	Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith 0001	A mechanistic performance model for superscalar out-of-order processors.	ACM Trans. Comput. Syst.	2009	DBLP DOI BibTeX RDF	Superscalar out-of-order processor, balanced processor design, mechanistic modeling, overprovisioned processor design, pipeline depth, pipeline width, resource scaling, wide front-end dispatch processors, performance modeling, analytical modeling
41	Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau	Aggregating processor free time for energy reduction.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	processor free time, embedded systems, aggregation, clock gating, code transformation, energy reduction
41	Samuli Aalto, Urtzi Ayesta, Sem C. Borst, Vishal Misra, Rudesindo Núñez-Queija	Beyond processor sharing.	SIGMETRICS Perform. Evaluation Rev.	2007	DBLP DOI BibTeX RDF	discriminatory processor sharing, in-sensitivity, multilevel processor sharing, workload, service differentiation, asymptotic analysis, queue length, sojourn time, generalized processor sharing, slowdown, delay minimization, size-based scheduling
41	Alan R. Shealy, Brian A. Malloy, David A. Sykes	SIMx86: An extensible simulator for the Intel 80×86 processor family.	Annual Simulation Symposium	1997	DBLP DOI BibTeX RDF	SIMx86, extensible simulator, Intel 80/spl times/86, Intel 8088 processor, 8086 processor, debugging facilities, simulator construction, virtual machines, domain model, performance gains, processor simulators
41	W. Lynn Gallagher, Chuan-lin Wu	Evaluation of a memory hierarchy for the MTS multithreaded processor.	ICPADS	1997	DBLP DOI BibTeX RDF	memory hierarchy evaluation, MTS multithreaded processor, hardware resource utilization, instruction throughput, multithreaded superscalar processor, multiple instruction streams, multiple functional unit architecture, parameter-driven simulator, SES/workbench, numerical benchmarks, memory system configurations, main memory latency, cache hit rates, realistic multilevel cache hierarchy, parallel processing, VLIW, superscalar processor, instruction cache
41	S. Krishnakumar, P. Suresh, S. Sadashiva Rao, M. P. Pareek, R. Gupta	A single chip, pipelined, cascadable, multichannel, signal processor.	VLSI Design	1995	DBLP DOI BibTeX RDF	delay lines, single chip signal processor, cascadable processor, multichannel signal processor, programmable delay line, memory mapped peripheral, online diagnostics, shadow accumulators, double metal CMOS process, 144 pin CPGA, VLSI, timing, pipeline processing, digital signal processing chips, pipelined processor, CMOS digital integrated circuits, array multipliers, DSP architecture, 2 micron
40	Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers	A Reconfigurable Functional Unit for TriMedia/CPU64. A Case Study.	Embedded Processor Design Challenges	2002	DBLP DOI BibTeX RDF
40	Georgi Kuzmanov, Stamatis Vassiliadis, Jos T. J. van Eijndhoven	A 2D Addressing Mode for Multimedia Applications.	Embedded Processor Design Challenges	2002	DBLP DOI BibTeX RDF
40	Konstantin Avrachenkov, Urtzi Ayesta, Patrick Brown 0001	Batch Arrival Processor-Sharing with Application to Multi-Level Processor-Sharing Scheduling.	Queueing Syst. Theory Appl.	2005	DBLP DOI BibTeX RDF	MX/G/1, work conservation, multi-level processor-sharing, processor-sharing, batch arrivals
38	Ching-Hsien Hsu, Yeh-Ching Chung, Don-Lin Yang, Chyi-Ren Dow	A Generalized Processor Mapping Technique for Array Redistribution.	IEEE Trans. Parallel Distributed Syst.	2001	DBLP DOI BibTeX RDF	generalized processor mapping, distributed memory multicomputers, runtime support, Array redistribution
38	Len Dekker, Edward E. E. Frietman	Optical link and processor clustering in the Delft parallel processor.	ICS	1988	DBLP DOI BibTeX RDF
38	Ed F. Deprettere, Jürgen Teich, Stamatis Vassiliadis (eds.)	Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS	Embedded Processor Design Challenges	2002	DBLP DOI BibTeX RDF
38	Vladimir D. Zivkovic, Paul Lieverse	An Overview of Methodologies and Tools in the Field of System-Level Design.	Embedded Processor Design Challenges	2002	DBLP DOI BibTeX RDF
38	Andy D. Pimentel, Simon Polstra, Frank Terpstra, A. W. van Halderen, Joseph E. Coffland, Louis O. Hertzberger	Towards Efficient Design Space Exploration of Heterogeneous Embedded Media Systems.	Embedded Processor Design Challenges	2002	DBLP DOI BibTeX RDF
38	C. John Glossner, Michael J. Schulte, Stamatis Vassiliadis	A Java-Enabled DSP.	Embedded Processor Design Challenges	2002	DBLP DOI BibTeX RDF
38	Stephan Wong, Stamatis Vassiliadis, Sorin Cotofana	Microcoded Reconfigurable Embedded Processors: Current Developments.	Embedded Processor Design Challenges	2002	DBLP DOI BibTeX RDF
38	Peter M. W. Knijnenburg, Toru Kisuki, Michael F. P. O'Boyle	Iterative Compilation.	Embedded Processor Design Challenges	2002	DBLP DOI BibTeX RDF
38	Clark N. Taylor, Debashis Panigrahi, Sujit Dey	Design of an Adaptive Architecture for Energy Efficient Wireless Image Communication.	Embedded Processor Design Challenges	2002	DBLP DOI BibTeX RDF
38	Ed F. Deprettere, Edwin Rijpkema, Bart Kienhuis	Translating Imperative Affine Nested Loop Programs into Process Networks.	Embedded Processor Design Challenges	2002	DBLP DOI BibTeX RDF
38	Henk L. Muller, Dan Page, James Irwin, David May 0001	Caches with Compositional Performance.	Embedded Processor Design Challenges	2002	DBLP DOI BibTeX RDF
38	Christian Haubelt, Jürgen Teich, Kai Richter 0001, Rolf Ernst	Flexibility/Cost-Tradeoffs of Platform-Based Systems.	Embedded Processor Design Challenges	2002	DBLP DOI BibTeX RDF
38	Patrice Quinton, Tanguy Risset	Structured Scheduling of Recurrence Equations: Theory and Practice.	Embedded Processor Design Challenges	2002	DBLP DOI BibTeX RDF	parallelization of loop nests, structured recurrence equations, automatic synthesis of parallel architectures, parallel VLSI architectures, scheduling
38	Bart Kienhuis, Ed F. Deprettere, Pieter van der Wolf, Kees A. Vissers	A Methodology to Design Programmable Embedded Systems - The Y-Chart Approach.	Embedded Processor Design Challenges	2002	DBLP DOI BibTeX RDF	Y-chart approach, Architecture Template, Stack of Y-charts, Abstraction Pyramid, Embedded Systems, Design Space Exploration
38	Dirk Desmet, Prabhat Avasare, Paul Coene, Stijn Decneut, Filip Hendrickx, Théodore Marescaux, Jean-Yves Mignolet, Robert Pasko, Patrick Schaumont, Diederik Verkest	Design of Cam-E-leon, a Run-Time Reconfigurable Web Camera.	Embedded Processor Design Challenges	2002	DBLP DOI BibTeX RDF
38	Bishnupriya Bhattacharya, Shuvra S. Bhattacharyya	Consistency Analysis of Reconfigurable Dataflow Specifications.	Embedded Processor Design Challenges	2002	DBLP DOI BibTeX RDF
36	Jonah Probell	Architecture Considerations for Multi-Format Programmable Video Processors.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	software programmable processor, hardwired processor, data tiling, SIMD, VLIW, processor architecture, multiprocessing
36	Daniel Jiménez-González, Xavier Martorell, Alex Ramírez	Performance Analysis of Cell Broadband Engine for High Memory Bandwidth Applications.	ISPASS	2007	DBLP DOI BibTeX RDF	arithmetic performance analysis, memory bandwidth application, synergistic processor element, DMA controller, direct memory access, element interconnect bus, bandwidth performance peak, processor component, message passing interface, data stream, single instruction multiple data, cell broadband engine, streaming programming model, processor speed
36	Yuichiro Miyaoka, Yoshiharu Kataoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki	Area/delay estimation for digital signal processor cores.	ASP-DAC	2001	DBLP DOI BibTeX RDF
36	Toshihiro Hattori, Takahiro Irita, Masayuki Ito, Eiji Yamamoto, Hisashi Kato, Go Sado, Tetsuhiro Yamada, Kunihiko Nishiyama, Hiroshi Yagi, Takao Koike, Yoshihiko Tsuchihashi, Motoki Higashida, Hiroyuki Asano, Izumi Hayashibara, Ken Tatezawa, Yasuhisa Shimazaki, Naozumi Morino, Yoshihiko Yasu, Tadashi Hoshi, Yujiro Miyairi, Kazumasa Yanagisawa, Kenji Hirose, Saneaki Tamaki, Shinichi Yoshioka, Toshifumi Ishii, Yusuke Kanno, Hiroyuki Mizuno, Tetsuya Yamada, Naohiko Irie, Reiko Tsuchihashi, Nobuto Arai, Tomohiro Akiyama, Koji Ohno	Hierarchical power distribution and power management scheme for a single chip mobile processor.	DAC	2006	DBLP DOI BibTeX RDF	mobile processor, partial power off, power domain, VLSI
36	Sunghyun Jee, Kannappan Palaniappan	Performance evaluation for a compressed-VLIW processor.	SAC	2002	DBLP DOI BibTeX RDF	CVLIW processor, individual instruction scheduling, VLIW, ILP
36	Jean-Paul Theis, Lothar Thiele	POM: a processor model for image processing.	ICCD	1995	DBLP DOI BibTeX RDF	POM, Periodic Operation Model, optimal mapping trajectory, bus bandwidth constraints, scheduling, real-time systems, computational complexity, image processing, image processing, parallel processing, allocation, processor architecture, processor model
36	Valentina Salapura, Michael Gschwind	Hardware/Software Co-Design of a Fuzzy RISC Processor.	DATE	1998	DBLP DOI BibTeX RDF	hardware/software co-evaluation, processor core, MIPS RISC processor, fuzzy processing, fuzzy rule evaluation, instruction set definition, performance evaluation, VHDL, logic synthesis, application specific instruction set processor (ASIP), hardware/software co-design, instruction set architecture, subword parallelism
36	Francesco Gregoretti, F. Intini, Luciano Lavagno, Roberto Passerone, Leonardo Maria Reyneri	Design and Implementation of the Control Structure of the PAPRICA-3 Processor.	PDP	1996	DBLP DOI BibTeX RDF	PAPRICA-3 processor, instruction execution, linear array processor PAPRICA-9, multi path queue structure, real-time systems, image processing, embedded systems, parallel architectures, image recognition, pipeline processing, array processor, pipeline architecture, application programs, real time image processing, control structure, image processing equipment, algorithmic efficiency
36	Michèle Dion, Tanguy Risset, Yves Robert	Resource-constrained scheduling of partitioned algorithms on processor arrays.	PDP	1995	DBLP DOI BibTeX RDF	physical processor arrays, communication capabilities, complex optimization problem, single integer linear programming problem, scheduling, computational complexity, complexity, linear programming, mapping, optimisation, processor arrays, partitioned algorithms, communication links, resource-constrained scheduling, optimal scheduling algorithms, linear processor arrays
36	C. J. Elston, D. B. Christianson, Paul A. Findlay, Gordon B. Steven	Hades-towards the design of an asynchronous superscalar processor.	ASYNC	1995	DBLP DOI BibTeX RDF	asynchronous superscalar processor, Hades, generic processor architecture, asynchronous processor design, decoupled operand forwarding, register writeback, computer architecture, logic design
35	Osamu Takahashi, Scott R. Cottier, Sang H. Dhong, Brian K. Flachs, Joel Silberman	Power-Conscious Design of the Cell Processor's Synergistic Processor Element.	IEEE Micro	2005	DBLP DOI BibTeX RDF	Synergistic processor element, power-conscious design, low power, CMOS, SPE, Cell Processor
34	Zhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson, Omar Sattari, Michael A. Lai, Jeremy W. Webb, Eric W. Work, Tinoosh Mohsenin, Bevan M. Baas	Architecture and Evaluation of an Asynchronous Array of Simple Processors.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	programmable DSP, digital signal processing, DSP, multi-core, array processor, GALS, many-core, chip multi-processor, globally asynchronous locally synchronous
34	Donald F. Towsley, C. Gary Rommel, John A. Stankovic	Analysis of Fork-Join Program Response Times on Multiprocessors.	IEEE Trans. Parallel Distributed Syst.	1990	DBLP DOI BibTeX RDF	fork-join program response times, task scheduling processor sharing, job scheduling processor sharing, system parameter values, performance evaluation, performance, multiprocessors, multiprocessing systems
34	Bharadwaj Veeravalli, Debasish Ghose, V. Mani	Optimal Sequencing and Arrangement in Distributed Single-Level Tree Networks with Communication Delays.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	optimalsequencing, distributed single-level tree networks, optimalprocessing time, single-level treearchitecture, optimal load distribution, load sequencing, processor-link arrangement, general case, computationalresults, root processor, front-end processor, optimal arrangement, resource allocation, distributed processing, distributed processing, optimisation, trees (mathematics), communication delays, distributed computing system, communication links, closed-form expressions
33	Blair Fort, Davor Capalija, Zvonko G. Vranesic, Stephen Dean Brown	A Multithreaded Soft Processor for SoPC Area Reduction.	FCCM	2006	DBLP DOI BibTeX RDF
33	Roman L. Lysecky, Frank Vahid	Design and implementation of a MicroBlaze-based warp processor.	ACM Trans. Embed. Comput. Syst.	2009	DBLP DOI BibTeX RDF	soft processor cores, FPGA, dynamic optimization, hardware/software partitioning, configurable logic, Warp processors, just-in-time (JIT) compilation
33	Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan	Online cache state dumping for processor debug.	DAC	2009	DBLP DOI BibTeX RDF	cache compression, processor debug, silicon debug, design for debug, post-silicon validation
33	Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	A low power VLIW processor generation method by means of extracting non-redundant activation conditions.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	low power, ASIP, clock gating, VLIW processor
33	Ji-Jon Sit, Rahul Sarpeshkar	A Cochlear-Implant Processor for Encoding Music and Lowering Stimulation Power.	IEEE Pervasive Comput.	2008	DBLP DOI BibTeX RDF	fine-timing information, electrode stimulation, analog processor, phase information, music processor, neural stimulation, low power, asynchronous, cochlear implant
33	Marco Mattavelli, Sylvain Brunetton, Daniel Mlynek	A Parallel Multimedia Processor for Macroblock Based Compression Standards.	ICIP (2)	1997	DBLP DOI BibTeX RDF	parallel multimedia processor, macroblock based compression standards, block-based video processing algorithms, DGP, digital generic processor, generic system architecture, pixel processors, RISC controller, video processing algorithms, video effects, window clipping, H.261, 1.7 GIPS, 54 MHz, 0.5 micron, code, video compression, digital filtering, MPEG-2, digital signal processing chips, H.263, SIMD architecture, MPEG-1
33	Cheng Chang, Chien-Chung Chen, Yao-Liang Chen, Fu-Shin Huang	Real-time scheduling in a programmable radar signal processor.	RTCSA	1997	DBLP DOI BibTeX RDF	programmable radar signal processor, parallel multi-processor architecture, real-time scheduling algorithm, digital signal processing, real-time scheduling, processing speed, radar signal processing
33	Hiroshi Fujita, Tatsuo Nakajima, Hiroshi Tezuka	A processor reservation system supporting dynamic QOS control.	RTCSA	1995	DBLP DOI BibTeX RDF	processor reservation system, dynamic QOS control, QOS values, user-level admission server, kernel support, scheduling, processor scheduling, multimedia computing, multimedia computing
33	Bret Stott, Dave Johnson 0003, Venkatesh Akella	Asynchronous 2-D discrete cosine transform core processor.	ICCD	1995	DBLP DOI BibTeX RDF	asynchronous 2-D discrete cosine transform core processor, self-timed design, CCITT compatible asynchronous DCT/IDCT processor, two-phase transition signaling, bounded delay approach, Sutherland's micropipeline, custom techniques, 2 /spl mu/ SCMOS technology, delays, discrete cosine transforms, digital signal processing chips, CMOS digital integrated circuits, standard cell, 2 micron
33	Fujio Yamaguchi	A unified approach to interference problems using a triangle processor.	SIGGRAPH	1985	DBLP DOI BibTeX RDF	determinant processor, geometry processor, interference problems, geometric modeling
33	Peter R. Cappello	Application-specific Processor Architecture: Then and Now.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	field-programmable gate array, FPGA, computer architecture, taxonomy, systolic array, processor array, application-specific processor, general-purpose processor
33	Myung Hoon Sunwoo, Soohwan Ong, Byungdug Ahn, Kyungwoo Lee	Design and Implementation of a Parallel Image Processor Chip for a SIMD Array Processor.	ASAP	1995	DBLP DOI BibTeX RDF	SIMD Array Processors, ASIC Chip, Image Processing, VLSI Design, VLSI Architectures
33	Toru Asano, Joel Silberman, Sang H. Dhong, Osamu Takahashi, Michael White, Scott R. Cottier, Takaaki Nakazato, Atsushi Kawasumi, Hiroshi Yoshihara	Low-Power Design Approach of 11FO4 256-Kbyte Embedded SRAM for the Synergistic Processor Element of a Cell Processor.	IEEE Micro	2005	DBLP DOI BibTeX RDF	11 fan-out of four, 11FO4, Synergistic Processor Element, private memory, streaming processing, Cell processor, multimedia processing, scratch pad memory
31	Krutartha Patel, Sridevan Parameswaran, Seng Lin Shee	Ensuring secure program execution in multiprocessor embedded systems: a case study.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	embedded system processors, tensilica, security, multiprocessors, code injection attacks
31	Edward D. Moreno, Sergio Takeo Kofuji	Efficiency of remote access caches in future SMP-based CC-NUMA multiprocessors: initial results.	ISPAN	1997	DBLP DOI BibTeX RDF	shared remote access cache, future SMP based CC-NUMA multiprocessors, symmetric multiprocessor nodes, future architectures, realistic hardware parameters, state of the art systems components, SPLASH-2 benchmark suite, performance application, baseline architecture, approach-1, slow network, approach-2, fast network, 32-processor system, four-processor SMP nodes, two-processor SMP nodes, multiprocessing systems, execution time, cost effectiveness
31	Clifford W. Mercer, Ragunathan Rajkumar	An interactive interface and RT-Mach support for monitoring and controlling resource management.	IEEE Real Time Technology and Applications Symposium	1995	DBLP DOI BibTeX RDF	RT-Mach, Real-Time Mach, resource management monitoring, resource management control, timing characteristics, a priori resource allocation decisions, changing user needs, operating system resource reserves, resource reservation abstraction, processor capacity reserves, rmon, processor usage display, processor reservation, reservation change requests, policy decisions, real-time systems, user interfaces, resource allocation, timing, multimedia systems, dynamic systems, interactive systems, operating systems (computers), multimedia computing, system monitoring, quality of service manager, interactive interface
31	Norman R. Howes, Alfred C. Weaver	Measurements of Ada Overhead in OSI-Style Communications Systems.	IEEE Trans. Software Eng.	1989	DBLP DOI BibTeX RDF	OSI-style communications systems, Ada model, seven-layer OSI reference model, single-processor machines, VAX 11/785, Rational 1000, expected message delay, novel model, server tasks, eight-processor Sequent Model 821, 14-processor Encore Multimax 320, Buhr model, server task model, Ada rendezvous, Ada overhead per message, parallel programming, Ada, concurrency, standards, computer networks, open systems, communications model, procedure calls
31	Chen-Yong Cher, Michael Gschwind	Cell GC: using the cell synergistic processor as a garbage collection coprocessor.	VEE	2008	DBLP DOI BibTeX RDF	BDW, SPU, explicitly managed memory hierarchies, local store, garbage collection, accelerator, SPE, coprocessor, cell, mark-sweep
31	Kyungsu Kang, Jungsoo Kim, Heejun Shim, Chong-Min Kyung	Software power estimation using IPI(inter-prefetch interval) power model for advanced off-the-shelf processor.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	IPI power model, black-box power model, prefetch power model, processor power modeling, software power estimation
31	Michael J. Schulte, John Glossner, Sanjay Jinturkar, Mayan Moudgill, Suman Mamidi, Stamatis Vassiliadis	A Low-Power Multithreaded Processor for Software Defined Radio.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	low power, wireless communication, computer architecture, multithreading, microarchitecture, Software Defined Radio, processor design
31	Kristen Accardi, Tony Bock, Frank T. Hady, Jon Krueger	Network processor acceleration for a Linux* netfilter firewall.	ANCS	2005	DBLP DOI BibTeX RDF	hybrid firewall, network firewall, prototype, throughput, network processor, netfilter
31	Phillip Krueger, Ten-Hwang Lai, Vibha A. Dixit-Radiya	ob Scheduling is More Important than Processor Allocation for Hypercube Computers.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	hypercubecomputers, scheduling, scheduling, resource allocation, hypercube, hypercube networks, job scheduling, Scan, processor allocation, performance problems
31	Sascha Uhrig, Jörg Wiese	jamuth: an IP processor core for embedded Java real-time systems.	JTRES	2007	DBLP DOI BibTeX RDF	Java execution environment, embedded system-on-a-chip implementation, virtual machine, real-time embedded system, multithreaded processor, Java processor, embedded operating system
31	Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun	Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	C compiler retargeting, embedded processor design, architecture description language, processor model, electronic system level
31	Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose	Application-specific customization of soft processor microarchitecture.	FPGA	2006	DBLP DOI BibTeX RDF	Nios, RTL generation, SPREE, FPGA, customization, embedded processor, ASIP, microarchitecture, application specific, soft processor
31	Tay-Jyi Lin, Chie-Min Chao, Chia-Hsien Liu, Pi-Chen Hsiao, Shin-Kai Chen, Li-Chun Lin, Chih-Wei Liu, Chein-Wei Jen	A unified processor architecture for RISC & VLIW DSP.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	dual-core processor, register organization, variable-length instruction encoding, digital signal processor
31	Robert Yung, Neil C. Wilhelm	Caching processor general registers.	ICCD	1995	DBLP DOI BibTeX RDF	caching processor general registers, processor cycle time requirements, small register cache, register caching, windowed-register architectures, parallel architectures, performance model, memory architecture, cache storage, register file
31	Sanjeev Setia, Mark S. Squillante, Satish K. Tripathi	Analysis of Processor Allocation in Multiprogrammed, Distributed-Memory Parallel Processing Systems.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	queueingtheory, independent jobs, multiple sequential tasks, job response time, distributed fork-joinqueueing system, processor allocation policy, bulk arrival queues, communicationoverhead, fork-join queues, modeling and analysis, scheduling, scheduling, parallel processing, parallel architectures, operating systems, shared-memory, synchronisation, shared memory systems, distributed memory systems, multiprogrammed, multiprogramming, processor allocation, distributed-memory, distributed memory, parallel processing systems, synchronization delay
31	Dipak Ghosal, Giuseppe Serazzi, Satish K. Tripathi	The Processor Working Set and Its Use in Scheduling Multiprocessor Systems.	IEEE Trans. Software Eng.	1991	DBLP DOI BibTeX RDF	processor working set, PWS, parallel program behavior, transputer-based multiprocessor machine, processor allocation strategies, static allocation policy, scheduling, scheduling, multiprocessing systems, transputers
31	J. M. Herron, J. Farley, Kendall Preston Jr., H. Sellner	A General-Purpose High-Speed Logical Transform Image Processor.	IEEE Trans. Computers	1982	DBLP DOI BibTeX RDF	peripheral processor, image processor, neighborhood transform, parallel processor, Array processing, cellular logic
29	David J. Bastyr	Nondedicated interprocessor communications discipline.	AFIPS National Computer Conference	1977	DBLP DOI BibTeX RDF
29	Ragunathan Rajkumar, Michael Gagliardi	High availability in the real-time publisher/subscriber inter-process communication model.	RTSS	1996	DBLP DOI BibTeX RDF	real time publisher/subscriber communications model, interprocess communication model, rejoins, repetitive real time processes, RT P/S model, processor membership protocol layer, periodic broadcast membership protocol, strong semantics, idempotence properties, weak interleaving needs, communication programming interface, steady state real time execution paths, multimedia dissemination applications, fault tolerant computing, distributed processing, feedback control, distributed real time systems, node failures, processor failures
29	Sekhar R. Sarukkai, Jerry C. Yan, Melisa Schmidt	Automated instrumentation and monitoring of data movement in parallel programs.	IPPS	1995	DBLP DOI BibTeX RDF	data-structure alignments, inter-processor data-structure interactions, compiler front end tools, tracking data-structure movements, NAS benchmarks, parallel programming, parallel programs, data structures, message passing, data flow analysis, software performance evaluation, program diagnostics, performance tools, message passing programs, inter-processor communications, data movement
29	Chris H. L. Moller, Gerald G. Pechanek	Architectural simulation system for M.f.a.s.t.	Annual Simulation Symposium	1996	DBLP DOI BibTeX RDF	pulse transformers, architectural simulation system, architecture verification, Mwave folded array signal transform processor, single chip scalable very long instruction word processor array, independent processes, socket mechanism, execution-unit operations, execution emulation, M.f.a.s.t. processor, parallel architectures, virtual machines, reconfigurable architectures, digital signal processing chips, instruction sets, functional models, array signal processing, simulator performance
28	Joshua Noseworthy, Miriam Leeser	Efficient use of communications between an FPGA's embedded processor and its reconfigurable logic.	FPGA	2006	DBLP DOI BibTeX RDF
28	Guilin Chen, Mahmut T. Kandemir	Optimizing inter-processor data locality on embedded chip multiprocessors.	EMSOFT	2005	DBLP DOI BibTeX RDF	chip multiprocessors, data locality, stencil computation
28	Alex C.-Y. Chang, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang	G-MAC: An Application-Specific MAC/Co-Processor Synthesizer.	DATE	2003	DBLP DOI BibTeX RDF
28	Alex Solomatnikov, Amin Firoozshahian, Ofer Shacham, Zain Asgar, Megan Wachs, Wajahat Qadeer, Stephen Richardson, Mark Horowitz	Using a configurable processor generator for computer architecture prototyping.	MICRO	2009	DBLP DOI BibTeX RDF	computer architecture prototyping, configurable/extensible processor generator, memory system architecture, reconfigurable architecture, VLSI design
28	Robert C. Hampshire, William A. Massey	A note on the event horizon for a processor sharing queue.	Queueing Syst. Theory Appl.	2008	DBLP DOI BibTeX RDF	Processor sharing queues, Diffusion limits, Dynamical queueing systems, Uniform acceleration, Virtual customers, Sojourn times, Transient behavior, Fluid limits
28	Mladen Berekovic, Tim Niggemeier	A Distributed, Simultaneously Multi-Threaded (SMT) Processor with Clustered Scheduling Windows for Scalable DSP Performance.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	clustering, distributed computing, DSP, MPEG-4, multi-threading, processor architecture, SMT
28	Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi, Nikil D. Dutt	Methodology for multi-granularity embedded processor power model generation for an ESL design flow.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	system-on-chip, embedded processor, power modeling, esl
28	Xiaodong Li, Ritu Gupta, Sarita V. Adve, Yuanyuan Zhou	Cross-component energy management: Joint adaptation of processor and memory.	ACM Trans. Archit. Code Optim.	2007	DBLP DOI BibTeX RDF	low-power design, memory, adaptive systems, processor, Energy management, performance guarantee, control algorithms
28	Alexey Kupriyanov, Dmitrij Kissler, Frank Hannig, Jürgen Teich	Efficient event-driven simulation of parallel processor architectures.	SCOPES	2007	DBLP DOI BibTeX RDF	embedded tools, simulation, modeling, processor arrays
28	Nikolay Kostadinov, Anelia Ivanova	A VHDL training model of a processor.	CompSysTech	2007	DBLP DOI BibTeX RDF	CPLD implementation, VHDL model, processor, instruction set
28	Virantha N. Ekanayake, Clinton Kelly IV, Rajit Manohar	An ultra low-power processor for sensor networks.	ASPLOS	2004	DBLP DOI BibTeX RDF	picojoule computing, sensor network processor, sensor networks, wireless, asynchronous, low-energy, event-driven
28	Minsu Choi, Nohpill Park, Fabrizio Lombardi	Hardware-Software Co-Reliability in Field Reconfigurable Multi-Processor-Memory Systems.	IPDPS	2002	DBLP DOI BibTeX RDF	Multi-Processor-Memory System, Field Reconfiguration, HW/SW Co-reliability, Modular Redundancy
28	Sunghyun Jee, Kannappan Palaniappan	Compiler Processor Tradeoffs for DISVLIW Architecture.	ISPAN	2002	DBLP DOI BibTeX RDF	Balanced Scheduling, DISVLIW, Processor architecture, ILP
28	Johan Van Praet, Dirk Lanneer, Werner Geurts, Gert Goossens	Processor modeling and code selection for retargetable compilation.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	code selection, graph instruction set graph, retargetable code generation, embedded systems, system design, retargetable compilation, processor modeling
28	T. Vinod Kumar Gupta, Purvesh Sharma, M. Balakrishnan, Sharad Malik	Processor Evaluation in an Embedded Systems Design Environment.	VLSI Design	2000	DBLP DOI BibTeX RDF	ASAP scheduler, Architecture constrained scheduler, ASIP, Processor architecture, Real-time constraints, Application profiling
28	Anteneh Alemu Abbo	An Embedded Processor for Integrated Navigation Receiver.	VLSI Design	1998	DBLP DOI BibTeX RDF	Integrated Navigation, Embedded Systems, FIR Filter, Application-Specific Processor